JPH0124269B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a signal processing display device, and more particularly to a device that digitally stores input signal waveforms and processes desired arithmetic operations using an electronic computer.

The representative conventional waveform observation device is an oscilloscope, which processes input signals analogously and displays them as a function of time on a cathode ray tube. However, with the advancement of digital technology such as electronic computers, it is now possible to sample the input signal, digitally convert it, store it, and use a computer to fast Fourier transform the stored waveform data and display it in the frequency domain. There was a strong demand for processing various mathematical operations such as differentiation, integration, averaging, and the product of two signals.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a novel signal processing and display device in which waveforms and related data can be processed by an electronic computer prior to display.

Another object of the present invention is to display the observed input signal waveform in real time using a single display device such as a cathode ray tube, and to digitally convert and store the desired waveform. An object of the present invention is to provide a novel signal processing display device that can perform mathematical calculation processing and display.

An example of the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows a block diagram of a conventional signal processing device. In the figure, a real-time signal corresponding to a single display axis is applied to input terminal 1. Block 2 represents a conventional sample and hold circuit that repeatedly samples the instantaneous value of the input waveform and holds that sample until the next sample is taken. Block 3 is a conventional analog/digital
A converter (hereinafter referred to as an A-D converter) is shown,
This converts the instantaneous waveform voltage value into digital data. This digital data is then supplied to the memory unit 4. A trigger signal obtained from the above-mentioned real-time signal is supplied to the input terminal 5.
A trigger circuit 6, which is usually a comparator, generates a trigger in response to this trigger signal. This trigger synchronizes the clock circuit 7 and outputs precisely synchronized clock pulses from this circuit 7 to the counter circuit 8.
to form address pulses to memory unit 4. Each digit derived from the real-time signal applied to terminal 1 as described above is stored in a separate memory cell. Next, the waveform information is supplied to the digital computer 9 for processing. This processed result is then supplied to a display device 10, and when the processed result is read out from the computer 9, it is visually displayed relative to the normal time axis signal.

FIG. 2 shows a general block diagram according to the invention. All blocks contain circuitry well known to those skilled in the art. It will be seen that information corresponding to the two axes of the graphic display device is simultaneously supplied to the input terminals 14, 16. This information is available for immediate display and processing. Sample and hold circuits 18 and 20 obtain samples of the instantaneous voltage values of the input signals in the manner of conventional sampling circuits. However, as discussed below, a delay strobe is used to capture data prior to triggering to allow vertical and horizontal information to be sorted simultaneously so that they are stored together as a coordinate point. The A/D converters 22, 24 then convert the sampled voltage values into corresponding digital values, the vertical information becoming the "data" to be stored in the memory unit 25, and the horizontal information becoming the "data" to be stored in the memory unit 25. “Address” that determines the location within unit 25
becomes.

The vertical and horizontal information stored in memory unit 25 can be retrieved and processed on digital computer 27 or displayed. It is also possible to return processed information from the digital computer 27 to the memory unit 25. When information is to be displayed, digital-to-analog converters (hereinafter referred to as DA converters) 28 and 30 convert the digital information into analog form. Switching circuits 32, 34 allow selection of the real signals at terminals 14, 16 or the processed signals from DA converters 28, 30. This selected signal is displayed by the display device 35.

FIG. 3 shows a detailed block diagram of a signal processing display device according to the present invention. This equipment consists of four units: an acquisition unit;
= signal extraction unit) 50, processing unit 5
1. It has a display unit 52 and an external computer 53. Acquisition unit 50 and display unit 52 can be connected to form a conventional oscilloscope. Unless otherwise noted, all blocks include conventional circuitry well known to those skilled in the art.

Each signal is obtained by a left vertical plug-in unit 60 and a right vertical plug-in unit 62 in a conventional manner, usually through probes or coaxial cables. Vertical plug-in units 60, 62 typically include attenuators and variable gain preamplifiers to provide a plurality of different deflection sensitivities. Vertical channel switch 63 connects vertical plug-in unit 60,
62 is selected to produce the vertical output signal of acquisition unit 50. The "A" horizontal plug-in 64 and the "B" horizontal plug-in 66 create a plurality of selectable time base signals or sweeps. Plug-ins 64, 66 can also have a preamplifier channel to amplify the signal to be displayed on the horizontal axis. The horizontal channel switch 67 selects the outputs of the plug-ins 64 and 66, and the acquisition unit 50
Obtain the horizontal output signal. Z-axis generator 68 generates signals that control conduction of beam current within the cathode ray tube. This Z-axis signal turns off the cathode ray tube and erases the display while the electron beam moves over a portion where information is not desired to be displayed, and then turns on the cathode ray tube again to display information. Readout circuit 69 produces alphanumeric information corresponding to the signal information on the vertical and horizontal axes. Readout information is displayed on the screen along with the displayed waveform, so
The Z-axis signal is sent to the readout circuit 69 according to the alphanumeric characters.
, the cathode ray tube can be turned off while the electron beam is deflected to and from the position.

In the processing unit 51, the vertical and horizontal signals are supplied to the display unit 52 through channel switches 71 and 72, respectively, and are supplied to the display unit 52 through the vertical sample and hold circuit 73 and the horizontal sample and hold circuit, respectively.
The signal is supplied to a hold circuit 74. Sample and hold circuits 73 and 74 extract instantaneous samples of waveform information and hold them until the next sample is extracted. Channel switch 76 is a sample
The outputs of the hold circuits 73 and 74 are selected and the selected voltage samples are supplied to the A/D converter 77. Here, the samples are converted to digital values. The A/D converter 77 also has a clock generator, which allows the sample and hold circuit 73.7
4 and a switching signal to channel switch 76 to select the vertical and horizontal samples at the appropriate times. Since the horizontal time base signal is slightly delayed relative to the vertical information due to some finite triggering and time base rise delay, the strobe to horizontal sample and hold circuit 74 is delayed by a suitable amount of time by delay line 78. As a result, the vertical information and the horizontal information are closely time-coordinated, and loss of the rising portion of the vertical information can be prevented.

The digital value of the sampled waveform is transferred from the A-D converter 77 to the core memory 8 via the bus 80.
2. As mentioned above, vertical information corresponds to "data" and horizontal information corresponds to "address". Core memory 82 can store several types of waveforms, each with alphanumeric data such as scale factors (units for each axis). This alphanumeric data is readout interface 8
3 and bus 80 to readout circuit 69
sent to and then returned to. Lead out/
Interface 83 provides compatibility between the analog devices of acquisition unit 50 and the digital devices of processing unit 51, and therefore includes the necessary converters.

Data from core memory 82 is supplied to external computer 53 via bus 80 and input/output interface 85. After processing by this computer, the data can be returned to the core memory 82 via the same route. Core memory 82 has additional capacity to store special information from the computer, such as messages to be read out on a display screen.

The front panel logic circuit 8 provides instructions to the external computer and controls the supply of all signals in the device.
6, this logic circuit 86 allows a direct interface between the user and the device. Acting in conjunction with the front panel control, front panel logic circuitry 86 generates control signals to select display signal sources from acquisition unit 50 and/or memory 82 and from within processing unit 51. select the data manipulation, such as storage, retention, supply to or reception from the computer, select the storage location of the waveform and its associated data, and select the computer program that will perform the desired action. This selected action provides these control signals to the appropriate circuits. Priority logic circuit 88 monitors the traffic on bus 80 and selects in turn each circuit that requires communication to bus 80, thereby allowing only one relevant piece of information to pass at a time.

The signal reproduced for display is stored in the core memory 82.
is sent to the display generator 90 via the bus 80. The circuit of this display generator 90 is
It is stated in Publication No. 38854. This generator 9
At 0, the digital value of the signal is converted to analog form using vector techniques. The vertical and horizontal signals are recovered from the waveforms and sent to the display unit 52 via channel switches 71 and 72, respectively.

Z-axis logic 92 receives inputs from Z-axis generator 68, front panel logic 86, and display generator 90, respectively, and produces a Z-axis signal corresponding to the waveform to be displayed. The Z-axis signal is supplied to a display unit 52 to create an appropriate display brightness. Depending on the Z-axis signal, the display or a portion thereof can be made to have different brightness, eg, dark, dim, normal, bright, etc. Z
Axis logic circuit 92 also includes channel switch 71,
72 to ensure that the appropriate signal is sent to display unit 52. Additionally, the detection signal is provided to an A/D converter 77 to avoid storing information sampled between sweeps.

The display unit 52 includes a vertical amplifier 95, a horizontal amplifier 96, a Z-axis amplifier 97, and a display device 99. Amplifiers 95 and 96 are conventional push-pull amplifiers that amplify the vertical and horizontal signals from switching circuits 71 and 72 in a manner suitable for driving the deflection plates of the cathode ray tube of display 99. Readout information is sent from readout circuit 69 to these amplifiers to appropriately amplify the alphanumeric characters associated with the display. Z-axis amplifier 97 receives the Z-axis signal from Z-axis logic circuit 92 and readout circuit 69, creates a voltage level, and supplies this to the cathode ray tube grid of display device 99 to conduct its electron beam. control. In this embodiment, the display device 99 is a cathode ray tube, but it is obvious that any type of display device, such as a pen recorder, could be used.

FIG. 4 shows a block diagram of the sampling device according to the present invention, and the waveforms of corresponding parts are shown in the operational waveform diagram of FIG. 5. The input signal for FIG. 5a is supplied to the input terminal 100 of FIG. 4, and this signal is amplified to an appropriate magnitude by an amplifier 101. This amplifier 101 may be a vertical amplifier in a conventional oscilloscope. Amplifier 101 for the trigger signal
5b and supplies it to the trigger generator 102, where the trigger shown in FIG. 5b is obtained. This trigger is applied to the time axis generator 103, which is a normal sweep circuit, and after a certain period of time, the time axis sweep sawtooth wave begins to rise linearly. This time axis signal waveform is shown in FIG. 5C. Each sample/hold circuit 1
05 and 106 are constituted by sampling diodes and storage capacitors. The strobe circuit 108 generates a sampling strobe at a predetermined period, but this period is arbitrary with respect to the vertical signal and the time axis signal. The sampling shown in Figure 5d.
A strobe is simultaneously supplied to vertical sample and hold circuit 105 and delay circuit 109. After the delay period, the strobe shown in FIG. 5e is applied to the horizontal sample and hold circuit 106. This delayed sampling strobe eliminates the need for a vertical delay line or pre-trigger time base signal. This output sample is available at output terminals 111,112.

It should be noted that, although the above description has been made regarding only one preferred embodiment of the present invention, various changes and changes can be made by those skilled in the art without departing from the gist of the present invention.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a signal processing device according to the prior art, FIG. 2 is a general block diagram of a signal processing display device according to the present invention, FIG. 3 is a detailed block diagram of the present invention, and FIG. 4 is a block diagram according to the present invention. FIG. 5 is a block diagram of the sampling device, and is a waveform diagram for explaining the operation showing the strobe timing of the sampling device of FIG. In the figure, 52 is a display unit, 53 is an external computer, 60 is a left vertical plug-in unit, 6
2 is the right vertical plug-in unit, 64 is “A”
Horizontal plug-in, 66 is "B" horizontal plug-in,
71 and 72 are channel switches, 73 and 7 respectively.
4 are vertical and horizontal sample and hold circuits, respectively;
82 is a core memory, 90 is a display generator, 60, 62, 64 and 66 are first devices, 7
3, 74, 77 and 82 are second devices, 52, 7
1, 72 and 90 constitute a third device, respectively.

Claims (1)

[Claims] 1. A first device that adjusts the input signal amplitude and generates a time-domain sawtooth wave in synchronization with the input signal;
a second device that samples, digitally converts, and stores the input signal and sawtooth wave voltage from the first device; an electronic computer that mathematically processes the data stored in the second device; a third device that converts the storage output of the device and the calculation output of the electronic computer into an analog voltage and selectively displays it together with the output of the first device, the third device converting the real time output from the first device; A signal processing display device capable of selectively displaying a signal waveform, a memory waveform stored in the second device, and data processed by the computer.