KR200141858Y1 - Digital scan conversion device for radar indicator - Google Patents

Abstract

The present invention is a scan timing control unit including an alignment control unit for generating an address for reading X, Y up / down and azimuth control data, etc. in a scanning converter of a radar display machine, and an XCK for XY conversion based on azimuth data. In addition, the target video data including the XY conversion unit generating the YCK is alternately recorded and read to the XCK and YCK in two timed memories, and the scan address control unit for controlling the XY conversion is integrated in each EPLD. It consists of 2 Retimed memory to store the target and 1 PROM to convert sin / cos value to XY value, and converts the radar target information input as R-θ value to XY coordinate value. It is a function to write and read according to the corresponding pixel in the range of TV monitor type display device in the direction of RANGE, and the image of the target stored in the memory to XY coordinate type memory. A radar target by implementing a function to be registered so generated for the number range of the target pixel X-Y axis, an address in the form as it viewed in PPI in time before the video is to be able to see on the TV monitor system before time.

Description

Digital Scan Converter of Radar Display

1 is a circuit diagram for showing R-θ information of a target in a PPI exhibitor according to the prior art.

2 is a configuration diagram of a digital scan conversion apparatus of a radar display device for converting R-θ information of a target according to the present invention into coordinates.

3 is an antenna rotation signal / transmission trigger synchronization circuit of the scan timing generator according to FIG.

4 is an operation timing diagram of an antenna rotation signal / transmit trigger synchronization circuit according to FIG.

5 is a synchronous clock (SYNC-CK) and sin / cos selection signal generation circuit diagram of a scan timing generator.

6 is a timing diagram of generating a synchronization clock (SYNC-CK) and a sin / cos selection signal.

7 is a detailed circuit diagram of an alignment control unit according to FIG. 2;

8 is a circuit diagram of a scan address control unit according to FIG. 2;

9 is a timing diagram related to the control of the timed memory according to the present invention.

10 is a circuit diagram of an XY conversion unit of the scan address control unit according to the present invention.

11 is an example of X, Y conversion to record an image in the target memory according to the present invention.

* Explanation of symbols for main parts of the drawings

100: scan timing controller 110: scan bit controller

120: gate and ram fault monitor 130: target monitor

140: scan timing generator

140a: Antenna rotation signal / transmission trigger synchronization circuit

140b: Synchronous clock (SYNC-CK) and sin / cos selection signal generator

150: array control unit 151: bit timing generator

152: offset latch 153: azimuth counter

154: current azimuth latch 155: scan conversion address latch

200: scan address control unit 210: video sampler

220: read gate generator 230: mux

240: Divider 250,260: Range counter 1,2

270: write gate generator 280: XY conversion unit

281: sin / cos data latch 282,283: summer

284,285: Latch 301: Oscillator

302: sin / cos table 303,304: timed memory

An object of the present invention is to provide a digital scan conversion apparatus for a radar display device that can apply a method of displaying the R-θ value of a radar target to a polar coordinate type PPI display device in a rectangular monitor type TV monitor display device. It is to.

The radar display unit is intended to convey distance / orientation (R-θ) information about the target to the operator. The most representative of the radar display unit is a PPI (Plan Position Indicator). The PPI places the origin of the CRT at the position of the radar, where it is synchronized with the azimuth scan of the antenna, which is then radiologically swept to shine the incoming video with the fluorescent film of the CRT. The start of the sweep is performed in synchronism with the transmission pulse of the radar, and the speed of the sweep is R / 2C (C is the propagation speed) when the display distance is R.

FIG. 1 is a circuit diagram showing R-θ information of a target in a PPI display according to the prior art. As shown in FIG. 1), the timing control circuit 2 which controls timing based on the transmission trigger signal, and the vertical and horizontal orientations of the orientation control circuit 1 based on the sweep gate control signal of the timing control circuit 2; Of the sweep generation circuit 3 for generating a sweep signal as a reference, the brightness gate control circuit 4 for luminance control based on the brightness gate control of the timing control circuit 2, and the timing control circuit 2; A range mark generating circuit 5 for generating a range mark based on range mark gate control and a video amplifying circuit 8 for amplifying a video signal based on a range mark of the range mark generating circuit 5; And a deflection circuit (6) (7) for controlling left and right deflection based on the output of the sweep generation circuit (3), deflection control of the deflection circuit (6) (7), and the luminance gate control circuit (4). And a CRT 9 for displaying the video signal of the video amplification circuit 8 on the screen based on the brightness control of the apparatus.

In the conventional PPI exhibitor, the circuit for displaying the R-θ information of the target includes a sweep gate signal, a luminance gate signal, and a distance mark gate signal when a trigger pulse synchronized with a transmission pulse is applied to the timing control circuit 2. Is generated. The sweep generation circuit 3 receives a sweep gate signal and generates a sweep signal for sweeping the vertical axis and the horizontal axis based on the vertical component cosθ and the horizontal component sinθ with respect to the antenna orientation from the orientation control generation circuit 1. These two sweep signals are amplified by the deflection circuit to drive the deflection coil of the CRT to generate a PPI sweep on the CRT.

The PPI sweep direction is determined by the relative magnitude of the two deflection currents. When a current of I1 = F (t) * cosθ and I2 = F (t) * sinθ (F (t) is a small wave function) is applied to the vertical and horizontal deflection coils, the deflection distance is equal to F (t) and the antenna The orientation of the PPI sweep indicating the orientation is θ.

On the other hand, in the CRT 9, when the PPI sweep is not performed, the electron beam is cut off by the bias voltage, and the CRT 9 does not shine. When the PPI sweep is performed, a negative luminance control signal is applied to the cathode of the CRT, which causes the CRT to shine, and when a video signal from the radar receiver is applied to the CRT grid with a positive voltage, the beam current is modulated to weaken the CRT screen. The distance / orientation information of the target is displayed.

However, such a conventional PPI indication method has a disadvantage in that it is difficult to use in a bright place because the distance / orientation information of the radar is identified by the afterglow of the fluorescent film and the refresh rate of the screen is in seconds, and the user feels fatigue easily. There is a disadvantage that can not identify the identification code and track display for the target.

The present invention aims to provide a digital scan conversion apparatus that can be applied to a TV monitor-type display. A technology for converting R-θ coordinate values into XY coordinate values by integrating main functions into two EPLDs in a conventional complex hardware configuration. Is to simplify.

The present invention integrates the main functions of the scanning converter of the radar display machine into two EPLDs, two Retimed memories for storing targets, and a PROM 1 for converting sin / cos values into XY values. Open-circuit circuit to convert information of radar target input as R-θ value into XY coordinate value, and to write and read according to the distance pixel (PIXEL) in the direction of range of TV monitor type display device, and memory It is possible to record the target image stored in the XY coordinate type memory so that the address of the XY axis can be generated during the range of the number of pixels of the target. Is achieved.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram of a digital scan converter according to the present invention. As shown in the drawing, digital video signals (DMVIDEO, DNVIDO, DJVIDO) input from a radar signal processor are subjected to XY scan conversion and input to a target memory of an exhibition machine. And an interface function to the system computer and each unit via the buses D0-D15, including a scan timing controller 100 including an ALINE controller 150 and an XY converter 280. Each of the address controller 200 includes one EPLD chip, an oscillator 301 for generating a reference clock required by the scan-timing controller 100 and the scan-address controller 200, and the scan-timing controller ( The sin / cos table 302 for generating sin / cos data based on the scan conversion address of the array control unit 150 of 100 and the video data sampled by the scan address control unit 200 are stored. It consists of two timed memories (303) (304) for mounting. Here, 'injection' in the name of the present invention is expressed as 'scan' (SCAN) in describing the present invention, which means the same meaning.

The radar target videos (DMVIDEO, DNVIDO, DJVI DO) input from the signal processor are stored in the timed memories 303 and 304 through the video sampler 210.

The reference frequency oscillated by the oscillator 301 is separated into a frequency corresponding to the laser display selection distance through the divider 240, and the frequency divided by the divider 240 is write gate generator 270 according to the selected distance. Is generated as a write gate signal, and the mux 230 selects the write gate signal or the read gate signal of the read gate generator 220. The required frequency of the read / write gate signal is selected at the MUX 230 and supplied to the range counters 1, 2 (250) and 260, and the retime based on the range counters 1, 2 (250 and 260). The video data are alternately written to the memory 303 and 304. In addition, when the read gate signal is generated by the read gate generator 220 based on the read signal RDCK input from the image processor, target data in the timed memory 303 or 304 that is not being written is read ( RMVIDEO, RNVIDO, RJVI DO) are written to the target memory.

When the TD_TRIG signal synchronized with the radar transmission signal is input and receives the antenna azimuth (the value between the heading and the north) with the offset compensation azimuth MARP, MACP signal and the bus D0-D15, the azimuth angle plus this angle is azimuth counter (153). Count), read the sin / cos data using the azimuth count value as the address of the sin / cos table 302, and scan the value corresponding to the transmission clock period to make the azimuth data the target memory address of the XY axis. When it is sent to the XY conversion unit 280 of the address control unit 200, X and Y clocks corresponding to 370 pixels of the X and Y axes appearing in the display are generated and sent to the image processor.

In addition, the azimuth (AZ) counter 153 generates an X, Y UP / DOWN signal, and becomes up and-when it becomes + based on the center point of the PPI screen generated on the display screen. At the time of down, the sector can be distinguished for each bearing.

The scan timing controller 100 includes one EPLD chip, a scan timing generator 140, a gate and ram fault monitor 120, a target monitor 130, and a target monitor 130. The scan bit controller 110 and the array control unit 150 are configured.

The scan timing generator 140, the antenna rotation signal / transmission trigger synchronization circuit 140a, the synchronization clock (SYNC-CK) and sin / cos selection signal generation circuit 140B, the antenna rotation signal / transmission trigger synchronization circuit 140A is a mux 141 that selects an antenna orientation related signal (MARP, MACP, BHM, BBP) and a transmission trigger signal TD_TRIG- input from the outside as shown in FIG. Two de-flip flops 142 and 143 composed of two stages for receiving an output signal as data and synchronizing with the clock signal RGCK of the oscillator 301, and the output of the de-flip flop 142 of the front end. An inverter 144 that inverts the signal DTRIG- and outputs the DTRIG signal, an inverter 145 that inverts the output signal DTRIG- of the de-flip flop 142, and an output of the inverter 145. And a NAND gate 146 which outputs a TRIG signal by NAND combining the output of the back-flop de-flop 143 with the NAND crab. By inverting the output of the bit 146 it is composed of an inverter 147 which outputs a signal TRIG-.

The antenna rotation signal / transmission trigger synchronizing circuit 140a selects an antenna orientation related signal (MARP, MACP, BHM, BBP) and a transmission trigger signal TD_TRIG- input from the external mux 141 through the oscillator 301. Trigger is generated at the point where TD_TRIG- falls and the time when the clock signal RGCK rises while passing through two deflip-flops D-FF to synchronize with the 22.2 MHz clock signal RGCK. Let's do it. The trigger DTRIG ends two clocks behind the clock signal RGCK. The TRIG signal is also generated at the same time, and the TRIG signal ends one clock later of the clock signal RGCK. The mux 141 is simply four 2 to 1 muxes for selecting when the bit (BITE) and the normal operation. The operation timing for this is as shown in FIG.

Meanwhile, as shown in FIG. 5, the synchronous clock SYNC-CK and the sin / cos selection signal generating circuit 104b count the TRIG signal to scan scan signals SCSEL0 and SECVEL1 and the synchronous clock SYNC_CK. A counter 148 for outputting a signal, a flip-flop FF1 for generating a signal synchronized with the trigger signal TRIG- of the falling edge, and an output of the flip-flop FF1 for a synchronization clock SYNC_CK of the counter 148. 2 flip-flops (FF2) (FF3), which generate a trigger gate signal in synchronization with the second stage, and the output of the flip-flop (FF3) and the synchronization clock (SYNC_CK) are AND-combined. And an AND gate for feeding back a control signal.

The synchronizing clock SYNC-CK and the sin / cos selection signal generating circuit 104b transmit the clock signal of the azimuth counter 153 to the array control unit 150 in synchronization with the bit timing as shown in FIG. The trigger gate (TRIGATE) signal for writing the azimuth state to the 12-bit latch is generated at any time. While the trigger gate signal is high, select signals SCSEL0 and SCSEL1 are generated to read the corresponding sin / cos values from the sin / cos table 302. If the two signals are 'low, low', the sin low bit is read. , 'High, high' reads the cos low bit, and 'low, high' reads the sin cos high bit. The timing of generating the synchronous clock SYNC_CK and the sin / cos selection signal is as shown in FIG.

In addition, as shown in FIG. 7, the alignment control unit 150 receives an offset between the heading portion of the radar and the eBook through the bus D0-D11 and records the offset into the offset latch 152 with the azimuth writing strobe. Whenever the HM signal is loaded, the offset value is loaded into the counter 153, and the offset-loaded counter 153 is bispulse (BP) synchronized with the synchronous clock (SYNC_CK) input from the scan timing generator 140. The counter state is increased to the address A0-A10 of the array and latched in the scan conversion address latch 155, and is input to the sin / cos table 302 at the time when the trigger gate (TRIGATE) signal rises. When transmitted, the sin / cos value at the release azimuth is read in three bytes in succession when the selection signals SCSEL0 and SCSEL1 are changed by SYS_CK from 0 to 2, and recorded in the latch 281 of the XY converter 280. This synchronizes the antenna rotation signal and the transmission trigger (TD_TRIG-) at 22.2 MHz to increase the azimuth counter 153 in which the offset between the radar and the north is compensated, and the initial time (D-TRIG time) at which each transmission trigger occurs. The sin / cos value of the azimuth is read at. The XY converter 280 generates an address of the target memory to synchronize with the RDCK used to read the memory.

X up / down and Y up / down of the array control unit 150 are output to the X-Y target memory to determine the up and down of the XY counter. If X up / down is '0', the X counter is up and if it is '1', it is down. This signal makes it possible to distinguish sectors by PPI orientation on the screen displayed on the display.

8 is a circuit diagram of the scan address control unit 200 and is composed of an EPLD. The range clock RNG-CK signal and the range gate R-GATE signal corresponding to the 371 pixels in the range direction are created on the CRT screen of the display device from the time when each transmission trigger occurs in the timed memory 303 or 304. Function to record the target image.

Receive RDCK (2MHz) in the image processor to generate an address for recording the polar coordinate type target image image in the timed memory 303, 304 recorded as above into the target memory of the rectangular coordinates (XY) type. It performs the function of generating the address XCK, YCK on the CY axis for the number of pixels in the display range range.

The write gate generator 270 generates address and write strobes WE1-, WE2- for recording the target image in the retimed memory 330, 304 from the time T- (DTRIG-) occurs corresponding to each transmission trigger. And an address and read enable signals OE1 and OE2 for reading data into the target memory from the memory that is not written among the two timed memories.

When the transmit trigger T- occurs, the timed memory 304 is in a writeable state, and both muxes 230 select the outputs of the write gate generators 270 and 271, and the output of the write gate generator is As selected, the timed memory 304 connects 1CK and 1CLR of the address counter 250 and 260 to R-CK and R-GATE, which are gated to R-GATE, respectively. Connect with -CI. That is, the address state of the memory is changed when the R-CK rises, and three kinds of video signals are recorded upon the rise after the fall. On the other hand, the timed memory 303 reads out three kinds of video signals already stored and writes them to the target memory whenever the address counter is increased in the section where the RD-gate is high.

A timing diagram related to the control of the timed memories 330 and 304 is illustrated in FIG. 9.

FIG. 10 is a circuit diagram of the XY conversion unit 280 of the scan address control unit 200. As shown in FIG. 10, a retime is performed by taking a weight for generating an XY clock in the sin / cos table 302 according to a corresponding azimuth value. The XY address of the target memory corresponding to the read memory (RD_GATE-1) in synchronization with the ADD_CK used to generate the address for generating the X and Y clocks required to read the memory 303 and 304 is read. Incremental to generate an address clock (XCK) (YCK) for recording a video image. The selection signals SCSEL0 and SCSEL1 of the XY-conversion portion are signals generated and input from the scan timing controller 100. The selection signals SCSEL0 and SCSEL1 are generated during the initial 72 RGCK each time a transmission trigger occurs to generate 3 bytes of X and Y clock weights at the corresponding azimuth. The output values of the sin / cos table 302 are read in bursts, and latched by the XY-conversion SC0-SC7. The XY value (SC0-SC7) of the sin / cos table 302 indicates that each of the 12-bit summers (pole ether) 282 (283) ADD_CK (RD_GATE) starts from the moment RD_GATE transitions from low to high. In this case, the generated carry output is synchronized with ADD_CK and this is XCK and YCK.

Assuming that a transmission trigger has occurred at an arbitrary azimuth angle, the video image is recorded in the timed memory 303 (304) during the R_GATE period. In addition, RDCK is generated asynchronously to read the timed memory during the RD_GATE period, and to write to the target memory of two-dimensional rectangular coordinate type. Therefore, two-dimensional X and Y addresses of the target memory must be generated, and the address is increased or decreased from the time RD_GATE is raised.

The outermost distance ring in the exhibition corresponds to 371 pixels as shown in FIG. 11 on the X and Y axes, and the size of the target memory should be at least (371 * 2) ² = 550564 bytes or more. In order to record the image in the target memory at arbitrary azimuth angle, the address of X, Y axis should be changed to 0-XA and 0-YA respectively, and it corresponds to XA = 371 * sinθ for X axis and YA = 371 * cosθ for Y axis. .

Therefore, the number of XCK and YCK that should occur during the RD_GATE period is equal to the number of XA and YA. The circuit implementing this is the circuit of the XY conversion part of FIG. 10, and generate | occur | produces XCK and YCK.

As described in detail above, according to the present invention, the brightness of the radar video drops over time in the PPI exhibition, but if the digital scan (scanning) conversion method is applied, the brightness can be kept constant until the next radar video is updated. There is. It also has the effect of storing lidar video and displaying it with high brightness. In addition, there is an effect that can leave and display information (track, identification code, symbol) about the target. In addition, there is an effect that can be applied to all the display devices using the TV monitor display.

Claims (7)

In the scanning conversion device of the radar display device, information of the radar target inputted as the R-θ value is converted into XY coordinate values, and written and read according to the distance pixel PIXEL in the direction of the range of the TV monitor display device. A scan timing controller 100 integrated in one EPLD chip, including an ALINE controller 150, and an image of a target stored in the memory to record an XY coordinate type memory in the range of the number of pixels of the target. A reference clock required by the scan address control unit 200 integrated with one EPLD chip including an XY conversion unit 280 for generating an address of an XY axis, and the scan-timing control unit 100 and the scan-address control unit 200. An oscillator 301 for generating a signal, a sin / cos table 302 for generating sin / cos data based on a scan conversion address of the alignment control unit 150 of the scan-timing control unit 100, and a scan word. It includes two retimed memories 303 and 304 for storing the video data sampled by the dress controller 200, and converts the radar target in the polar coordinate form into the rectangular coordinate form to display the PPI display image. Digital scanning converter of the radar display, characterized in that for converting to be seen in a TV monitor-type display in the form as seen. According to claim 1, The scan-timing control unit 100, the gate and ram fault monitor 120 for monitoring and controlling the gate and ram fault, the gate and ram fault monitoring control signal and data input via the bus The scan bit controller 110 for controlling the scan bit based on the target, the target monitor 130 for monitoring the target and generating a lamp driving signal, the reference frequency of the transmission trigger signal TD_TRIG- and the oscillator 301, and the scan bit. The scan timing generator 140 generates a trigger gate (TRIGATE) signal for latching the azimuth angle of the antenna, a selection signal for reading sin / cos data, and a synchronous clock based on the control data of the controller 110 to control scan timing. And azimuth data of the antenna is input through the bus under the control of the scan timing generator 140 to latch the offset of the azimuth angle. To generate an address for reading the data of the sin / cos table 302 and an array controller 150 for generating X and Y up / down signals. Digital scanning inverter of radar display. The method of claim 2, wherein the scan timing generator 140 comprises an antenna rotation signal / transmission trigger synchronization circuit 140a, a synchronization clock SYNC-CK, and a sin / cos selection signal generation circuit 140b. The antenna rotation signal / transmission trigger synchronizing circuit 140a includes a mux 141 for selecting an antenna orientation related signal (MARP, MACP, BHM, BBP) and a transmission trigger signal TD_TR IG- inputted from the outside, and the mux ( In order to generate the trigger DTRIG at the point where the TD_TRIG- falls and the time when the clock signal RGCK rises in synchronization with the clock signal RGCK of the oscillator 301 by receiving the output signal of 141 as data. Two de-flip flops 142 and 143 composed of two stages, an inverter 144 for inverting the output signal DTRIG- of the de-flip flop 142 of the preceding stage and outputting the DTRIG signal; An inverter 145 for inverting the output signal DTRIG- of the de-flop flop 142, an output of the inverter 145, and the NAND gate 146 outputs the TRIG signal by NAND combining the output of the de-flip flop 143 on the rear stage, and inverter 147 outputs the TRIG signal by inverting the output of the NAND gate 146. The synchronizing clock (SYNC-CK) and the sin / cos selection signal generating circuit 104b count the TRIG signal and output the scan selection signals SCSEL0 and SECVEL1 and the synchronizing clock SYNC_CK. And flip-flops FF1 for generating a signal synchronized with the trigger signal TRIG- of the falling edge, and the output of the flip-flops FF1 in two stages with the synchronization clock SYNC_CK of the counter 148. An AND gate which feeds the two flip-flops FF2 and FF3 for generating a trigger gate signal, the output of the flip-flop FF3, and the synchronization clock SYNC_CK into a control signal of the counter 148. And a digital scan converter of a radar display. The apparatus of claim 2, wherein the alignment controller 150 includes a bit timing generator 151 for generating a bit pulse BP synchronized with the synchronization clock SYNC_CK input from the scan timing generator 140, and a radar control device. Offset latch 152 for receiving the offset between the heading part and the e-book via bus D0-D11 and latching it with the azimuth write strobe, and counting the offset value and outputting it to addresses A0-A11, X, Y up / down Latches an azimuth counter 153 for outputting a signal, a current azimuth latch 154 for latching the current azimuth counted by the counter 153 and sending it to the bus, and a count address of the azimuth counter 153 When the trigger gate (TRIGATE) signal rises, it is transmitted to the sin / cos table 302, and the sin / cos value at the corresponding azimuth angle is selected by SCSYS0 and SCSEL1 of 0 to 2 SYS_CK. 3 bytes when changed Reading a continuous X-Y digital scanning converter of the entire radar period, characterized in that consists of the address latch 155 for writing into the latch of the conversion unit 280. The According to claim 4, X up / down, Y up / down of the arrangement control unit 150 is output to the XY target memory to determine the up and down of the XY counter, if X up / down is '0' The counter is up, and if it is '1', the counter is down, and the digital scan converting apparatus of the radar display device, characterized in that it is possible to distinguish sectors for each PPI orientation on the screen displayed on the display device by this signal. The frequency divider 240 divides the reference frequency of the oscillator 301 into a required frequency, and T- corresponding to every transmission trigger in synchronization with the divided frequency. From the time of (DTRIG-) occurrence, address generation and writing stolobs WE1- and WE2- for recording the target image are generated in the retimed memories 303 and 304, which are not recorded among the two retimed memories. A write gate generator 270 for generating the address and read enable signals OE1 and OE2 for reading data from the target memory to the target memory, a read gate generator 220 for generating a read gate signal based on the read clock RDCK, and the read The mux 230 selects the output of the gate generator 220 and the output of the write gate generator 270, and counts the output of the mux 230 to the two timed memories 303 and 304. Alternately Two range counters 250 and 260 for recording and reading the recorded target image as an image of XY coordinates, and sampling the input video data and shifting them to the two timed memories 303 and 304. The video sampler 210 and the data read from the sin / cos table 302 are latched to read the XY-converted data in the timed memory 303 and 304 based on the summation, and then the target memory is read. It is composed of one EPLD chip including an XY conversion unit 281 that generates an XCK YCK for storing in the memory. A function of recording a target image by creating a range clock RNG-CK signal and a range gate R-GATE signal corresponding to the pixels 371 in the range direction, and in the timed memories 303 and 304 as described above. Polar coordinate target image It is configured to receive the RDCK (2MHz) from the image processor and generate the address XCK and YCK of the XY axis for the number of pixels in the display range range to generate an address for recording the paper into the target memory in the form of coordinate coordinates (XY). Digital scan inverter of radar display. The method of claim 6, wherein the X and Y converters 280 are configured to generate a corresponding azimuth angle during the initial 72 RGCK every time a transmission trigger occurs based on the SCSEL0 and SCSEL1 signals generated and input from the scan timing controller 100. A sin / cos data latch 281 that reads the output value of the sin / cos table 302 in bursts of X and Y clock weights by three bytes and latches the result in the XY-conversion SC0-SC7, and the sin / cos table 302 Two summers 282 outputting XCK and YCK by synchronizing the carry output generated by ADD_CK by operating the XY value (SC0-SC7) during the ADD_CK (RD_GATE) period from the time when RD_GATE goes from low to high. 283 and two latches 284 and 285 for latching the respective values of the summers 282 and 283 and feeding them back to the summers. .