JPH01241854A - Semiconductor device - Google Patents

Abstract

PURPOSE:To set the mobility of electrons in a higher state by forming an insulating layer on a silicon substrate, recrystallizing a polysilicon layer formed thereon, and forming a gate electrode layer across a channel direction on a transistor region formed with the channel in a direction of [100]. CONSTITUTION:An insulating layer 12 is formed on a substrate 11 in a plane (100). A transistor region 31 partitioned by a LOCOS layer 14 of recrystallized polysilicon is formed on the layer 12. The direction of a facet [110] of the layer 12 is set to a parallel state to one edge of the substrate 11, and the direction of the channel of the region 13 is so set as to coincide with the direction [100] inclined at 45 deg. with respect to the direction of the facet. An insulating layer 15 is formed on the region 13, and a gate electrode layer 16 is laminated on the layer 15. The mobility of electrons and holes can be both enhanced as compared with a conventional one in which a channel is formed in a direction of a plane [110].

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention particularly relates to a semiconductor device, which is a three-dimensional IC, and a method for manufacturing the same, which utilizes anisotropy caused by stress within a molten recrystallized film.

[Prior Art] When a transistor is formed on a single crystal silicon substrate, the facet is usually set to [110], so a channel is formed along the [1101 direction] of this facet. ing. Therefore, the current flowing through the channel is directed in the [110] direction. If this is a bulk transistor, it does not matter whether the current flows in the [110] direction or the [1001 direction, since the mobility of electrons does not change.

However, SOI (Silicon On In5
When a transistor is formed on a ulator film, anisotropy in electron mobility is observed.

In other words, when a fused recrystallized layer of polysilicon, for example, is formed on an insulating film, stress will be inherent in the fused recrystallized layer due to the difference in thermal expansion characteristics between the insulating film and the polysilicon layer. Yes, for example S OS (Sil
In the case of a film (icon on 5apphire), there is a compressive stress within the film, and in the case of an SOI film, on the contrary, there is a tensile stress, and this stress causes anisotropy in the electron mobility. This is considered to be a factor that gives rise to In fact, compressive stress is inherent in the SO8 film, and it is known that this compressive stress lowers the mobility of electrons and increases the mobility of holes.

[Invention or problem to be solved] This invention was made in view of the above points, and it is a three-dimensional IC that can be configured to have a higher electron mobility. The present invention aims to provide a semiconductor device and a method for manufacturing the same.

[Means for Solving the Problems] That is, in the semiconductor device according to the present invention, an insulating layer is formed on the surface of a single crystal silicon substrate, and a polysilicon layer is formed on the insulating layer. This polysilicon layer is recrystallized and its facets [10
The transistor region is set so that a channel is formed along the direction [0]. A gate electrode layer is formed so as to intersect with the direction of the channel.

[Function] In a semiconductor device configured as described above, [
The source and drain are formed along the [100] direction, and the channel is formed along the [1001] direction. In this way, compared to the conventional method in which channels are formed in the direction of facets [1, 10], the mobility of electrons and holes can be reduced by 3.
It can be increased by about 0%, and good operating characteristics can be obtained.

[Embodiments of the invention] Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

1 and 2 show the state of the structure, in which an insulating layer 12 made of, for example, 5j02 is formed on the surface of a (100) silicon substrate 11. and,
A transistor region 13 made of recrystallized polysilicon is formed on this insulating layer 12, and this transistor region 13 is divided into 14 main sections by LOCO3 layers 14.

In this case, the direction of the facet [110] of the insulating layer 12 is set parallel to one edge of the silicon substrate 11, whereas the direction of the channel of the transistor region 13 is set parallel to the one edge of the silicon substrate 11. Facet [110]
It is set to match the [100] direction which is inclined at 45 degrees with respect to the direction of .

Then, an insulating layer 15 is formed on this transistor region 13, and a gate electrode layer 16 is further laminated on this insulating layer 15. In this case, the gate electrode 16 is formed so as to overlap the n- region formed in the polysilicon layer constituting the transistor region 13 and to extend perpendicularly to the channel direction of the transistor region 13. On both sides of the region, p+ regions are set as a source region and a drain region, respectively.

That is, in the semiconductor device configured in this manner, the pn junction of the transistor region 13 is formed in a state aligned with the [1001 direction,
The electron mobility in the [100] direction is set in other directions, especially in the channel direction in normal semiconductor devices.
1.10] direction is set sufficiently high.

Specifically, when the channel direction is [110] (
(parallel to the normal facet direction), 1 in the p-channel
50cJ/Vs, 4500♂/V for n channel
s, but if you have a channel in the facet [100] direction, the p channel is 195c♂/VsXn channel is 550c♂/V
It becomes s.

3A to 3F sequentially show the manufacturing process of the semiconductor device as described above. First, as shown in FIG. 3A, for example, a
An insulating layer 12 made of a silicon oxide film is formed to a thickness of μm. In this case, the seed portion 121 is formed by appropriate etching.

On this insulating layer 12, a polysilicon film 21 is deposited to a thickness of, for example, 0.4 μm. This polysilicon film 21 is melted and recrystallized using, for example, a halogen lamp or a laser beam, and As shown in Figure C, an 801 layer 22 for forming a transistor is formed. When forming such an SOI layer 22, the silicon substrate 1
Due to the difference in coefficient of thermal expansion between SOI layer 22 and polysilicon, stress is generated inside SOI layer 22. For example, the substrate 11
The facet [110] direction is set parallel to the edge of 1 of the facet.

Next, for example, p
This is to form a channel transistor, and as shown in the third diagram, the 801 layer 22 is heated at 150 KeV with 10
15 phosphorus ions are implanted to make this SOI layer 22 into a 0-person shape.

Once the n-type 801 layer 22 is formed in this way, the portions other than the transistor formation region are oxidized with LOGO8 as shown in FIG. Be compartmentalized. In this case, as shown in FIG. 4A, the channel of the transistor is set to coincide with the [100 direction] which is inclined by 45 degrees with respect to the [110] direction.

In this case, it may be set so that it is parallel to the facet direction or []OO], and in this case, as in the case of forming a normal transistor, the channel of the transistor region The direction is 1 of the substrate 11
The transistor regions can be set up in the usual way so that they are parallel to the two edges.

In this way, once the transistor region 13 is set so that the channel direction is set in the [100] direction, the gate oxidation of the 801 layer 22 of this transistor region 13 is performed as shown in FIG. 3F. Then, a gate oxide film 15 is formed. Then, on this gate oxide film 15, a gate electrode layer 16 is formed of polysilicon, for example, and this gate electrode layer 16 is formed in a direction perpendicular to the channel direction of the transistor region 13, as shown in FIG. It is formed so as to extend to.

Once the gate electrode layer 16 is formed in this way,
60 K e V % 10'' dose holonno ions are implanted to form p+ type source region 131 and drain region 13 located on both sides of gate electrode layer 16, respectively.
form 2.

Once the transistor section is constructed in this way, an interlayer insulating layer 23 is formed using 9,000 BPSG, for example, and contact holes are formed by etching corresponding to the source region 131 and drain region 132, and the contact hole portions are formed by etching. This semiconductor device is completed by forming aluminum interconnections 24 and 25.

In the above embodiments, an insulating layer is formed on a single crystal silicon substrate and a polysilicon layer is formed on this insulating layer, or a polysilicon layer is formed on a simple insulating substrate. It can be implemented in the same way even if

[Effects of the Invention] As described above, in the semiconductor device according to the present invention, the direction of the channel of the 5OI) transistor to be formed, or [
100] direction.

In this way, the electron mobility is approximately 30% higher than when the channel is set in the normal [110] direction.
It has been confirmed through experiments, etc. that the degree of Therefore, in a semiconductor device constructed in this way, a transistor is constructed in a state where the stress anisotropy existing in the molten recrystallized film is effectively utilized. This makes it possible to easily and reliably obtain a three-dimensional IC with good operating characteristics.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a planar configuration of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a cross-sectional configuration diagram of a portion corresponding to the line ■-■ in FIG. 1, and FIGS. 3F is a cross-sectional configuration diagram sequentially illustrating the manufacturing process of the semiconductor device, and FIGS. 4A and 4B are diagrams illustrating the channel direction and the state of the gate electrode in the transistor region of the semiconductor device, respectively. be. 11... Silicon substrate, 12... Insulating layer, 13...
- Transistor region, 15... Gate insulating layer, 16.
...Gate electrode, 21...Polysilicon film, 22...
・801 layer, 24.25...aluminum wiring. Applicant's representative Patent attorney Takehiko Suzue Figure 3A Figure 3B Figure 3C Figure 3E Figure 3F P+A'- Figure 3D Figure 4A @t, Figure B

Claims (1)

[Claims] Consisting of a substrate having an insulating layer on at least the surface thereof, and a semiconductor layer formed on the insulating layer and recrystallized, a channel is formed along the [100] direction of the semiconductor layer. and a gate electrode layer formed on the transistor region via an insulating layer and set to cross the channel direction, and on both sides of the gate electrode layer, the A semiconductor device characterized in that a source and a drain are formed along the [100] direction.