JPH01241156A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH01241156A
JPH01241156A JP6736588A JP6736588A JPH01241156A JP H01241156 A JPH01241156 A JP H01241156A JP 6736588 A JP6736588 A JP 6736588A JP 6736588 A JP6736588 A JP 6736588A JP H01241156 A JPH01241156 A JP H01241156A
Authority
JP
Japan
Prior art keywords
layer
base
fet
doped
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6736588A
Other languages
Japanese (ja)
Inventor
Toshiyuki Usagawa
利幸 宇佐川
Takeyuki Hiruma
健之 比留間
Shigeo Goshima
五島 滋雄
Masahiko Kawada
河田 雅彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP6736588A priority Critical patent/JPH01241156A/en
Publication of JPH01241156A publication Critical patent/JPH01241156A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Bipolar Transistors (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To make a base layer thin, to realize a high frequency as well as low base resistance and to form an FET active layer having high breakdown strength and high performance, by making the base layer have a structure where a delta-doped layer is inserted between upper and lower regions containing an extremely small amount of impurities. CONSTITUTION:A base layer consisting of n-type GaAs layers 14' and 14 and a delta-doped n<++> type GaAs layer 15 is formed so that it faces to a p-type AlXGa1-XAs emitter layer 16. Further, p-type GaAs and p<+> type GaAs collector layers 13 and 12 are formed and then, an emitter electrode 20, base electrodes 21 and 21', and collector electrodes 22 are formed. On the other hand, the delta-doped layer 15 which is inserted between thin layers 14 and 14' having low concentrated impurities is formed even as the active layer of an FET. As far as the base layer of a bipolar transistor is concerned, it is extremely thin and its resistance becomes low in this way. Thus, this device reduces base resistance and achieves a high frequency. Moreover, it is formed as the active layer of the FET so that it may have high breakdown strength and high efficiency.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、超高速、超高周波の半導体装置に係り、特に
電界効果型トランジスタとバイポーラトランジスタを同
一基板内に構成することに好適な半導体装置に関する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an ultra-high speed, ultra-high frequency semiconductor device, and in particular to a semiconductor device suitable for configuring a field effect transistor and a bipolar transistor on the same substrate. Regarding.

〔従来の技術] 最近、砒素ガリウム(GaAs)中の特定の原子PyJ
(或いは原子層に準じる層)にのみ不純物(n型又はp
型)をドープする技術を(δドープ:たとえばJapa
nese Journal of Applied P
hysics24巻Nn8 19135年ページL60
8〜L610をみよ)が開発され、電界効果型トランジ
スタの製作に応用されている。
[Prior art] Recently, a specific atom PyJ in gallium arsenide (GaAs) has been studied.
(or a layer similar to an atomic layer) contains impurities (n-type or p-type).
type) doping technique (δ doping: for example, Japa type).
nese Journal of Applied P
hysics Volume 24 Nn8 19135 Page L60
8 to L610) was developed and applied to the production of field effect transistors.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

本発明は、1)この様なδ−ドープ技術を用いて、バイ
ポーラトランジスタのベース層を形成すること、2)δ
−ドープ領域を一方ではバイポーラトランジスタのベー
ス領域に用い、他方では電界効果型トランジスタの能動
層に用いることで、同一基板にバイポーラトランジスタ
と電界効果型トランジスタを形成することが目的である
The present invention provides 1) forming a base layer of a bipolar transistor using such δ-doping technology, and 2) δ-doping.
- The purpose is to form a bipolar transistor and a field-effect transistor in the same substrate, by using the doped region on the one hand in the base region of the bipolar transistor and on the other hand in the active layer of the field-effect transistor.

δドープ技術を用いてバイポーラトランジスタのベース
層を作る目的は、極限までベース層を薄くすることにあ
る。又FET(電界効果型トランジスタ)の能動層に用
いる目的は、能動層を薄くすることでFETを高性能化
することである。
The purpose of making the base layer of a bipolar transistor using δ-doping technology is to make the base layer as thin as possible. Further, the purpose of using it in the active layer of a FET (field effect transistor) is to improve the performance of the FET by making the active layer thinner.

〔課題を解決するための手段〕[Means to solve the problem]

本発明を実現する手段をG a A s /AQGaA
sヘテロ接合を有するpnp型へテロバイポーラトラン
ジスタ(Hetero −junction Biro
lar Transistor:HBTと略記)の場合
に例を取りながら説明する(第1図(a)、(b)にそ
の断面図を示す)。
Means for realizing the present invention is GaAs /AQGaA
Hetero-junction Biro pnp type hetero bipolar transistor with s heterojunction
This will be explained using an example of a lar transistor (abbreviated as HBT) (cross-sectional views thereof are shown in FIGS. 1(a) and 1(b)).

第1図(a)、(b)  に半導体装置断面図を示す。FIGS. 1(a) and 1(b) show cross-sectional views of the semiconductor device.

p型AQxGat−xAs16エミツタ層に対し、n−
(¥はアンドープ)GaAs層14’ 、14とδドー
プされたn++GaAs層15からなるベース層が形成
され、p−GaAs13.p+GaAs12コレクタ層
が形成され、各々、エミッタ電極20、ベース電極21
.21’ コレクタ電極22暫δ−ドープ層15はFE
Tと能動層としても形成できる。即ち、第1図(b)に
断面図を示す様に、δ−ドープ層15を用いて、一方で
はFETの能動層に他方をバイポーラトランジスタのベ
ース層に用いることができる。
For p-type AQxGat-xAs16 emitter layer, n-
A base layer consisting of GaAs layers 14' and 14 (\ is undoped) and a δ-doped n++ GaAs layer 15 is formed, and p-GaAs 13. A p+GaAs 12 collector layer is formed, with an emitter electrode 20 and a base electrode 21, respectively.
.. 21' Collector electrode 22 temporary δ-doped layer 15 is made of FE
It can also be formed as an active layer. That is, as shown in the cross-sectional view in FIG. 1(b), the δ-doped layer 15 can be used on one side as an active layer of an FET and on the other as a base layer of a bipolar transistor.

即ち、バイポーラトランジスタの形成は第1図(a)と
同様に形成する。一方では、ベース層の部分14.15
.14’ を用いて、第1図(b)のFET部分に示す
様に、ソースff電極21”、ドレイン電極21″′シ
ヨツトキーゲート電極23を形成することでnチャンネ
ルFETとして用いることができる。このとき、電極2
2は基板バイアス電極となる。又、第1図(、)の様に
ベース電極21は独立に2個形成すれば、一つの素子で
pnp型HBTとしても、ジーψ多′ジョン(Junc
tion)型nチャンネルFETとしても動作する。
That is, the bipolar transistor is formed in the same manner as in FIG. 1(a). On the one hand, part 14.15 of the base layer
.. 14' can be used as an n-channel FET by forming a source ff electrode 21'', a drain electrode 21'' and a shot key gate electrode 23, as shown in the FET part of FIG. 1(b). . At this time, electrode 2
2 is a substrate bias electrode. Furthermore, if two base electrodes 21 are formed independently as shown in FIG.
tion) type n-channel FET.

以上動作原理をpnp型HBTのnチャンネルベース層
の場合について発明原理を説明したが、npn型HBT
のpチャンネルベース層の場合についても同様の識別を
することができる。
The operating principle has been explained in the case of the n-channel base layer of a pnp-type HBT.
A similar distinction can be made for the p-channel base layer.

〔作用〕[Effect]

上下Y不純物の極めて小さい領をン;さむ構造にしてい
るので、 1)バイポーラトランジスタのベース層としては、極め
て薄く、かつ、低抵抗にできるのでベース抵抗を低減で
き、高いfrを実現できる。
Since the structure is such that the upper and lower regions with very small Y impurities are sandwiched between them, 1) the base layer of a bipolar transistor can be extremely thin and have low resistance, so the base resistance can be reduced and a high fr can be achieved.

2)FETの能動層としては、非常に薄い能動層を形成
できるために、高耐圧で高性能のFETを形成すること
ができる。
2) Since a very thin active layer can be formed as the active layer of the FET, a high-performance FET with high breakdown voltage can be formed.

3)FETとバイポーラを容易に同一基板に形成できる
3) FET and bipolar can be easily formed on the same substrate.

この様にpnp型HT3 TとnチャンネルGaAsM
ESFET (或いはnpn型HB Tとpチャンネル
GaAs MESFET)を同一基板に形成することで
、たとえば特願昭61−40244に開示される技術思
想と同様な回路形式を実現できる。
In this way, pnp type HT3 T and n channel GaAsM
By forming an ESFET (or an npn-type HBT and a p-channel GaAs MESFET) on the same substrate, it is possible to realize a circuit format similar to the technical idea disclosed in Japanese Patent Application No. 61-40244, for example.

〔実施例〕〔Example〕

以下更に詳しく本発明を実施例を通して説明する。 The present invention will be explained in more detail below through examples.

実施例1 pnp型HB TとnチャンネルFETに適用した場合
の実施例を第1図(a)、(b)を用いて説明する。M
OCVD (有機金属熱分解法)を用いて、半絶縁性G
aAs基板10上又はSi基板10上にアンドープG 
a A sバッファー層11を3000人形成した後、
Mgを2X101θロー3含有するp+ GaAs 1
2を3000人tMgを1xto18■−δ程度含有す
るp−GaAs13を形成後高純度GaAs層14(ア
ンドープ層:不純物1011015a以下に通常なって
いる)を50人形成した。更にδ−ドープ法或いはAL
E法を用いてSeをI X I Q ”cn’?’@む
n+十層15を形成し、更に高純度G a A s層1
4′を150人形成した。
Embodiment 1 An embodiment in which the present invention is applied to a pnp type HBT and an n-channel FET will be described with reference to FIGS. 1(a) and 1(b). M
Using OCVD (organometallic pyrolysis), semi-insulating G
Undoped G on the aAs substrate 10 or the Si substrate 10
a After forming the buffer layer 11 of 3000 people,
p+ GaAs 1 containing Mg 2X101θ rho3
After forming p-GaAs 13 containing about 1xto18■-δ of Mg by 3,000 people, a high-purity GaAs layer 14 (undoped layer: impurity concentration is usually less than 1011015a) was formed by 50 people. Furthermore, δ-doping method or AL
Using the E method, Se is formed to form an I
150 people formed 4'.

次にMgを3 X 1018exa−”含有するp+A
QxGa+−、A s(x〜0.3) M2Sを200
0人形成し、更に、Mgを2X]019m′″3含有す
るp+GaAs層17を3000人形成した。
Next, p+A containing 3 x 1018exa-” Mg
QxGa+-, A s(x~0.3) M2S 200
Furthermore, 3000 people formed a p+GaAs layer 17 containing 2×]019m''3 of Mg.

本実施例では半導体層13.14を区別して形成したが
、これは必ずしも必要ない。
In this embodiment, the semiconductor layers 13 and 14 are formed separately, but this is not necessarily necessary.

即ち、低濃度のコレクタ層13.14が通常の様に形成
されていればよい。又、δドープ層は50人程度まで拡
がってもよい。
That is, it is sufficient if the low concentration collector layers 13 and 14 are formed in the usual manner. Further, the δ-doped layer may be extended to about 50 people.

コレクタ電極22を形成した(第1図(a))。A collector electrode 22 was formed (FIG. 1(a)).

ドレインとして用いればjunction型FETとし
ても用いることができる。
If used as a drain, it can also be used as a junction type FET.

又、F E T/HB Tを同一基板に形成した例(第
1図(b))を次に説明する。バイポーラトランジスタ
は第1図(a)と同様に形成できる。
Further, an example in which FET/HBT are formed on the same substrate (FIG. 1(b)) will be described next. A bipolar transistor can be formed in the same manner as shown in FIG. 1(a).

FETは、p型G a A s 17 、 AlGaA
s16を選択的に取り除き、その領域にソース(21′
)ドレイン(21″′)電極ショットキーゲート電極2
3を各々通常の方法で形成した。
FET is p-type GaAs 17 , AlGaA
s16 is selectively removed and the source (21'
) Drain (21″′) electrode Schottky gate electrode 2
3 were each formed in a conventional manner.

FET領域の下部にあるn型領域12は通常フローティ
ングにせずに、電位を固定するため、制御電極22を形
成する。又、コレクタ層12は、半絶縁性基板中に選択
的に形成した後、半導体層13以上の層を形成してもよ
い(例えば特開昭6O−134479)。FETとして
のしきい値電圧Vthの調整はG a A 8層14′
の膜厚を制御(エツチング或いは膜厚をかえる)するか
、δ−ドープ層のシート濃度をかえることで容易に達成
できる。
The n-type region 12 under the FET region is usually not made floating, but a control electrode 22 is formed in order to fix the potential. Further, the collector layer 12 may be selectively formed in a semi-insulating substrate, and then the semiconductor layer 13 or more layers may be formed (for example, Japanese Patent Laid-Open No. 6O-134479). Adjustment of the threshold voltage Vth as a FET is performed using the G a A 8 layer 14'
This can be easily achieved by controlling the film thickness (etching or changing the film thickness) or by changing the sheet concentration of the δ-doped layer.

たとえば、δ−ドープ層を重ね合せるという意味でδド
ープ層に準ずる層としてSi不純物濃度5X10”a1
″″♂のn+GaAs層を200人PA度形成して本実
施例のδドープ層の代りとしても良い。
For example, as a layer similar to the δ-doped layer in the sense of overlapping the δ-doped layer, the Si impurity concentration is 5×10”a1.
A ``''♂ n+GaAs layer may be formed by 200 PA steps in place of the δ-doped layer of this embodiment.

実施例2 npn型HBTの場合について説明する。Example 2 The case of an npn type HBT will be explained.

第1図(a)、(b)において、n型とn型を入れかえ
る。即ち12としてSi又はSeドープ(〜5 X 1
0”am−8)GaAs層、13としてSiを〜101
BQll’″δ程度含有する層に、δドープ層15をM
g又はBeを5 X 10 lBam−”含有する層に
、エミツタ層16として、n型AlGaAs層をSiド
ーパントを4X1017cn″″8含ませる。オーミッ
ク層17としてSiを5X10”cm−δ程度含有する
G a A s層を形成する。
In FIGS. 1(a) and 1(b), n-type and n-type are interchanged. That is, as 12, Si or Se doped (~5
0”am-8) GaAs layer, Si as 13~101
The δ-doped layer 15 is added to the layer containing approximately BQll'″δ.
The emitter layer 16 is made of an n-type AlGaAs layer containing Si dopants of 4X1017cn''8. Form a As layer.

エミッタ、ベース、コレクタ、ゲート、ソース・ドレイ
ン電極も各々P型とn型を入れかえた形で電極金属を通
常の通り選択する。
The emitter, base, collector, gate, source/drain electrodes are also selected in the usual way, with the P-type and N-type electrodes being switched.

の様なδドープ構造は、G a A s系のみならず、
InGaAs、 T n P、 InAQAs、 In
AQGaAs、 S i等でも実現できることは言うま
でもない。
δ-doped structures such as
InGaAs, TnP, InAQAs, In
It goes without saying that this can also be realized with AQGaAs, Si, etc.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、HBTのベース層をδ−ドープ層によ
り形成、又FETの能動層をδ−ドープ層として同時に
形成するので 1)ベース層を薄くでき高いfr  (〜80GHzダ
クタンス)にすることができる。
According to the present invention, the base layer of the HBT is formed as a δ-doped layer, and the active layer of the FET is simultaneously formed as a δ-doped layer, so 1) the base layer can be made thinner and have a higher fr (~80 GHz ductance); Can be done.

3)FETとHBTを容易に同一基板に形成できるので
、低消費電力で高集積超高速のLSI(大規模集積回路
)を実現できる 等の効果がある。
3) Since FETs and HBTs can be easily formed on the same substrate, there are effects such as the ability to realize highly integrated, ultra-high-speed LSIs (Large Scale Integrated Circuits) with low power consumption.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(n)、(b)は本発明の半導体装置の断面構造
図である。 12・・・高濃度コレクタ層、13・・・低濃度コレク
タ層、14′・・・高純度層、15・・・δドープ層(
ベース)、16・・・ワイドギャップ半導体層(エミッ
タ)、20・・・エミッタ電極、21.21’ ・・・
x−xTl!極、21’、21〜・・・ソース・ドレイ
ンz46.23・・・ゲート電極。 7.′
FIGS. 1(n) and 1(b) are cross-sectional structural diagrams of the semiconductor device of the present invention. 12...High concentration collector layer, 13...Low concentration collector layer, 14'...High purity layer, 15...δ doped layer (
base), 16... wide gap semiconductor layer (emitter), 20... emitter electrode, 21.21'...
x-xTl! Pole, 21', 21~...source/drain z46.23...gate electrode. 7. ′

Claims (1)

【特許請求の範囲】 1、不純物原子を単一平面内或いは、単一平面に準ずる
(数原子層〜数十原子層)原子層にドープし、該原子層
(I)の上下の少なくとも一つは不純物を故意にはドー
プしない高純度層を有する多層膜をベース層として用い
るバイポーラ型トランジスタ動作をすることを特徴とす
る半導装置。 2、特許請求の範囲第1項記載の半導体装置において、
該ベース層(I)を電界効果型トランジスタの能動層に
も用い、同一基板内に、電界効果型トランジスタ動作を
する装置とバイポーラ型動作をする装置を各々1ヶ以上
形成されていることを特徴とする半導体装置。 3、特許請求の範囲第2項記載の半導体装置電界効果ト
ランジスタのゲート電極が、ショットキー接合を形成し
て配されることを特徴とする半導体装置。
[Claims] 1. Doping impurity atoms in a single plane or in an atomic layer similar to a single plane (several atomic layers to several tens of atomic layers), at least one above and below the atomic layer (I); A semiconductor device characterized in that it operates as a bipolar transistor using a multilayer film having a high purity layer not intentionally doped with impurities as a base layer. 2. In the semiconductor device according to claim 1,
The base layer (I) is also used as an active layer of a field effect transistor, and one or more devices each having a field effect transistor operation and a bipolar type operation are formed in the same substrate. semiconductor device. 3. A semiconductor device according to claim 2, wherein the gate electrode of the field effect transistor is arranged to form a Schottky junction.
JP6736588A 1988-03-23 1988-03-23 Semiconductor device Pending JPH01241156A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6736588A JPH01241156A (en) 1988-03-23 1988-03-23 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6736588A JPH01241156A (en) 1988-03-23 1988-03-23 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH01241156A true JPH01241156A (en) 1989-09-26

Family

ID=13342913

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6736588A Pending JPH01241156A (en) 1988-03-23 1988-03-23 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH01241156A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006008689A1 (en) * 2004-07-15 2006-01-26 Koninklijke Philips Electronics N.V. Bipolar transistor and method of manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006008689A1 (en) * 2004-07-15 2006-01-26 Koninklijke Philips Electronics N.V. Bipolar transistor and method of manufacturing the same

Similar Documents

Publication Publication Date Title
US5986287A (en) Semiconductor structure for a transistor
JP3135939B2 (en) HEMT type semiconductor device
US5567961A (en) Semiconductor device
JP2604349B2 (en) Semiconductor device
JP2001217257A (en) Semiconductor device and its manufacturing method
JPH027532A (en) Laminated channel field effect transistor
US5147775A (en) Method of fabricating a high-frequency bipolar transistor
JP2001210657A (en) Semiconductor device and manufacturing method therefor
JPH11186280A (en) Bipolar transistor and manufacture thereof
JP3483716B2 (en) Semiconductor device
JP3087370B2 (en) High-speed logic circuit
Chen et al. Depletion mode modulation doped Al 0.48 In 0.52 As-Ga 0.47 In 0.53 As heterojunction field effect transistors
EP0240567B1 (en) Semiconductor device
JPH01241156A (en) Semiconductor device
JPS61147577A (en) Complementary semiconductor device
JP3087278B2 (en) Monolithic integrated circuit device
JP2626220B2 (en) Field effect transistor and method of manufacturing the same
EP0093557B1 (en) High-speed complementary semiconductor integrated circuit
EP0283878A1 (en) Field effect transistor
JP2006228784A (en) Compound semiconductor epitaxial wafer
JPS62199049A (en) Semiconductor device
JP2655594B2 (en) Integrated semiconductor device
EP0276981B1 (en) Semiconductor integrated circuit device and method of producing same
JP3006792B2 (en) Heterostructure field effect transistor
JP2911075B2 (en) Field effect transistor