JPH01241144A - Rough wiring method of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To prevent the usage of redundant wirings and excess wiring regions by conducting inter-block rough wirings once after one-timeinter-block arrangement and after rough wirings before arrangement and wirings in blocks. CONSTITUTION:A building-block type integrated circuit using a computer is designed in a hierarchy manner. Rough wiring paths among blocks 10 and terminals onto the sides of blocks 6 are set before the detailed arrangement and wirings of logic cells 1 in a block 7 are executed, and the detailed array of the cells 1 in the block 7 is determined on the basis of the result of the rough wirings. Rough wirings among the blocks 10 are performed in consideration of the positions of the array of the cells 1 in the block 7 once more. Accordingly, rough wiring paths among the blocks 10 and the positions of terminals for each block 6 can be determined without generating redundant wiring wiring regions even on viewing without the discrimination of the hierarchy of in-block 7-inter-block 10.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a general wiring method for a building block type semiconductor integrated circuit using a combinator.

(Prior Art) FIG. 8 shows a schematic configuration of a semiconductor integrated circuit chip using a general building block method.

A plurality of circuit blocks 6 are provided on the chip, and an input/output circuit area 11 is provided around a wiring area 106 between each circuit block.

The wiring area between blocks is divided into a plurality of portions 10a called channels, and wiring is often performed using a channel wiring method. In each channel, boundaries that connect only to other channels and boundaries that connect to other channels and blocks face each other. The direction connecting boundaries that connect only with other channels is called the trunk direction, and the direction perpendicular to it is called the branch direction.

Further, as shown in FIG. 9, some blocks are arranged such that cell rows 9 in which cells 1 are arranged are alternately arranged with wiring areas 7 and wired to satisfy a predetermined function.

Such a block will be tentatively called a type person block.

Each cell has a wiring pattern to perform its own logical function, but as shown in FIG. The wiring connecting the cells to 9 can freely pass through. cell l
The area where wiring has already been applied and other wiring cannot freely pass through is called a wiring prohibited area 2.

Determining the approximate wiring route means determining which part of the wiring area to pass through in order to satisfy the wiring requirements. FIG. 11 shows different schematic wiring paths that meet the same wiring requirements. In FIG. 11, the block 6 and the inter-block wiring area 10 are shown, and the wiring to the block is represented by a wiring route opening and another wiring route 62 by solid lines and dotted lines.

One layout method for semiconductor integrated circuit devices using the building block method involves first making a detailed arrangement within the block, then relative placement of each block, and then performing general and detailed wiring between the blocks (see Figure 12). (Refer to (a)), before performing detailed placement and wiring within blocks, perform relative placement of each block, determine approximate wiring between blocks and block terminal positions, and then perform placement and wiring within blocks. There are some that perform detailed wiring. (1st
(See Figure 2 (b)) According to the former, there are no external constraints when arranging and wiring blocks, so the block size can be made smaller to some extent than the latter. However, the wiring area between blocks becomes large. For example, in the example of Fig. 13, the signal line n connecting block A and block B is determined to be on the left side of the block person and the right side of block B when optimization is performed within the block (as shown in M2S diagram (a)). (Intra-block wiring is first performed, and then inter-block general wiring is then performed.) This results in redundant wiring when viewed at the chip level.

It is better to set the terminals on the right side of the block person and on the left side of block B, so that the wiring length of the signal line and the wiring area between blocks can be reduced (as shown in Figure 13 (b), after roughly wiring between blocks, Perform internal placement and wiring.)

According to the latter, the wiring length between blocks and the wiring area between blocks can be easily reduced. Furthermore, the results of optimization between blocks can be reflected in the arrangement and wiring within the block without excessively increasing the block size. However, since the terminal positions of blocks and the rough wiring between blocks are performed before the layout and wiring within the block have been decided, the wiring route is not optimal when viewed without distinction between blocks and hierarchies within the block. There are cases. (See Figure 14) In the example of Figure 14 (a), block A of type A
・The wiring connecting the cells ASB and C in B and C is arranged so that it passes under each block, which is clearly a long route for the wiring. However, in the rough wiring between blocks that is performed before placement within a block, it is not known where in blocks A@B and C the cells with connection requests will be placed, so it is difficult to allocate terminals to optimal positions and determine wiring routes. Have difficulty.

In the example of FIG. 14(b), block A of type A.
The wiring path connecting cell d@e in block C runs from the upper left side of block B to the upper right side.
It can be seen that the passage area on the cell row of block A is smaller than the passage area on the cell row of block B after the rough wiring in the block or before the placement in the di-block. With rough wiring between terminals, it is difficult to allocate terminals to optimal positions and determine wiring routes.

In the example of FIG. 14(C), block A of type A.
Terminals are set on the top side of each block as a wiring path connecting cells f and g in block C, and these are connected, but accurate estimates for blocks A and C can only be made by using the rough wiring within the block. After that, it is difficult to determine the optimal wiring route using the general wiring before the layout within the block is completed.

(Problem to be Solved by the Invention) In the conventional technology, rough wiring between blocks is performed only once, either before or after placement and wiring within a block. If it is performed after placement and wiring within blocks, the wiring area between blocks will increase. If you do this before placing and wiring within a block, you may not know the location of the cells within the block, the degree of wiring congestion within the block, the size of the block has not been determined, etc. When viewed without distinguishing between layers, redundant wiring and wiring areas occur. Therefore, both when looking only between blocks, and when looking without distinction of hierarchy within and between blocks,
It is an object of the present invention to determine approximate wiring paths between blocks and terminal positions of each block without creating redundant wiring-wiring areas.

[Structure of the invention]

(Means for solving the problem) Perform rough wiring between blocks once before placing and wiring within the block, reflect the results of optimization between blocks in the placement and wiring within the block, and after placing the blocks within the block In this article, we perform rough wiring between blocks by considering the cell position, and after rough wiring within a block, we perform rough wiring between blocks by taking into consideration the degree of wiring congestion and block size within the block. Also, when looking at the hierarchy within and between blocks, the approximate wiring paths between blocks and the terminal positions of each block are determined without generating redundant wiring and wiring areas.

(Function) Prevent the use of redundant wiring or unnecessary wiring area by performing rough wiring between blocks once before placement and wiring within a block and once after placement within a block and after rough wiring. .

(Example) In Fig. 1, once before placement in the plant, once after placement,
A flowchart is shown when performing inter-block general wiring processing once after intra-block general wiring.

Shape information of logic elements (cells) included in circuit blocks other than tie IA and type A, connection information between the circuit blocks and logic elements, and assignment of logic elements to type large blocks (if there are multiple type large blocks) 5 tart when the relative position of each circuit block is input.

5step 1: Create a path graph that covers the steps.

By searching for the shortest route on the route graph, an approximate route between blocks is determined. For example, the path graph shown in FIG. 4 is used.

Furthermore, the terminal positions of type A blocks are determined so as to minimize the wiring area between blocks. (References Information Processing Society of Japan Fist Design Automation Study Group 36-8゜February 1987,
1986 Application No. 238836) 8 step 2:
Automatic placement within the block is performed based on the terminal position information obtained in the above process.

5tep 3: Search for the shortest route between blocks again based on the cell power distribution information. At this time, a path graph is used that can reflect the cell positions to a certain degree, as shown in FIG. For example, the route graph is created and the shortest route search is performed in accordance with the procedure shown in FIG.

More details later. To avoid unnecessary trunk lines by considering the cell position when determining the terminal position. A terminal is set in a terminal setting range M determined from the cell position. (See Figure 7) Step 4: Perform general wiring within the block. Along with this, the degree of overlapping of the main lines of each channel within the block (d
It is called "sensity". ). It is also checked how much of the cell row on-pass wiring area is used.

Also, estimate the size (width and height) of each type of person's block. After rough wiring within a block, the width of the block can be accurately known, and the height of the block can also be accurately estimated from the density.

5step 5: From the result of 5step 4, delete the route information that connects to the cell of the blocker with the wiring within the block.

The density of the channel within each block along with the cell position
t)'.

The chip is divided into lattice-like regions as shown in FIG. 6, taking into consideration the area of passing wiring on the cell row, and a route search is performed.

See Figure 7 for the method of dividing into a grid. More details later.

The weight of the route graph is not based on physical distance, but on how much space there is in the wiring area.

The figure is an example of a method for calculating weights. Place restrictions on physical execution as necessary. Also, determine the terminal position of the type A block.

5tep 6: In accordance with the process of 5tep 4, the wiring route within the block is partially changed.

Step 7 * Perform detailed wiring within and between blocks.

In the above example, inter-block general wiring is performed once before intra-block placement, once after intra-block placement, and once after intra-block general wiring.

It is also possible to perform this once after the intra-block placement and general wiring within the block.

Furthermore, it is also possible to perform the general wiring between blocks according to the present invention without using a route graph.

The following is how to create a route graph for rough wiring after placement in a block. Create a path graph for each net and perform the path search. (See Figure 3) First, create a graph of the type A play that is connected to the net. Select the cell closest to the top, bottom, left, and right sides of the cells that are connected to the net, and place a node on top of that cell. Draw perpendicular lines from each node to the top, bottom, left, and right sides and use these as branches.

Let the legs of the perpendicular line be the nodes.

Create a path graph for regions within the chip other than type A.

The method of creating a route graph for performing the general wiring within the block after the general wiring within the block is as follows.

(See Figure 2) Each region within the chip is divided into grids, and the difficulty of passing the wiring is calculated for each grid region. To divide a large type block into areas on a grid, it is divided vertically into wiring areas and cell row areas, and horizontally into appropriate areas. X
The difficulty of passing when trying to pass in the direction is 0 in the wiring area.

In the cell row area... Calculate the size of the section as the number of wires passing through the section of wiring area 17. The difficulty of passing in the X direction is the maximum density in the wiring area.
Let y be dM and the density within the grid be d.

put out

Channels between blocks are divided by straight lines in the branch line direction to create a lattice. The difficulty of passage is as follows: In the branch line direction...In the O1 main line direction, the maximum density in that channel is dM,
If the density in the grid is ftd, it is calculated as □.

dM-d For blocks other than type A, divide them into appropriate grids, and set the width of 9＠ in both x and 1 directions to infinity if it is a wiring prohibited area, and 0° if it is not. .

This makes it possible to evaluate how much the area increases in the direction perpendicular to the passing direction when passing through a certain area in a certain direction, and it can be seen that routes with low evaluation values do not increase the area of any chip. By equalizing the degree of wiring congestion, we aim to increase the degree of integration of the υ chip.

A route search is performed based on the weight of each grid, and if there are multiple routes with the same weight, the route with the shortest physical distance is selected.

〔Effect of the invention〕

By performing inter-block rough wiring once before placement and wiring within a block, once after placement within a block or after rough routing, or once after both, even when looking only between blocks, To determine an approximate route without generating redundant wiring/wiring areas even when viewed without distinguishing between layers. It becomes possible to increase the degree of integration of chips.

[Brief explanation of the drawing]

1 and 2 are flowcharts explaining the present invention in detail, FIG. 3 is a flowchart showing an example of a method for creating a path graph used for schematic wiring between blocks after placement, and FIGS. 4 and 5. and Figure 6 are examples of route graphs used during rough wiring before placing within a block, during rough wiring after placing within a block, and during rough wiring after rough wiring between four blocks, respectively. A diagram illustrating an example of a method for determining the positions of block terminals during general wiring to be performed later; FIG. 8 is a schematic configuration diagram of a chip using a general building block; and FIG. 9 is a block diagram. Fig. 10 is a diagram of a prohibited area for cell passage wiring, Fig. 11 is a diagram of a wiring route, and Fig. 12 is a diagram of a conventional layout flow.
FIG. 13 is a diagram illustrating an example of a wiring route, and FIG. 14 is a diagram illustrating problems in the conventional technology. 1...Cell. 2... Area where wiring is prohibited on the cell. 6...Block. 7...Intra-block wiring area. 9... Cell row. 10...Inter-block wiring area. 11... Peripheral circuit block. Agent Patent Attorney Yudo Nori Chika Matsuyama Light Speed Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Illustrator B7 Rough ■- Figure 6 Figure 8 - Ippon Nishikikata 9, 10, 11, and 12. Guto Q

Claims (3)

[Claims] (1) A building block type integrated circuit in which multiple blocks are arranged on a semiconductor substrate, each of which achieves a desired logic function by arranging multiple cell rows each consisting of multiple logic cells and wiring between each logic cell. In the general wiring method between blocks when designing a block, before performing the detailed placement and wiring of logic cells within a block, after setting the general wiring route between blocks and terminals on the sides of the block, Schematic wiring of a semiconductor integrated circuit, characterized in that detailed placement of cells within a block is determined based on the wiring results, and then rough wiring between blocks is performed once again, taking into account placement positions of cells within the block. Method. (2) The general wiring between blocks after intra-block placement is determined, and after the general wiring within the block is determined, the general wiring between blocks is performed once again taking into account the degree of wiring congestion within the block. 2. A method for schematically wiring a semiconductor integrated circuit according to claim 1. (3) During the general wiring between blocks after the general wiring within a block has been completed, the difficulty of passing the wiring due to the degree of congestion of the wiring is considered, not the physical distance, to equalize the degree of wiring congestion. 2. A method for schematically wiring a semiconductor integrated circuit according to claim 1.