JPH01240998A - Propagation delay time calculating system - Google Patents

Abstract

PURPOSE:To make time necessary for delay calculation minimum by extracting a duplicate path out of a forward path from a starting point to an output and backward path from an end point to an input, executing troublesome delay calculation only for the extracted path, and obtaining the delay time between the starting point and the end point. CONSTITUTION:Based on inputted circuit information 4, starting point information and end point information, a path extracting part 1 between the starting point and the output extracts the forward path from the starting point to the output, and a path extracting part 2 between the end point and the input extracts the backward path from the end point to the input. A delay calculating part 3 executes the delay calculation of the duplicate path out of the both paths, and the delay time between the starting point and the end point is calculated. Thus, by executing the troublesome delay calculation only for the duplicate path out of the forward path from the starting point to the output and the backward path from the end point to the input, the processing time necessary to obtain the delay time between the starting point and the end point can be shortened to a minimum.

Description

[Detailed Description of the Invention] [Summary] Regarding a propagation delay time calculation method that calculates the propagation delay time between arbitrary nodes, the path from the start point to the output and the end point to the input is traced, and the delay is calculated only for the path where the two overlap. Start point/output that calculates the delay time between the start point and end point and extracts the path between the start point and output based on circuit information, start point information, and end point information, with the aim of reducing processing time. Regarding the overlapping paths extracted by the inter-path extraction unit, the end-point/input path extraction unit that extracts the path between the end point and the input, and the start-output/output path extraction unit and the end-point/human-powered path extraction unit, and a delay calculation section that calculates the delay time between the start point and the end point, and is configured to output the determined delay time between the start point and the end point.

[Industrial application field]

The present invention relates to a propagation delay time calculation method for calculating the propagation delay time (delay time) between arbitrary nodes that is necessary when performing a delay time analysis of a circuit.

[Problems to be solved by conventional technology and invention] Conventionally,
When calculating the delay time between arbitrary nodes in a circuit, the delay time is calculated sequentially while tracing the path from the start point pin of the LSI whose delay time is to be calculated until the end point pin is found, and then the delay time is calculated sequentially until the end point pin is found. Was. Calculation of this delay time includes square root calculation in addition to addition and multiplication, and takes 10 to 100 times longer than tracing processing to find a path from a starting point pin to an ending point pin. Therefore, as schematically shown using the diagonal lines in Figure 6, the delay time is calculated for all paths from the starting point pin (starting point A) to the output, and the delay time is calculated even for unnecessary paths. There is a problem in that calculations are performed, which increases processing time. In particular, as the circuit becomes more complex, the processing time increases, which becomes a serious problem.

The present invention aims to shorten processing time by tracing paths from a start point to an output and from an end point to an input, and calculating delay only for paths where both overlap to find the delay time between the start and end points. .

[Means for solving problems]

Means for solving the problem will be explained with reference to FIG.

In FIG. 1, a starting point/output path extraction unit 1 extracts a forward path from the starting point to the output.

The end point/input path extraction unit 2 extracts a backward path from the end point to the input.

The delay calculation unit 3 performs delay calculations on overlapping paths among the paths extracted by the start point/output path extraction unit 1 and the end point/input path extraction unit 2, and
This calculates the delay time of the path between end points.

Circuit information 4 is input in an attempt to calculate the delay time.

[Effect]

As shown in FIG. 1, the present invention provides input circuit information 4
, the start point information, and the end point information, the start point/output path extraction unit 1 extracts a forward path from the start point to the output, and the end point/human power path extraction unit 2 extracts the backward path from the end point to the input. , the delay calculation unit 3 calculates the delay for the overlapping paths among both paths, and calculates the delay time between the starting point and the ending point.

Therefore, the starting point and
It becomes possible to reduce the processing time required to find the delay time between end points to the necessary minimum.

〔Example〕

First, the delay calculation range according to the present invention will be explained with reference to FIG.

In FIG. 5, first, a forward path from the starting point A of a given circuit to the output where the ending point B exists, and a backward path from the ending point B to the input where the starting point A exists are determined. Second, if only the overlapping paths of these two paths are extracted, the range is shown using diagonal lines in the figure. Therefore,
Only the minimum necessary range indicated using this diagonal line,
By performing delay calculation and finding the delay time between the starting point A and the ending point B, it is possible to minimize the amount of delay calculation and shorten the processing time.

Next, in accordance with the order shown in the flowchart of FIG.
Using the circuit information example in Figure 4 and the link table example in Figure 4,
The operation of the configuration shown in FIG. 1 will be explained in detail.

In FIG. 2, ■ in the figure initializes the link table. This can be done, for example, by preparing the link table in Figure 4 (see Figure 4) and inputting the paths a to n in the circuit information example in Figure 3.
This means that the path column of this link table is entered as shown in the figure, and the mark is initialized to O (zero).

3 in the figure performs forward tracing from the starting point toward the output, and adds "+1" to the mark of the corresponding path.

As shown in Figure 4 (B), this is done by performing a forward trace from the starting point A in the circuit information example in Figure 3 to the output where the ending point B exists, and corresponding to the paths a, b, C, etc. found. This means adding "+1" to the mark column.

In the figure, it is determined whether or not the trace has been traced to the output of the circuit. If YES, perform ■ in the figure.

In the case of NO, since the output has not yet been traced, step 2 in the figure is repeated.

■ in the figure traces backwards from the end point toward the input, and adds "+2" to the mark of the corresponding path. This is shown in Figure 4 (
As shown in c), perform backward tracing from end point B in the example circuit information in Figure 3 to the input where end point A exists,
Found path m, k.

This means adding "+2" to the mark column corresponding to h, etc.

3 in the figure traces to the input of the circuit and determines whether it is 1 or not. If YES, perform ■ in the figure.

In the case of NO, since the input has not been traced yet, step 2 in the figure is repeated.

3 in the figure calculates the delay time of the path with the mark "3" to find the delay time between the start point and the end point. This means that the mark in the link table in Figure 4 (c) is "3".
is stored (corresponding to the path indicated by the thick line in Figure 3), calculate the delay time of this path, and calculate the delay time between the start point A and the end point B. It means.

Through the above processing, only the paths connecting the starting point A and the ending point B are extracted, and by calculating the delay time only for these extracted paths and finding the delay time between the starting point and the ending point 13, It becomes possible to reduce the processing time required for delay calculation to the necessary minimum.

FIG. 3 shows an example of circuit information. The thick line indicates the path marked with "3".6 FIG. 4 shows an example of the link table. FIG. 4(a) shows the initial state, in which zero is stored in the mark column.

Figure 4 (b) shows the result after tracing forward from the starting point A, and a value increased by "+1" is stored in the mark field of the 8-pass. Figure 4 (c) shows the trace tracing backward from the end point B. This is the latter one, and the value increased by “+2” is stored in the mark field of the corresponding path.
The path for which "3" is stored is the path that connects the start point A and the end point B. Therefore, only the path for which "3" is stored in this mark column is required to calculate the delay between the start point A and the end point B. Find the delay time between.

FIG. 5 shows the delay calculation range according to the present invention.

The shaded area is the delay calculation range.

〔Effect of the invention〕

As described above, according to the present invention, overlapping paths (a forward path from the start point to the output and a backward path from the end point to the input) are extracted, and the time-consuming delay calculation is performed only on the extracted paths. Since this configuration employs a configuration in which the delay time between the start point and the end point is calculated by performing the above steps, the time required to calculate the delay between arbitrary nodes can be minimized. In particular, as the circuit becomes more complex, the time required for delay calculation can be reduced compared to the conventional method.

[Brief explanation of the drawing]

Fig. 1 is a configuration diagram of one embodiment of the present invention, Fig. 2 is a flowchart explaining the operation of the present invention, Fig. 3 is an example of circuit information, Fig. 4 is an example of a link table, and Fig. 5 is a delay calculation range according to the present invention. , FIG. 6 shows the delay calculation range according to the prior art. In the figure, 1 is the start point/output path extraction section, 2 is the end point/input path extraction section, 3 is the delay calculation section, and 4 is the -:7-type 3.
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Claims (1)

[Claims] In a propagation delay time calculation method that calculates a propagation delay time between arbitrary nodes, there is a starting point/output method that extracts a path between a starting point and an output based on circuit information, starting point information, and ending point information. Interval path extraction part (
1) and an end point/input path extraction unit (2) that extracts the path between the end point and the input, and a start point/output path extraction unit (1) and an end point/input path extraction unit (2). and a delay calculation section (3) that calculates the delay time between the start point and the end point by calculating the delay for the overlapping paths that have been detected, and is configured to output the calculated delay time between the start point and the end point. Characteristic propagation delay time calculation method.