JPH01238486A - Speed control circuit for motor - Google Patents

Abstract

PURPOSE:To form a digital processor in a circuit adapted to be integrated, and to accelerate a processing time by so setting counting means that the counted value when a motor is rotated at an instructed speed takes a specific value. CONSTITUTION:Counter means 14 for counting a signal from encoder signal generating means 2 is so set that the counted value when a motor 1 is rotated at an instructed speed takes a specific value. Speed error signal output means 20 outputs a bit initially varied in its code as counted from the less significant bit of all bits of the counter means 14 and a bit of less significant bit than this bit as speed error signals. The code of the bit varied initially in its code and the bit of more significant bit of the bit are inverted by code inverting means 16, and the output of the means 16 and a phase error signal are added. Then, the speed error signal and the phase error signal are added and output to a driving circuit 3.

Description

[Detailed description of the invention] Table of contents Overview ・ ・ ・ ・ ・ ・ ・ ・
・ ・ ・ 3 pages Industrial application fields ・・・・・・・
・Page 5: Prior art ・・・・・・・・・Page 5: Problem to be solved by the invention ・Page 8: Means for solving the problem ・Page 8: Effects・
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Example ・ ・ ・ ・ ・ ・ ・ ・ ・
・ ・ Page 12 Effects of the invention ・・・・・・・・・・・・2
0 page I! Regarding the speed control circuit of the required motor, we aim to provide a speed control circuit for the motor that aims to speed up the processing time by converting the f-digital processing circuit, which was conventionally realized with a microprocessor, into a circuit suitable for IC. The speed of the motor is controlled by using an encoder signal proportional to the rotational speed of the motor, digitally processing the cycle of the encoder signal to obtain a speed error signal and a phase error signal, and feedback controlling the rotational speed of the motor based on these signals. In the control circuit, when the motor rotates at the commanded speed,
counter means for counting the period of the encoder signal, the count value of which is set to a value such that the sign changes once or twice in binary representation; A speed error signal output means for outputting a changing bit and bits lower than the bit as a speed error signal, and an addition for cumulatively adding arbitrary bit lengths of a counter means including at least a bit whose sign changes first. means, sign inverting means for inverting the sign of the bit whose sign first changes among the bits input to the adding means and bits higher than the bit, and outputting the calculation result of the adding means as a phase error signal. and phase error signal output means.

! ! ! 190s 1kuri The present invention relates to a motor speed control circuit.

Brushless motors, which use non-contact electronic commutation instead of a commutator, are highly reliable in terms of lifespan and electrical noise, and are increasingly being applied to a variety of devices. Since this brushless motor has a high degree of structural freedom, it is easy to make it lighter, thinner, shorter, and smaller, and its uses are expanding as a direct drive motor that can easily maintain relative mechanical precision between equipment and the motor. Such motors are widely used in applications that require highly accurate constant speed rotation, such as cassette tape recorders, video tape recorders, and scanner motors for laser beam printers. Therefore, there is a need for a motor speed control circuit that allows the motor to rotate at a constant speed with high precision.

Conventional technology In a circuit that controls the speed of a brushless motor, an encoder signal proportional to the rotational speed of the motor is used, the cycle of this encoder signal is digitally processed to obtain a speed error signal and a phase error signal, and these signals are digitally processed. A method is known in which the data is fed back to the motor drive circuit after analog conversion (D/A conversion).

FIG. 4 is a block diagram of a conventional example of the above-mentioned system, in which 1 is a motor, 2 is an encoder signal generator, 3 is a motor drive circuit, 4 is a clock generator, 5 is a synchronous circuit,
6 is a counter, 7 is a delay circuit, 8 is an overflow detection circuit, 9 is a microprocessor (MPU), 10.11 is a D/A converter, and 12 is an addition circuit.

The operation of the circuit shown in FIG. 4 will be explained. Suppose that the command rotation speed of the motor is f, and the actual rotation speed of the motor is fH.
, the frequency z of the clock generator 4 is f. Hl, the encoder signal generator 2 shall output a signal once per motor rotation. MPLI9 is given f/f as the ll count value by software.

The counter 6 counts the period of the signal output from the encoder signal generator 2 at the frequency of the clock generator 4.

The signal from the encoder signal generator 2 is sent to a counter 6 which is synchronized with the frequency of the clock generator 4 in a synchronization circuit 5.
, a timing signal for inputting the count value of the counter 6 to the MPLJ 9, and a reset signal for the overflow detection circuit 8. As a result, the MPU 9 has a count value f /fH corresponding to the rotation period of the motor.
is input. There are two types of output from MPtJ9, one being fCSC which is f/f minus f/fH, which corresponds to the speed error signal. The other one is an output obtained by cumulatively adding the speed error signal Δf, which corresponds to a phase error signal. The speed error signal Δf is digital/analog converted by a D/A converter 10 and then input to an adder circuit 12 . On the other hand, the phase error signal is digital/analog converted by a D/A converter 11 and then input to an adder circuit 12 . The adder circuit 12 adds both signals with a gain determined by the servo band, etc., and inputs this to the motor drive circuit 3 to control the motor at a constant speed.

However, in the conventional motor speed control circuit as described above, digital signals are processed using MPLJ9, which results in high prices and slow processing speeds since it is not a dedicated circuit. was there.

The present invention has been made in view of these points, and its purpose is to speed up the processing time by converting a digital processing circuit, which was conventionally realized using a microprocessor, into a circuit suitable for integration into an IC. An object of the present invention is to provide a speed control circuit for a motor.

Means to solve problems FIG. 1 shows a block diagram of the principle of the present invention.

In FIG. 1, a motor 1, an encoder signal generator 2,
Drive circuit 3, D/A converter 10.11 and addition circuit 12
is substantially the same as the conventional circuit shown in FIG.

When the motor rotates at a commanded speed, a counter means 14 is provided for counting the period of an encoder signal proportional to the rotational speed of the motor, the count value being set to a value such that the sign changes once or twice in binary representation. . That is,
Among all the bits of the counter means 14, the values of the bits higher than the bit whose sign changes first, counting from the lower order, are all "0" or "1". Further, the counter means 14
A speed error signal output means 20 is provided for outputting, as a speed error signal, the bit whose sign changes first and the bits lower than this bit among all the bits counted from the lower order bit.

Further, an addition means 18 for cumulatively adding arbitrary bit lengths of the counter means 14 including at least a bit whose sign changes first, and a bit whose sign changes first among the bits input to the addition means 18 and the bit. It is constructed by providing a sign inverting means 16 for inverting the sign of the higher-order bits, and a phase error signal outputting means 22 for outputting the calculation result of the adding means 18 as a phase error signal.

More desirably, there is provided a determining means for determining whether or not the count result of the period of the encoder signal is larger than a value that can be expressed by the bit length of the counter means 14; A selection means may be provided for selecting the output values of the output means 20 and the phase error signal output means 22 so that the count results are the maximum values within a range where the determination means does not determine that the output values are large.

Function As described above, the counter means 14 is set so that the count value when the motor rotates at the commanded speed takes a special value. For example, the bit length of the counter means 14 is 6, the output to the D/A converter 10°11 is 4 bits,
When using the counter means 14 as a down counter,
For example, the count value when the motor rotates at the command speed is set to [001000J. When the counter means 14 is used as an up counter, the count value is set to, for example, rllloooJ. Further, when the bit length of the counter means 14 and the input bit length to the D/A converter 10.11 are equal at 4 bits, the count value is set to, for example, N0OOJ.

By setting the count value of the counter means 14 in this way, a speed error signal and a phase error signal obtained by cumulatively adding the speed error signal can be obtained from the count value of the period of the encoder signal corresponding to the rotational speed of the motor. It is possible to simplify the configuration of the adding means 18 for calculating and the determining means for determining the range in which the addition is correctly performed. Furthermore, it becomes easy to convert the input from the two error signals to the D/A converter 10.11 into straight binary or its complement expression suitable for an inexpensive R-2R ladder resistance network.

The speed error signal and phase error signal converted from digital to analog by the D/A converter 10.11 are input to the adder circuit 12 as in the conventional circuit, and the adder circuit 12 converts these signals into a gain determined by the servo band, etc. By adding this result to the motor drive circuit 3, the motor 1
is controlled at a constant speed.

Example Embodiments of the present invention will be described below based on the drawings.

FIG. 2 shows a block diagram of the first embodiment of the present invention, and components that are substantially the same as those of the conventional circuit shown in FIG. 4 are given the same reference numerals.

In FIG. 2, 3o is an up counter with a bit length of 4 bits, 31, 33, and 37 are latches, 34 is a sign inverter that inverts the sign of the most significant bit, 35 is a digital adder, and 32, 36 are digital multiplexers. , 38 and 39 are delay circuits, and 40 is an overflow detection circuit. The overflow detection circuit 40 constitutes the determining means 24, and the digital multiplexers 32 and 36 constitute the selecting means 26.

The operation of this embodiment will be explained below.

Assume that the command rotation speed of the motor is r, H7 is the actual rotation speed of the motor, f is the frequency of the H1 clock generator z4, and f is the frequency of the H1 encoder signal generator 2l, which outputs a signal once per motor rotation. do.

When the motor is rotating at the command speed f, counter 3
A count value of 0 is expressed in binary as [1o.

0'', the frequency f of the clock generator 4.

Establish. That is, fo/f is 1000 in binary representation.
The frequency fc of the clock generator 4 is determined so that it becomes J. The signal from the encoder signal generator 2 is sent to the synchronization circuit 5 at the frequency f of the clock generator 4. After being synchronized by , it is used as a clear signal for the counter 3o, a timing signal for the latch 3L 33.37 to latch the input signal, and a reset signal for the overflow detection circuit 40.

When the rotational speed of the motor is fH, the frequency f of the clock generator 4 is fH. The count value of the counter 30 which performs the counting operation is f/fH. When fH>f8, the counter 30 is an up counter, so its count value is expressed in binary as [less than 1000J, for example ro
lllJ etc. On the other hand, if fH<fs, the count value is greater than "1000", for example "1oo1".
etc., or the counter 30 overflows. The overflow of the counter 30 is detected by the overflow detection circuit 40, and when an overflow occurs,
The digital multiplexer 32 selects the data to be rl 111J regardless of the counter value of the counter 30. The output of the digital multiplexer 32 is latched by the latch 33 with a predetermined delay of the delay circuit 39, and the value indicated by the latch 33 is the rotational speed fH of the motor.
Since this signal changes around "1000" depending on the magnitude of the command speed fs, this signal can be regarded as a speed error signal with an offset.

Next, the phase side will be explained. A value obtained by inverting only the most significant bit of the output of the latch 31 by the sign inverter 34 is input to the digital adder 35, and the value of the latch 37 is also fed back and input. With this configuration, the digital adder 35 cumulatively adds speed error signals without offset. This is nothing but the phase error signal described in the conventional example shown in FIG.

Digital multiplexer 36 outputs counter 3 at f,<f.
When the count value of 0 overflows, the phase error signal is rllllIJ regardless of the output of the digital adder 35.
It is provided to improve the start-up characteristics of the motor and to prevent the motor from being erroneously synchronized at, for example, 1/2 of the commanded speed.

Speed error signal output from latch 33 and latch 37
The phase error signals outputted from the circuits are each subjected to digital/analog conversion by D/A converters 10 and 11 and input to the adder circuit 12 . The adder circuit 12 adds both signals with a gain determined by the servo band, etc., and inputs this to the motor drive circuit 3 to control the motor 1 at a constant speed.

FIG. 3 is a block diagram of a second embodiment of the present invention. Third
In the figure, 42 is a 6-bit up counter, 43 is a digital comparator, and 44 is an OR circuit. Other circuits are second
Since it is substantially the same as the first embodiment shown in the figure, its explanation will be omitted. In this embodiment, the overflow detection circuit 40
and a digital comparator 43 constitute the determining means 24.

The operation of this embodiment will be explained below.

The clock frequency fo generated by the clock generator 4 is
When the command speed of the motor is f, fo/fS is determined to be a binary expression F'111000J or a smaller value.If f/f8 is smaller than rl11000J, the same amount is set in the Samir switch 45. An appropriate value for correction is set so that when the counter 42 counts the period of the encoder signal, the value set in the Samir switch 45 is input into the counter 42 in advance.This allows the motor to operate at the command speed. When the period of the signal output from the encoder signal generator 2 during rotation is counted by the frequency of the clock generator 4, the value is:
Make it so that it becomes rllloooJ.

The encoder signal from the encoder signal generator 2 is
Similar to the first embodiment shown in the figure, after being synchronized with the frequency of the clock generator 4 by the synchronization circuit 5, the load signal which sets the value set in the Samir switch 45 in the counter 42, the latch 31.33° 37 is used as a timing signal for latching an input signal and as a reset signal for the overflow detection circuit 4o.

The digital multiplexer 32 has the lower 4 of the counter 42.
Enter bits. On the other hand, a value obtained by inverting only the most significant bit of the lower four bits of the counter 42 by the sign inverter 34 is input to the digital adder 35. Furthermore, the output signal of the latch 37 is fed back and input to the digital adder 35 . The overflow detection circuit 4o detects whether or not an overflow occurs when the counter 42 counts the period of the encoder signal. This detection result is sent to the digital multiplexers 32 and 36, and is also input to the OR circuit 44.

The digital comparator 43 is a circuit that determines whether or not the upper two bits of the counter output match "11", and inputs the result of this determination to the OR circuit 44. Since the count value when the motor rotates at the commanded speed is determined as described above, the digital comparator 43 can omit the function of comparing the magnitudes. Is the calculation for determining the error signal performed correctly by the combination of the output of the overflow detection circuit 40, the output of the digital comparator 43 that detects whether the upper two bits of the counter match "11", and the OR circuit 44? Now you can know what's going on.

The output of the OR circuit 44 is the digital multiplexer 32.3
It functions as a data select signal of 6.

That is, if the overflow detection circuit 40 detects an overflow, or if the digital comparator 43 determines that the upper two bits of the count value of the counter 42 do not match "11J," the OR circuit 44 First, the overflow detection circuit 4o is connected to the digital multiplexer 32.
．． Data sent to 36 (rl 111J if overflow is detected, foo if overflow is not detected)
oOJ ) is output. On the other hand, no overflow is detected and the digital comparator 43 is "1".
1], it means that the motor is rotating near the command speed, and in this case, OR
From the circuit 44, digital multiplexers 32 and 36 output signals for selecting the output of the latch 31 and the output of the digital adder 35.

Similarly to the first embodiment described above, the value of the latch 33 varies depending on the magnitude of the motor rotational speed f14 and the command speed f.
Since it changes around 00J, this signal can be regarded as a speed error signal with an offset. Also, latch 3
The value indicated by 7 is the cumulative addition of velocity error signals without offset, and indicates a phase error signal.

By adopting the configuration shown in FIG. 3, the quantization error can be made smaller than in the embodiment shown in FIG.
The speed control performance can be improved without increasing the bit length of the /A converter 10.11.

As detailed above, the present invention has made it possible to replace the digital processing circuit conventionally realized with a microprocessor with a circuit suitable for IC, reducing the cost of the motor speed control circuit. This has the effect of speeding up the processing time.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram of the first embodiment of the invention, and Fig. 3 is a block diagram of the second embodiment of the invention.
Embodiment Block Diagram FIG. 4 is a block diagram of a conventional example. DESCRIPTION OF SYMBOLS 1...Motor, 2...Encoder signal generator, 3...Drive circuit, 4...Clock generator,
14... Counter means, 16... Sign inversion means,
18...Addition means, 20...Speed error signal output means, 22...Phase error signal output means, 30.42...Counter, 31.33.37...Latch, 32.36...・Digital multiplexer, 34...
Sign inverter, 35... Digital adder, 40... Overflow detection circuit, 43... Digital comparator.

Claims (2)

[Claims] (1) Using an encoder signal proportional to the motor rotation speed, digitally process the cycle of the encoder signal to obtain a speed error signal and a phase error signal, and feedback control the motor rotation speed based on these signals. In a speed control circuit for a motor, when the motor rotates at a commanded speed, the encoder signal is set such that a predetermined bit is "1" and lower bits are "0" in binary representation of the count value. counter means (14) for counting the period of the counter means (14); and speed error signal output means (20) for outputting the predetermined bit and bits lower than the predetermined bit among all bits of the counter means (14) as a speed error signal. sign inverting means (16) for inverting the sign of at least one bit among the predetermined bit and bits higher than the bit among the bits from the counter means (14); and cumulatively inverting the sign of the inverted bit. Addition means (18
), and phase error signal output means (22) for outputting the calculation result of the addition means (18) as a phase error signal. (2) Determination means (24) for determining whether the count result of the period of the encoder signal is outside the range of values that can be expressed by the predetermined bits and bits lower than the predetermined bits.
And, if the determination means (24) determines that it is out of order,
The output values of the speed error signal output means (20) and the phase error signal output means (22) are determined to be the maximum or minimum value within the range depending on whether the output values are larger or smaller. The motor speed control circuit according to claim 1, further comprising selection means (26) for selecting.