JP2781864B2 - Digital drive for motor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a digital motor driving apparatus for controlling the speed of a DC motor by digital signal processing. [Summary of the Invention] The present invention relates to a digital drive device for a motor in which the speed of a DC motor is controlled by digital signal processing, a rotation speed detection means for detecting the rotation speed of the motor, and a reference value according to the rotation speed setting. A reference value generation means for generating, a comparison means for comparing the rotation speed information from the rotation speed detection means with the reference value generated by the reference value generation means, and obtaining a difference; Signal processing means for performing digital arithmetic processing to convert the digital signal into an m-bit (m ≧ 3 positive integer) digital signal and outputting the converted signal, and an n-bit (m> n, n is a positive integer) digital signal A digital-to-analog conversion means for converting into an analog signal, and k bits (m> k, where k is a positive integer and (n + k)>
m) to convert the digital signal into an analog signal, and an analog output of the first digital-to-analog converting means to the second digital-to-analog signal.
Attenuating means for attenuating the analog output of the analog converting means so as to adjust the weight; and an adding means for adding the attenuated analog signal from the attenuating means and the analog signal from the second digital-analog converting means. A driving means for driving the motor based on the addition result from the adding means, a latch means for latching upper n bits of the m-bit digital output, and a substantially intermediate value of the k-bit digital signal. a fixed data generating means for generating k-bit fixed data; a high-order n-bit signal among m-bit digital signals output from the digital signal processing means; and an n-bit signal output from the latch means. First switching means for switching to
Second switching means for selectively switching between the lower k-bit signal of the m-bit digital signal output from the digital signal processing means and the k-bit signal output from the fixed data generating means; In a stable state, the first switching means selects the n-bit signal output from the latch means, and the second switching means selects the m-bit digital signal output from the digital signal processing means. And when the rotational speed is unstable, the first switching means selects the upper n-bit signal from the m-bit digital signals output from the digital signal processing means, and K output from the fixed data generating means by the second switching means.
And control means for controlling the selection of the bit signal, so that a high-precision speed control can be performed using a low-precision and inexpensive digital-analog conversion circuit. [Prior Art] Conventionally, as a digital drive device for a DC motor in which the rotational speed is controlled by digital signal processing, a fourth motor is used.
The one shown in the figure has been proposed. That is, in FIG. 4, (1) is a DC motor which is required to rotate at a constant speed like a capstan motor of a tape recorder, for example. A frequency generator (2) for detecting a rotational speed is provided in association with the rotating shaft of the motor (1), and a frequency corresponding to the rotational speed of the motor (1) obtained at the output side of the frequency generator (2). signal
FG is supplied to a rotation cycle detection circuit (3), a DC voltage corresponding to the rotation cycle is obtained at the output side of the rotation cycle detection circuit (3), and this output signal is supplied to a comparison circuit (4). Reference numeral (5) denotes a speed setting circuit that can obtain a reference voltage value according to the rotation speed setting, and supplies the reference voltage value from the speed setting circuit (5) to the comparison circuit (4). At the output side of the comparison circuit (4), a signal of the difference between the output signal of the rotation period detection circuit (3) and the reference voltage value is obtained, and the difference signal is supplied to the digital signal processing circuit (6). In the digital signal processing circuit (6), the digital signal is converted into a digital signal corresponding to the added value of the difference signal and a digital operation is performed. In this example, six digital control signals of, for example, "011101" are converted into six signals in parallel. Output to the output terminals (6a), (6b),... (6f) so that the least significant bit becomes higher bit sequentially.
This digital signal processing circuit (6) has six output terminals (6
a) (6b)... A 6-bit digital control signal obtained in (6f), for example, “011101” is supplied to a 6-bit digital-analog conversion circuit (7), and the output side of the digital-analog conversion circuit (7) Is supplied to the motor (1) via the drive circuit (8) to control the rotation speed of the DC motor (1). In the example of FIG. 4, the rotational speed of the DC motor (1) is detected by a frequency generator (2), and this is compared with a reference value from a speed setting circuit (5). The digital signal processing circuit (6) obtains a 6-bit digital control signal, and converts the 6-bit digital control signal to a digital signal.
An analog control signal is obtained through an analog conversion circuit (7), and the DC motor (1) is controlled by the control signal. Therefore, the DC motor (1) is controlled at the speed set by the speed setting circuit (5). Can rotate at a constant speed. [Problems to be Solved by the Invention] The accuracy of speed control using the digital signal processing circuit (6) is determined by the number of bits of the digital control signal.
When the number of bits of the digital control signal is increased, for example, to 6 bits, the number of bits corresponding to the number of bits, for example, 6 bits
A bit digital-analog conversion circuit (7) is required. In other words, increasing the number of bits of the digital-analog conversion circuit (7) reduces the voltage variable width determined by load fluctuations and the like, and reduces the resolution (step width) determined by rotation accuracy and the like. The accuracy of the speed control will increase. However, increasing the number of bits of the digital-to-analog conversion circuit (7) has the disadvantage that the configuration is rapidly complicated every time one bit is added, and the cost is extremely high. In view of the above, an object of the present invention is to make it possible to perform relatively high-precision speed control using an inexpensive digital-to-analog conversion circuit with low precision and a small number of bits. [Means for Solving the Problems] The digital driving device for a motor according to the present invention is, for example, as shown in FIG. 1, a rotational speed detecting means (2) (3) for detecting the rotational speed of the motor (1) obtained by digital signal processing. )When,
Reference value generation means (5) for generating a reference value according to the rotation speed setting, rotation speed information from the rotation speed detection means (2) (3), and a reference generated by the reference value generation means (5). A comparing means (4) for comparing the values to obtain a difference, and performing digital operation processing on the difference obtained by the comparing means (4) to convert the difference into an m-bit (m ≧ 3 positive integer) digital signal Digital signal processing means (6) for converting and outputting an n-bit (m> n, n is a positive integer) digital signal to an analog signal; Bits (m> k, where k is a positive integer (n +
k)> m) a first digital-to-analog conversion means (7a) for converting a digital signal into an analog signal, and an analog output of the first digital-to-analog conversion means (7a) Attenuating means (11) for attenuating the analog output of the converting means (7b) in order to adjust the weight; an analog signal subjected to attenuating processing from the attenuating means (11); (12) adding means for adding the analog signal from
A driving means (8) for driving the motor (1) based on the addition result from the adding means (12), and a latch means (14) for latching upper n bits of the m-bit digital output. Fixed data generating means (10) for generating k-bit fixed data representing a substantially intermediate value of the k-bit digital signal, and m-bit digital signals output from the digital signal processing means (6). First switching means (13) for selectively switching between an upper n-bit signal and an n-bit signal output from the latch means (14); and an m-bit digital signal output from the digital signal processing means (6). Second switching means (9) for selectively switching between the lower k-bit signal of the signals and the k-bit signal output from the fixed data generating means (10); The switching means (13) selects the n-bit signal output from the latch means (14), and the second switching means (9) selects the m-bit signal output from the digital signal processing means (6). The lower k-bit signal is selected from among the digital signals, and when the rotation speed is unstable, the first switching means (13) selects the m-bit digital signal output from the digital signal processing means (6). Control means for selecting the upper n-bit signal and controlling the second switching means (9) to select the k-bit signal output from the fixed data generating means (10). Things. [Operation] In the present invention, the digital-to-analog conversion circuit is constituted by at least two first and second digital-to-analog conversion circuits (7a) and (7b).
The variable width of the analog conversion circuit (7b) is set to a predetermined number of times, for example, four times, the number of steps of the first digital-analog conversion circuit (7a), and the first digital-analog conversion circuit (7a) supplies the digital control signal to the first digital-analog conversion circuit (7a). A predetermined number of lower bits, for example, 4 bits, are supplied, and the second digital-analog conversion circuit (7b) partially overlaps, for example, 2 bits with the lower predetermined bits of the digital control signal. Since a predetermined number of higher order bits, for example, 4 bits, are supplied, when the rotation speed of the motor (1) is large, such as when the motor (1) is activated,
The upper bits of the digital control signal fluctuate. At this time, the rotation speed of the motor (1) is mainly controlled by the upper bits. In this case, the second digital-analog conversion circuit (7b) is mainly used. However, when the motor is stable, the rotation speed of the motor (1) is small, so that only the lower bits of the digital control signal fluctuate. In this case, the first digital-analog conversion circuit (7a) mainly operates. Even if a fixed digital signal is supplied to the second digital-analog conversion circuit (7b), regardless of the control of the rotation speed of the motor (1), the first digital-analog conversion circuit (7
The rotation speed of the motor (1) can be controlled with accuracy determined by the step a), and a digital-analog conversion circuit of relatively small number of bits, for example, 4 bits, is used, and the accuracy is relatively high. Rotation speed can be controlled. [Embodiment] An embodiment of a digital driving device for a motor according to the present invention will be described below with reference to FIG. In FIG. 1, portions corresponding to FIG. 4 are denoted by the same reference numerals, and detailed description thereof will be omitted. In this example, the four output terminals (6) from the lowest of the six output terminals (6a) (6b)... (6f) of the digital signal processing circuit (6) from which a 6-bit digital control signal is obtained, for example.
a) Connect (6b), (6c) and (6d) to the stable fixed contact (9S) of the changeover switch (9), and transfer the lower 4 bits of the digital control signal to the stable fixed contact (9S). To be supplied. Reference numeral (10) denotes a fixed data generation circuit. In this example, a fixed data of an intermediate value of a 4-bit digital signal, for example, "0,1,1,1" or "1,0,0,0" is output. This fixed data is supplied to the variable-side fixed contact (9D) of the changeover switch (9), and the movable contact (9a) of the changeover switch (9) is connected to a 4-bit digital-data having a relatively simple structure. It is supplied to the analog conversion circuit (7a). In this case, the movable contact (9a) of the changeover switch (9)
Is connected to the fixed-side fixed contact (9D) when the upper 4 bits of the digital control signal are changed, for example, when the upper 4 bits of the digital control signal are changed, and is connected to the fixed-side fixed contact (9S) when the upper 4 bits of the digital control signal are not changed. As described above, it is controlled by the control signal from the digital signal processing circuit (6). The digital-analog conversion circuit (7a) converts the analog output signal to one of the digital-analog conversion circuits (7a).
In other words, in order to reduce the bit step to one-fourth, ie, 1/4, of the variable width of the 4-bit digital-analog converter (7b) having a relatively simple configuration, the digital-analog converter (7b) In order to make the variable width of (4) four times the step of this digital-analog conversion circuit (7a),
The addition circuit (1
2) to supply. Also, the stable fixed contact (9) of the changeover switch (9) of the digital control signal obtained at the output terminals (6c), (6d), (6e) and (6f) of the digital signal processing circuit (6).
The lower 4-bit signal supplied to S) and the higher 4-bit signal which overlaps the 2-bit by 4 bits are supplied to the variable-side fixed contact (13D) of the changeover switch (13) and to the latch circuit (14). I do. The latched output signal of the latch circuit (14) is supplied to the stable fixed contact (13S), and the 4-bit digital signal obtained at the movable contact (13a) of the changeover switch (13) has a relatively simple structure. The signal is supplied to an adder circuit (12) via a 4-bit digital-analog converter circuit (7b). In this case, this switch (1
The movable contact (13a) of (3) is connected to the fixed contact (13D) on the fluctuation side when the upper 4 bits of the digital control signal fluctuate, for example, when the upper 4 bits of the digital control signal fluctuate, and is stable when the upper 4 bits of the digital control signal do not change. It is controlled by a control signal from the digital signal processing circuit (6) so as to be connected to the side fixed contact (13S). The latch circuit (14) is connected to this switch (1
The upper 4 bits of the digital control signal, for example, "0111" are latched at the timing when the movable contact (13a) of 3) is switched and connected to the stable fixed contact (13S). The output signal of the adding circuit (12) is supplied to the motor (1) via the driving circuit (8) so as to control the rotation speed of the motor (1). Otherwise, the configuration is the same as in FIG. The operation of the present example will be described with reference to the flowchart of FIG. 2. At the time of startup, the change in the rotation speed of the motor (1) is large, so that the movable contacts (9a) of the changeover switches (9) and (13) respectively. And (13a) are the floating fixed contacts (9D)
And (13D), in which case the fixed data generation circuit (10) supplies the intermediate value of the 4-bit digital signal, for example, the fixed data of "0111" to the digital-analog conversion circuit (7a), and this analog signal Is attenuated to 1/4 and supplied to the adder circuit (12). At this time, the upper 4 bits of the digital control signal obtained at the output side of the digital signal processing circuit (6) are switched to the changeover switch (13) Is supplied to a digital-analog conversion circuit (7b), and the output analog signal is supplied to an addition circuit (12). The output signal of the addition circuit (12), that is, an analog control signal, controls the motor (1). The rotation speed is controlled, the rotation speed of the motor (1) approaches the set value of the speed setting circuit (5), and the frequency signal FG obtained at the output side of the frequency generator (2), that is, the output of the period detection circuit (3) Beside Stable Sometimes, the change-over switch when the error between the detected signal and the reference value which is predetermined within ie the upper 4 bits is no longer changed (9) and (13)
The respective movable contacts (9a) and (13a) are switched and connected to the stable fixed contacts (9S) and (13S), and at this time, the upper four bits of the digital control signal are latched by the latch circuit (14). At the time of this stabilization, the fixed upper 4-bit digital signal latched by the latch circuit (14) is supplied to the digital-analog conversion circuit (7b).
A constant analog signal obtained at the output side of the analog conversion circuit (7b) is supplied to the addition circuit (12). At this time, the lower 4 bits of the digital control signal of the digital signal processing circuit (6) are converted into digital signals. The digital signal is supplied to the digital-analog conversion circuit (7a) via the changeover switch (9), and the analog signal obtained at the output side of the digital-analog conversion circuit (7a) is attenuated to 1/4 and added to the addition circuit (12). The rotation speed of the motor (1) is controlled by an analog control signal obtained at the output side of the addition circuit (12). In this case, when the rotation speed of the motor (1) greatly fluctuates, such as when the motor (1) is started, the upper bits of the digital control signal fluctuate. Since the rotation speed is controlled, in this case the digital-analog conversion circuit (7b)
Mainly operates, and when the rotation speed is stable, the rotation speed of the motor (1) is small. Therefore, only the lower bits of the digital control signal mainly change. In this case, the digital-analog conversion circuit (7a) mainly works. Even if a fixed digital signal is supplied to the digital-analog conversion circuit (7b), regardless of the control of the rotation speed of the motor (1), the motor (1) is determined with the accuracy determined by the steps of the digital-analog conversion circuit (7a). ) Can be controlled, and the relatively high-precision control of the rotational speed can be achieved by using, for example, a 4-bit digital-to-analog conversion circuit (7a) (7b) having a relatively simple configuration and a small number of bits. it can. In the above example, as shown in the flow chart of FIG. 3, the upper four bits of the digital control signal are supplied to the digital-analog conversion circuit (7b) of FIG. )), The digital signal of the lower two bits and the median value of the overlapped bits are supplied, and the same operation and effect as described above can be easily obtained even when the configuration is the same as above when the operation is stable. . In the above-described embodiment, an example in which two relatively simple digital-to-analog conversion circuits are used has been described. However, three or more relatively simple digital-to-analog conversion circuits are used. It can be easily understood that the same configuration can be adopted. In addition, the present invention is not limited to the above-described embodiment, and it goes without saying that various other configurations can be adopted without departing from the gist of the present invention. According to the present invention, there is an advantage that the rotation speed can be controlled with relatively high accuracy by using an inexpensive digital-analog conversion circuit having a relatively simple configuration and a small number of bits.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a digital drive device for a motor according to the present invention, FIGS. 2 and 3 are diagrams respectively illustrating the present invention, and FIG. FIG. 2 is a configuration diagram illustrating an example of a digital drive device for the motor of FIG. (1) is a motor, (2) is a frequency generator, (3) is a synchronization detection circuit, (4) is a comparison circuit, (5) is a speed setting circuit,
(6) is a digital signal processing circuit, (7a) and (7b) are digital-analog conversion circuits, (8) is a drive circuit,
(9) and (13) are changeover switches, (10) is a fixed data generation circuit, (11) is a 1/4 attenuation circuit, and (14) is a latch circuit.

Claims (1)

(57) [Claims] Rotation speed detection means for detecting the rotation speed of the motor, reference value generation means for generating a reference value according to the rotation speed setting, rotation speed information from the rotation speed detection means and the reference value generation means Comparing means for comparing the reference value to obtain a difference; digital processing for performing digital operation processing on the difference obtained by the comparing means to convert the signal into an m-bit (m ≧ 3 positive integer) digital signal; Signal processing means; second digital-analog conversion means for converting an n-bit (m> n, n is a positive integer) digital signal into an analog signal; k-bit (m> k, k is a positive (N + k)> m as an integer
A first digital-to-analog converting means for converting the digital signal into an analog signal, and for weighting an analog output of the first digital-to-analog converting means to an analog output of the second digital-to-analog converting means. An attenuating means for attenuating the analog signal from the attenuating means and an analog signal from the second digital-analog converting means, and an adding means for adding the analog signal from the adding means. Driving means for driving a motor; latch means for latching upper n bits of the m-bit digital output; fixed data generating means for generating k-bit fixed data representing a substantially intermediate value of the k-bit digital signal And the upper n-bit signal of the m-bit digital signal output from the digital signal processing means. A switch selectively the n-bit signal outputted from said latch means first
Switching means, and second switching means for selectively switching between a lower k-bit signal of the m-bit digital signal output from the digital signal processing means and a k-bit signal output from the fixed data generating means. When the rotational speed is stable, the first switching means selects the n-bit signal output from the latch means, and the second switching means selects the m-bit signal output from the digital signal processing means. Lower k of digital signals of
When the rotation speed is unstable, the first switching means selects the higher-order n-bit signal from the m-bit digital signals output from the digital signal processing means, and the second switching means selects the higher-order n-bit signal. Control means for controlling the switching means to select the k-bit signal output from the fixed data generating means and a k-bit signal output from the fixed data generating means.