JPH01252182A - Control circuit for speed of motor - Google Patents

Abstract

PURPOSE:To start a motor rapidly by using an output value from an output means at the time of the start of the motor as a command value for forced acceleration. CONSTITUTION:A counter means 14 counting an encoder signal proportional to the rotational speed of a motor is set so that a specified bit is brought to '1' and bits of orders higher than that of the specified bit to '0' when the motor is rotated at an instructed speed. An output means 20 outputs the specified bit and the bits of the higher orders in all bits of the counter means 14 as speed error signals. An output means 22 adds a value displayed by the bits lower than the specified bit and an output from the output means 22, and outputs an added value as a phase error signal. A decision means 24 sets output values from the output means 20, 22 at fixed values when displacement from the range of a value capable of represented by the specified bit and the bits of the higher orders of the result of counting is decided.

Description

[Detailed description of the invention] Table of contents Overview ・ ・ ・ ・ ・ ・ ・ ・ ・
・ ・ ・ 4 pages Industrial application fields ・・・・・・・
・Page 6: Prior art ・・・Page 7: Problems to be solved by the invention ・Page 12: Means for solving the problem ・・Page 14: Effects ・ ・
・ ・ ・ ・ ・ ・ ・ ・ ・ ・ 16 truths
Example ・ ・ ・ ・ ・ ・ ・ ・ ・
・ ・ Page 17 Effects of the invention ・・・・・・・・・・・・2
1 page summary Regarding motor speed control circuits, the purpose of this project is to provide a motor speed control circuit with improved motor start-up characteristics, using an encoder signal proportional to the motor rotation speed, and converting the period of the encoder signal digitally. In a motor speed control circuit that processes the encoder signal to obtain a speed error signal and a phase error signal, and feedback-controls the rotational speed of the motor based on these signals, a counter means for counting the period of the encoder signal and a counter means for counting the period of the encoder signal are provided. a first output means having a memory function for outputting a value as a speed error signal; an addition means for cumulatively adding the count value of the counter means; and a code for inverting the sign of the most significant bit among the bits input to the addition means. an inverting means, a second output means having a storage function for outputting the calculation result of the addition means as a phase error signal, and determining whether or not the count result of the counter means is larger than a value that can be expressed by the first output means. and a determining means, and when the determining means determines that the size is large, the output values of the first output means and the second output means are set so that the count result becomes a maximum value within a range where the determining means does not determine that the size is large. The timing of updating the storage contents of the selection means and the first output means and the second output means is determined after the encoder signal is input and the value of the speed error signal and the value of the phase error signal are determined, or after the value of the speed error signal and the phase error signal are determined, or When the determining means determines that the move is large, the selecting means selects the output values of the first output means and the second output hand so that the count result becomes the maximum value within a range where the determining means does not determine that the move is large. and storage content updating means for updating the stored content after the selection is confirmed.

Industrial applications The present invention relates to a motor speed control circuit.

Brushless Morph, which uses non-contact electronic rectification instead of a commutator, is highly reliable in terms of lifespan and electrical noise.
Application to various devices is progressing.

This brushless morph has a high degree of structural freedom, making it easy to make it lighter, thinner, shorter, and smaller, and its use as a direct drive motor is expanding because it makes it easier to maintain relative mechanical precision between the device and the motor. Such motors are widely used in applications that require highly accurate constant speed rotation, such as scanner motors for cassette type % beam printers.

Therefore, there is a need for a motor speed control circuit that allows the motor to rotate at a constant speed with high precision.

Conventional technology In a circuit that controls the speed of a brushless motor, an encoder signal proportional to the rotational speed of the motor is used, the period of this encoder signal is digitally processed to obtain a speed error signal and a phase error signal, and the signals are digitally processed. A method is known in which the data is fed back to the motor drive circuit after analog conversion (D/A conversion). In conventional motor speed control circuits of this type, digital signals are processed by a microprocessor. However, when a microprocessor is used, it becomes expensive and the processing speed is slow because it is not a dedicated circuit. Accordingly, the present inventors have previously proposed a motor speed control circuit which aims to speed up the processing time by converting the digital processing circuit, which has conventionally been implemented using a microprocessor, into a circuit suitable for IC.

FIG. 6 is a block diagram of a motor speed control circuit according to a prior application proposed by the present inventors.

In FIG. 6, 42 is a 6-bit up counter, 3
1.33.37 is a latch, 34 is a sign inverter that inverts the sign of the upper bit, 35 is a digital adder, 32.36
is a digital multiplexer, 38.39 is a delay circuit, 4
0 is an overflow detection circuit, 43 is a digital comparator, and 44 is an OR circuit.

The operation of the conventional example shown in FIG. 6 will be explained below.

Assume that the command rotational speed of the motor is fsHz, the actual rotational speed of the motor is f, h, the frequency of the reference clock generator 4 is FcHz, and the encoder signal generator 2 outputs a signal once every rotation of the motor.

Clock frequency f generated by reference clock generator 4.

If the commanded speed of the motor is f, then fc/rs
is determined to be rl 11000J or a smaller value in binary representation. rc/fs is rlllooo
'', the Samir switch 45 is set to an appropriate value to compensate for the difference, and the Samir switch 4 is set when the counter 42 counts the period of the encoder signal.
The value set to 5 is preset in the counter 42 in advance. As a result, when the period of the signal output from the encoder signal generator 2 is counted using the frequency of the reference clock generator 4 when the motor is rotating at the command speed, the value is "111000". .

The encoder signal from the encoder signal generator 2 is synchronized with the frequency of the reference clock generator 4 in the synchronization circuit 5, and then the clear signal of the counter 42, the latch 31.33.3
7 is used as a timing signal for latching an input signal and as a reset signal for the overflow detection circuit 40.

The digital multiplexer 32 has the lower 4 of the counter 42.
Enter bits. On the other hand, a value obtained by inverting only the most significant bit of the lower four bits of the counter 42 by the sign inverter 34 is input to the digital adder 35. Furthermore, the output signal of the latch 37 is fed back and input to the digital adder 35 . The overflow detection circuit 40 detects whether or not an overflow occurs when the counter 42 counts the period of the encoder signal. '' to the digital multiplexers 32 and 36, and also inputs this detection result to the OR circuit 44.

The digital comparator 43 is a circuit that receives the upper two bits of the counter output and determines whether this value matches "11" or not, and inputs the result of this determination to the OR circuit 44. Since the count value when the motor rotates at the commanded speed is determined as described above, the digital comparator 43 can omit the function of comparing the magnitudes. The output of the overflow detection circuit 40, the output of the digital comparator 43 that detects whether the upper two bits of the counter match "11", and the combination of the OR circuit 440 determine whether the calculation to obtain the error signal is performed correctly. It is now possible to know.

The output of the OR circuit 44 is sent to the digital multiplexer 32',
It functions as a data select signal of 36.

That is, if the overflow detection circuit 40 detects an overflow, or if the digital comparator 43 determines that the upper two bits of the count value of the counter 42 do not match "11", the OR circuit 44 , first from the overflow detection circuit 40 to the digital multiplexer 3.
2. Data sent to 36 (“1111” if overflow is detected, “00” if no overflow is detected)
00'') is output. On the other hand, no overflow is detected and the digital comparator 43 is "11".
”, it means that the motor is rotating near the command speed. A signal is output to select the output.

The output of the data and the detection result to the OR circuit 44 is based on the output value of the digital multiplexer 32.36 and the latch 33.36.
After being latched by the counter 37, the counter 42 is reset by a signal delayed by the delay circuit 38.

The value of the latch 33 is the motor rotational speed f and the command speed f.
It changes around "1000" depending on the size of , so
This signal can be regarded as a speed error signal with an offset. Further, the value indicated by the latch 37 is the cumulative addition of speed error signals without offset, and indicates a phase error signal.

Speed error signal output from latch 33 and latch 37
The phase error signals outputted from the circuits are each subjected to digital/analog conversion by D/A converters 10 and 11 and input to the adder circuit 12 . The adder circuit 12 adds both signals with a gain determined by the servo band, etc., and inputs this to the motor drive circuit 3 to control the motor 1 at a constant speed.

Note that 6 is a start switch, and when the start switch 6 is turned on after the power source is turned on, the rotation of the motor is started.

Problems to be Solved by the Invention However, in the circuit configuration as described above, as shown in the time chart of FIG. 7, when the motor starts,
Encoder signal generator 2 from when motor start signal is input
During the period until the first latch signal is generated, the output values of the latches 33 and 37 are undefined depending on the power-on state. Furthermore, since the counter 42 counts the period of the encoder signal, there may be errors in the output values of the latches 33 and 37 until the encoder signal generator 2 generates the second latch signal. Ta. That is, in FIG. 7, if there is an overflow of the counter as shown by the broken line between a, a correct output value will be obtained as the output value for the above-mentioned period, but if there is no overflow, the output value will be incorrect. There was a case. As described above, in the conventional control circuit, a correct output cannot be obtained until the latch signal is generated twice, and this has been a cause of inhibiting the start-up characteristics of the motor.

The present invention has been made in view of these points, and an object thereof is to provide a speed control circuit for a motor that improves the start-up characteristics of the motor.

Means to solve problems FIG. 1 shows a block diagram of the principle of the present invention.

When the motor rotates at the commanded speed, the cycle of the encoder signal proportional to the motor's rotational speed is set so that the count value is expressed in binary so that the predetermined bit is "1" and the lower bits are "0". A counter means 14 is provided for counting. Further, a first output means 20 is provided which has a storage function to output the predetermined bit and bits lower than the predetermined bit among all the bits of the counter means 14 as a speed error signal.

Further, sign inverting means 16 inverts the sign of the predetermined bit among the bits from the counter means 14, and sign inverting means 16 for inverting the sign of the predetermined bit among the bits from the counter means 14, and a sign inverting means 16 for inverting the sign of the predetermined bit among the bits output from the counter means 14, and an output bit of the sign inverting means 16 and an output bit of the counter means 14 lower than the predetermined bit. Adding means 18 for adding the value indicated by the bit string consisting of bits and the output value of the second output means 22, and a second output means 22 having a storage function for outputting the calculation result of the adding means 18 as a phase error signal are provided. Additionally, a determining means 24 is provided for determining whether or not the result of counting the period of the encoder signal is out of the range of values that can be expressed by the predetermined bits and bits lower than the predetermined bits.

In addition, when the determining means 24 determines that it is out of order,
a selection means 26 for selecting the output values of the first output means 20 and the second output means 22 so that the count results will be the maximum or minimum value within the range depending on whether the output values are out of the range; and the first output means 2
0 and the storage contents of the second output means 22 are updated after the encoder signal is input and the value of the speed error signal and the value of the phase error signal are determined, or the rotation speed of the motor is slower than the command speed. , and the determination means 24 determines that the output value of the counter means 14 is larger than the value that can be expressed by the first output means 20, and the selection means 26 determines that the rotation speed of the motor is higher than the command speed. The storage content updating means 28 selects the value representing the slowest value and then updates the stored content.

Function As described above, the counter means 14 is set so that the count value when the motor rotates at the commanded speed takes a special value. For example, the bit length of the counter means 14 is 6, the output to the D/A converter 10°11 is 4 bits,
When using the counter means 14 as a down counter,
The count value when the motor rotates at the commanded speed is set to, for example, "001000J." When the counter means 14 is used as an up counter, the count value is set to, for example, rlllooo. Further, if the bit length of the counter means 14 and the input bit length to the D/A converter 10.11 are equal at 4 bits, the count value is set to, for example, "1000".

By setting the count value of the counter means 14 in this way, a speed error signal and a phase error signal obtained by cumulatively adding the speed error signal can be obtained from the count value of the period of the encoder signal corresponding to the rotational speed of the motor. Addition means 18 for determining and determination means 24 for determining the range in which addition is correctly performed.
can be easily configured.

Furthermore, a memory content updating means 28 is provided, and the first output means 2
0 and the timing of updating the storage contents of the second output means 22 not only when the encoder signal is input, but also when the output value of the counter means 14 is larger than the value that can be expressed by the first output means 20. 24 is determined, the motor can be started up quickly when the motor starts up, and the start-up characteristics can be significantly improved.

Embodiments The present invention will be explained in detail below based on embodiments shown in the drawings. In the description of the embodiment, the same components as those of the conventional circuit shown in FIG. 6 will be denoted by the same reference numerals, and the description thereof will be omitted.

FIG. 2 is a block diagram of an embodiment of the present invention.

In the figure, 7 is a pulse generator that generates a pulse at the same time as the start switch 6 is turned on, and 46 and 47 are OR circuits. The OR circuit 46 receives an overflow signal from the counter 42, receives a signal from the encoder signal generator 2 via the synchronization circuit 5, or receives a pulse from the pulse generator 7, Delay circuit 3
A latch signal is generated to latches 33 and 37 through 9.

The OR circuit 47 receives one word from the pulse generator 7 when the motor starts, and forces the overflow detector 40 into a state in which an overflow is detected. The structure and operation of other parts are the same as the conventional circuit shown in FIG. 6, so their explanation will be omitted.

FIG. 4 is a time chart of the above-described embodiment. At the same time that the start switch 6 is turned on and a motor start signal is generated after a predetermined period of time has elapsed after the power is turned on, the pulse generator 7 generates a pulse. This pulse is OR
is input to the overflow detector 40 via a circuit 47;
The overflow detector 40 is brought into a state in which an overflow is detected. This allows digital multiplexer 3
Data "1111" is sent to the terminals 2 and 36, and this data is selected by the signal from the OR circuit 44.

Since the signal from the pulse generator 7 is also input to the OR circuit 46, the data "1111" selected by the digital multiplexer 32.36 is latched into the latch 33.37 with a predetermined delay time.

Therefore, the correct output can be obtained from the latches 33 and 37 almost at the same time as the start switch 6 is turned on, and the motor can be started quickly.

The overflow signal indicated by a broken line in FIG. 4 indicates that an overflow may or may not occur, and when an overflow occurs, the data "1111J" Since it can be latched with a predetermined delay time, it indicates that the motor is ready to generate the correct output when starting.However, if the counter does not overflow within the predetermined period, the pulse generator Correct output can only be obtained by latching data 1111j based on the signal from 7. With the above configuration, latches 33 and 37 will rotate the motor in the normal rotation direction from the time the start signal is applied. Produces output that accelerates quickly.

FIG. 3 shows a block diagram of another embodiment of the present invention,
The pulse generator 7 and OR circuit 47 are omitted from the embodiment shown in FIG. 2, and the other configurations are completely the same as the embodiment shown in FIG.

As shown in the time chart of FIG. 5, in this embodiment, the counter 42 is
This is effective when it is known that the counter 42 will generate an overflow signal, and in most practical applications, the counter 42 will generate an overflow signal at least once before starting the motor. Therefore, this embodiment is effective in most cases in actual circuits, and from the time the start signal is applied, the latch 33°37
outputs an output to quickly accelerate the motor in the normal rotational direction.

Effects of the Invention As detailed above, according to the present invention, by setting the output values of the first output means and the second output means at the time of starting the motor as a command value for forcibly accelerating the motor, the motor can be started quickly. This has the effect of making it possible to

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram of an embodiment of the invention, Fig. 3 is a block diagram of another embodiment of the invention, and Fig. 4 is a time chart of the embodiment of Fig. 2. , FIG. 5 is a time chart of the embodiment of FIG. 3,
FIG. 6 is a block diagram of the conventional example, and FIG. 7 is a time chart of the conventional example. DESCRIPTION OF SYMBOLS 1...Motor, 2...Encoder signal generator, 3...Drive circuit, 4...Reference clock generator, 7...Pulse generator, 14...Counter means, 16... sign inversion means, 18...addition means 20
...first output means, 22...second output move, 24
...determination means, 26.. selection means, 28.
...Memory content update means, 31.33.37...Latch, 32.36...Digital multiplexer, 3.4...
・Sign inverter, 35...Digital adder 40・
...Overflow detection circuit, 42...Counter, 43...Digital comparator, Recruitment 2 figure 0x example time night figure 4

Claims (2)

[Claims] (1) Using an encoder signal proportional to the motor rotation speed, digitally process the cycle of the encoder signal to obtain a speed error signal and a phase error signal, and feedback control the motor rotation speed based on these signals. In a motor speed control circuit, when the motor rotates at a commanded speed, the count value is expressed in binary, with a predetermined bit being "1", all bits lower than that bit being "0", and bits higher than that bit being "0". all"
a counter means (14) for counting the cycle of the encoder signal, which is set to be "0" or all "1"; First output means (20) having a memory function to output bits as a speed error signal
and sign inverting means (16) for inverting the sign of the predetermined bit among the output bits of the counter means (14); It has an addition means (18) for adding a value indicated by a bit string consisting of lower bits than the predetermined bits and a phase error signal, and a storage function for outputting the calculation result of the addition means (18) as the phase error signal. a second output means (22); a determination means (24) for determining whether the count result of the period of the encoder signal is out of the range of values that can be expressed by the predetermined bit and lower bits; If the determination means (24) determines that the determination is off,
The output values of the first output means (20) and the second output means (22) are selected so that the count results are the maximum or minimum value within the range, depending on whether the deviation is large or small. a selection means (26) for selecting, and the first output means (
20) and the second output means (22) after the encoder signal is input and the value of the speed error signal and the phase error signal are determined, or after the rotational speed of the motor is at the command speed. and the output value of the counter means (14) is larger than the value that can be represented by the first output means (20), the determination means (24)
), and the selection means (26) selects a value indicating that the rotational speed of the motor is the slowest relative to the commanded speed. motor speed control circuit. (2) When a motor start signal is input, regardless of the value of the counter means (14), if the value of the counter means (14) is off to a larger value, the determination means (24) The signal is determined by the determining means (
24. The motor speed control circuit according to claim 1, further comprising means for inputting to the motor speed control circuit.