JPH01238482A - Speed controller - Google Patents

Speed controller

Info

Publication number
JPH01238482A
JPH01238482A JP63062023A JP6202388A JPH01238482A JP H01238482 A JPH01238482 A JP H01238482A JP 63062023 A JP63062023 A JP 63062023A JP 6202388 A JP6202388 A JP 6202388A JP H01238482 A JPH01238482 A JP H01238482A
Authority
JP
Japan
Prior art keywords
motor
speed
counter
value
pulse
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63062023A
Other languages
Japanese (ja)
Inventor
Shigeru Jinnai
神内 茂
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP63062023A priority Critical patent/JPH01238482A/en
Publication of JPH01238482A publication Critical patent/JPH01238482A/en
Priority to US08/126,758 priority patent/US5444345A/en
Pending legal-status Critical Current

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  • Control Of Electric Motors In General (AREA)

Abstract

PURPOSE:To speed-control a motor in a high accuracy by obtaining data regarding the irregularity of an FG pulse during several resolutions from a constant speed at the time of motor start, and compensating it therewith. CONSTITUTION:When the start command of a motor is output, a CPU 1 starts a motor 5. When attainment of the motor to a normal speed is detected from the value of a counter 4 for counting an FG pulse, data regarding the irregularity of the FG pulse is obtained during several revolutions. The speed of the motor is controlled by adding a correction on the basis of the data. Thus, even a motor having low accuracy of the FG can be accurately speed-controlled.

Description

【発明の詳細な説明】 〔産業上の利用分野] 本発明は、例えばビデオテープレコーダ(VTR)に用
いるモータの速度制御装置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a speed control device for a motor used in, for example, a video tape recorder (VTR).

〔従来の技術〕[Conventional technology]

従来は、FGの精度が非常に良いという前提のもとにモ
ータの速度制御を行なっていた。
Conventionally, motor speed control has been performed on the premise that the FG accuracy is very high.

(発明が解決しようとする課題) しかしながら、従来の速度制御装置においては、FGの
精度が良くないと、ジッタを少なくすることができない
という欠点があった。
(Problem to be Solved by the Invention) However, the conventional speed control device has a drawback that jitter cannot be reduced unless the FG accuracy is good.

そこで本発明の目的は、以上のような問題を解消し、高
精度に速度制御することができる装置を提供することに
ある。
SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and provide a device that can control speed with high precision.

〔課題を解決するための手段〕[Means to solve the problem]

本発明はモータのFGパルスをカウントするカウンタと
、該カウンタの計測値を用いて前記モータか定速に達し
てから数回転の間にFGパルスのばらつきに関するデー
タを作成するデータ作成手段と、該作成手段のデータに
基づい°C前記モータの回転制御を補正する手段とを具
えたことを特徴とする。
The present invention includes a counter that counts FG pulses of a motor, a data creation means that uses the measured value of the counter to create data regarding variations in FG pulses during several rotations after the motor reaches a constant speed, and The invention is characterized by comprising means for correcting the rotational control of the motor by °C based on the data of the generating means.

〔作 用〕[For production]

本発明によれは、例えばモータの起動時に、定速になっ
てから数回転の間にFGのばらつぎに関するデータを得
て、それを用いて補正を加えてモータの速度を制御する
ことによって回転精度を向上させることができる。
According to the present invention, for example, when starting the motor, data regarding FG variation is obtained during several rotations after reaching a constant speed, and the data is used to make corrections to control the speed of the motor. Accuracy can be improved.

〔実施例〕〔Example〕

第1図〜第3図は本発明の実施例を示し、第1図は本発
明実施例のブロック図であり、第2図はFGパルスの波
形を示し、第3図は本実施例のフローチャートである。
1 to 3 show embodiments of the present invention, FIG. 1 is a block diagram of the embodiment of the invention, FIG. 2 shows the waveform of the FG pulse, and FIG. 3 is a flowchart of the embodiment. It is.

第1図の2は補正のためのデータを記録しておくための
RAMであって、後述のようなP、N。
Reference numeral 2 in FIG. 1 denotes a RAM for recording data for correction, and includes P and N as described later.

C,lipなどのレジスタを有する。3はモータ5を回
転させるためのトライバ、4はFG比出力第2図に示す
a)をカラン1−するカウンタ、1はRAM2、カウン
タ4よりの人力を処理し、トライバ3に制御値を出力す
るCPUである。
It has registers such as C and lip. 3 is a driver for rotating the motor 5; 4 is a counter for calculating the FG ratio output a) shown in Fig. 2; 1 is a RAM 2, which processes the human power from the counter 4 and outputs a control value to the driver 3; It is a CPU that performs

カウンタ4は立上りにおいてカウント値をラッチし、[
l:PUlはラッチされた値を読み出す。またラッチす
ると同時にカウンタ4は0にクリアされる。
Counter 4 latches the count value at the rising edge, and [
1: PU1 reads the latched value. Furthermore, the counter 4 is cleared to 0 at the same time as the latch.

第3図のフローチャートを用いて本発明の詳細な説明を
する。
The present invention will be explained in detail using the flowchart shown in FIG.

まずステップ(以下S)1においてモータのスタート指
令を待ち、スタート指令が来ると52においてモータを
起動する。ついでS3でFGの立上りまで待って、S4
でカウンタ4の値を入力する。ついでS5で人力した値
よりほぼ定常の速度(たとえば定速の95%)に達した
かを判断し、達していなければ、はぼ定速になるまでS
3、S4、S5をくり返す。はぼ定速になればS6に行
き、FGの立上りまで待って、S7でカウンタ4の値を
入力する。
First, in step (hereinafter referred to as S) 1, a start command for the motor is waited for, and when the start command is received, the motor is started in 52. Next, wait until FG rises in S3, and then switch to S4.
Enter the value of counter 4 with . Next, in S5, it is determined whether the speed has reached an almost constant speed (for example, 95% of the constant speed) from the manually input value, and if it has not reached it, then the S speed is continued until the constant speed is reached.
3. Repeat S4 and S5. When the speed becomes almost constant, the process goes to S6, waits until FG rises, and inputs the value of counter 4 in S7.

ついでS8で補正を行なわない速度制御を行い、S9で
定常速度に達したかを判断し、達していなければ定速に
なるまでS6、S7、S8、S9をくり返す。
Then, in S8, speed control without correction is performed, and in S9, it is determined whether the steady speed has been reached. If the steady speed has not been reached, S6, S7, S8, and S9 are repeated until the constant speed is reached.

定速になれば510へ進み、レジスタPとNをOとする
。ついで511でFGの立−トリまで待ち、512でカ
ウンタの値を人力し、その値をCとする。
When the speed becomes constant, the process advances to 510 and registers P and N are set to O. Next, in step 511, the program waits until the FG is set up, and in step 512, the value of the counter is entered manually, and that value is set as C.

ついでS13でlipにC−Goを加算する。なお11
pはスタート時に0にクリアしておく。coはシックが
ない場合の定速時のカウンタの値である。
Then, in S13, C-Go is added to lip. Note 11
Clear p to 0 at the start. co is the value of the counter at constant speed when there is no sick.

ついで514で補正を行なわない制御を行い、515て
Pに1を加える。ついで516でPがPoに等しくなっ
たかを判断し、等しくなければ、等しくなるまでSll
へ518をくり返す。Poは1回転のFGの数である。
Then, in step 514, control is performed so that no correction is performed, and in step 515, 1 is added to P. Next, in 516, it is determined whether P is equal to Po, and if not, Sll is held until they become equal.
Repeat 518. Po is the number of FGs in one rotation.

S16で等しくなると、517に進み、Pを0としNに
1を加える。
If they are equal in S16, the process proceeds to 517, where P is set to 0 and N is incremented by 1.

ついで518でNがNoに等しくなったかを判断し、等
しくなければ、等しくなるまで511−518をくり返
す、NOは1以上の整数である。
Next, in 518, it is determined whether N is equal to No. If not, steps 511-518 are repeated until they become equal. NO is an integer of 1 or more.

518で等しくなると、S19 に進み、up(p−o
〜Po−1)をNoで割る。この時、Hpの和が0とな
るように切上げ、切捨てを行う。
If they are equal at 518, the process advances to S19 and up(p-o
~Po-1) divided by No. At this time, round up and round down so that the sum of Hp becomes 0.

ついで520でFGの立上りまで待ち、521てカウン
タの値を人力する。ついでS22で補正を加えた速度制
御を行う。補正の計算例を示すと、y=に、 (C+H
p−Go)十に2Σ(C+1Ip−Go) + K3y
:制御値 C:カウンタの値 に1、K2、K、:定数 上に示す式により計算を行い、I(pを補正項として加
えである。なお、補正なしの制御は上式より)Ipをと
ったものである。
Next, in step 520, it waits until FG rises, and in step 521, the value of the counter is input manually. Then, in S22, speed control with correction is performed. To show an example of correction calculation, for y=, (C+H
p-Go) 10 to 2Σ(C+1Ip-Go) + K3y
:Control value C: Counter value 1, K2, K, :Constant Calculate by the formula shown above and add I(p as a correction term.In addition, control without correction is from the above equation) Ip. This is what I took.

ついで523でPをPalをPoで割った余りとする。Then, in 523, let P be the remainder of Pal divided by Po.

524でモータのストップ指令が来るまで520〜52
4をくり返し、ストップ指令が来ると、S25でモータ
を停止しSlへもどる。
520 to 52 until the motor stop command comes at 524
4 is repeated, and when a stop command is received, the motor is stopped in S25 and the process returns to Sl.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、FGの精度の良くないモータでも高精
度で速度制御することかでき、たとえはシックを少なく
することが可能となり、調整等を容易にする効果がある
According to the present invention, it is possible to control the speed with high precision even with a motor whose FG is not accurate, and it is possible to reduce sick, for example, and to facilitate adjustment.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明実施例のブロック図、 第2図はFGパルスの波形を示す図、 第3図は本実施例の動作フローチャー1−である。 第1図 第2図 FIG. 1 is a block diagram of an embodiment of the present invention, Figure 2 is a diagram showing the waveform of the FG pulse; FIG. 3 is an operational flowchart 1- of this embodiment. Figure 1 Figure 2

Claims (1)

【特許請求の範囲】[Claims] 1)モータのFGパルスをカウントするカウンタと、該
カウンタの計測値を用いて前記モータが定速に達してか
ら数回転の間にFGパルスのばらつきに関するデータを
作成するデータ作成手段と、該作成手段のデータに基づ
いて前記モータの回転制御を補正する手段とを具えたこ
とを特徴とする速度制御装置。
1) a counter that counts the FG pulses of the motor; a data creation means that uses the measured values of the counter to create data regarding variations in the FG pulses during several revolutions after the motor reaches a constant speed; A speed control device comprising: means for correcting rotational control of the motor based on data of the means.
JP63062023A 1988-03-17 1988-03-17 Speed controller Pending JPH01238482A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP63062023A JPH01238482A (en) 1988-03-17 1988-03-17 Speed controller
US08/126,758 US5444345A (en) 1988-03-17 1993-09-27 Speed control apparatus for a motor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63062023A JPH01238482A (en) 1988-03-17 1988-03-17 Speed controller

Publications (1)

Publication Number Publication Date
JPH01238482A true JPH01238482A (en) 1989-09-22

Family

ID=13188160

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63062023A Pending JPH01238482A (en) 1988-03-17 1988-03-17 Speed controller

Country Status (1)

Country Link
JP (1) JPH01238482A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55103090A (en) * 1979-01-29 1980-08-06 Sony Corp Speed controller for motor

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55103090A (en) * 1979-01-29 1980-08-06 Sony Corp Speed controller for motor

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