JPS63308567A - Speed detector - Google Patents

Abstract

PURPOSE:To enable accurate detection of speed even for an apparatus vary frequency in the starting and stopping of a pulse generator, by latching the contents of a counter according to a scan pulse or a synchronization demand signal. CONSTITUTION:An N' latch buffer 9 is added between a counter 6 and an O latch buffer 8 to latch the contents of the counter 6 according to an input of a scan pulse P1 or a synchronization demand signal P2. The pulse P1 is outputted from a scan pulse generator 2 at each fixed cycle set with a scan time setter 3, but when the signal P1 is inputted through an OR circuit OR1, the pulse P1 is generated in a specified time after the inputting thereof to synchronize a scanning. An N latch buffer 7 latches counting contents at each pulse P1 while the buffer 9 latches the contents of the counter 6 at a time of the pulse P1 or the signal P2 and moreover, a buffer 8 latches the contents of the buffer 9 at each pulse P1. This enables accurate detection of revolutions of a pulse generator 4 even in a circuit having a scan synchronization.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital speed detection device that is designed to ensure correct speed detection even when a pulse generator is installed in a device that frequently starts and stops.

[Conventional technology]

FIG. 1 shows a block diagram of a conventional speed (or rotational speed) detection device, in which 1 is a clock pulse generator, 2 is a scan pulse P that is sent out at every time specified by a scan time setting device 3. DOWN counter; 4 is a pulse generator driven by a drive source such as an electric motor; 5 is a pulse waveform converter that converts into a positive or negative pulse signal depending on the rotational direction of the pulse generator 4; 6 is the pulse waveform converter. IJP counting 5 output pulses
- A counter consisting of a DOWN counter, 7 a N latch buffer that latches the contents of the counter 6 every time a scan pulse P is input, and 8 a latch buffer 8 that latches the contents of the N latch buffer 7 every time a scan pulse P1 is input. 0 latch buffer, 11 is an arithmetic processing unit that reads the contents of the N latch buffer and 0 latch buffer each time the scan pulse P is input, and calculates the speed (or number of revolutions); 1° is a crystal oscillator.

FIG. 2 shows a time chart, and in the present invention, a scan pulse P1 (interrupt pulse) is sent out from the counter 2 at regular intervals set by the scan time setter 3, and the pulse generator 4 is sent out in the arithmetic processing unit II. The scan pulse generator 2 calculates the speed (or rotational speed) of the scan pulse P,
is output and reconfigured.

The N latch buffer 7 latches the contents of the counter 6 at the timing of the scan pulse P.

For example, the content n1 of the counter 6 is latched by the scan pulse at point A, and is maintained at n until the next point B.

Similarly, nz at point B, n2 at point C. At point B, it changes like n4.

The 0 latch buffer 8 latches the contents of the N latch buffer 7 at the timing of the scan pulse P1. Therefore, the data from the N latch buffer 7 one scan ago remains in the 0 latch buffer 8.

The arithmetic processing unit 11 performs arithmetic operations as shown in the flowchart of FIG. 3 each time a scan pulse P is input (scan interruption).

That is, the speed (or rotational speed) N is calculated as shown in the following equation.

However, nN: N latch buffer read value n, :0 latch buffer 8 read value K: Proportionality constant TS Niscan time N: Number of revolutions of pulse generator 4 [Problem to be solved by the invention] Operating mode in manufacturing of the product When this type of speed detection device is installed in a device that frequently switches between speed control, torque control, and position control, the scan pulse generator 2 has a It is effective to provide a synchronization request signal like this. However,
- Since the instantaneous scan time changes, there is a problem that speed detection becomes inaccurate and product variations occur.

This can be explained using the time chart shown in FIG. 4 as follows.

That is, as shown in Figure 4, the scan pulses C and D
If synchronization request signal P2 is given between
Scan pulse D will be generated later. Therefore, the scan pulse interval T is larger than Ts. If there is such scan synchronization, the speed (or number of rotations) N
' is expressed by the following equation, and has the relationship N≠N' with equation (1) (1). Therefore, if N' is used for control, variations will occur in the products manufactured by the manufacturing equipment.

Therefore, in the present invention, even when a synchronization request signal is given (1
) is intended to be performed in the arithmetic processing unit 11.

[Means for solving problems]

In order to solve the above-mentioned problems, the present invention does not use the method of latching the contents of the N latch buffer 7 in the 0 latch buffer 8, but instead latches the contents of the N latch buffer 7 in the 0 latch buffer 8. An N' latch buffer that latches the contents of the counter 6 is newly added between the counter 6 and the O latch buffer 8, and even when the synchronization request signal P2 is applied, the 0 latch buffer 8 has a scan setting time Ts.
The content of the minute counter 6 is configured to be latched so that the arithmetic processing unit 11 calculates the equation (1) instead of the equation (2).

〔Example〕

FIG. 5 shows an embodiment of the present invention, which differs from the conventional device shown in FIG.
The scan pulse P is applied to the scan pulse generator 2 via the scan pulse P.

Alternatively, an N' latch buffer 9 is newly added between the counter 6 and the O latch buffer 8, which latches the contents of the counter 6 in response to the input of the synchronization request signal P2.

With this configuration, even when the synchronization request signal P2 is given. A counter value similar to that of the conventional device shown in FIG. 1 is latched in the 0 latch buffer 8.

FIG. 6 shows a time chart of signals and counter values of each part in FIG. 5, and the operation of the embodiment apparatus will be explained with reference to this time chart as follows.

The scan pulse generator 2 generates a scan pulse P every fixed time Ts, similar to the conventional device shown in FIG.

However, when the synchronization request signal P2 is input, both are set, and a scan pulse is generated Ts after that time to synchronize the scan.

On the other hand, the N latch buffer 7 latches the contents of the counter 6 at every scan pulse, the N' latch buffer 9 latches the contents of the counter 6 at every scan pulse or synchronization request signal timing, and the 0 latch buffer 8 latches the contents of the counter 6 at every scan pulse or synchronization request signal timing. The contents of the latch buffer 9 are latched every scan pulse.

Therefore, the number of rotations of the pulse generator between CDs where the scan time is extended is calculated as s, so the calculation s according to the calculation flowchart in Figure 3 holds true, and even in a circuit with scan synchronization, the pulse generator rotates at 40 rotations. This means that the number can be detected correctly.

In the above embodiment, the case where the pulse generator rotates in forward and reverse directions was taken as an example and explained, but if the pulse generator rotates only in one direction, the pulse waveform converter may not be used.

〔Effect of the invention〕

As described above, according to the present invention, even when this type of digital speed detection device is applied to a device that needs to provide a synchronization request signal, accurate speed detection can be performed, and the operation mode changes frequently. This is an excellent digital speed detection device for use in such devices.

[Brief explanation of drawings]

Fig. 1 is a block diagram of the conventional device, Fig. 2 is a time chart of signals and counter values of each part in Fig. 1, and Fig. 3 is a time chart of the signals and counter values of each part in Fig. 1.
The figure shows an operation flowchart of the arithmetic processing device in FIG. 1, FIG.
The figure is a block diagram of an embodiment of the present invention, and FIG. 6 is a time chart of signals and counter values of various parts in the embodiment. 1... Clock pulse generator 2... Scan pulse generator 3... Scan time setter 4... Pulse generator 5... Pulse waveform converter 6... Counter 7... N latch buffer 8...0 latch buffer 9...N' latch buffer 10...Crystal oscillator 11... Arithmetic processing unit. He He Hezu Nobu U QQ

Claims (1)

[Scope of Claims] A DOWN counter that sends a scan pulse using a clock pulse as an input signal and is set by the scan pulse and a synchronization request signal, and a counter that counts output pulses sent from a pulse generator; an N latch buffer that latches the contents of the counter in response to an input of a pulse; an N' latch buffer that latches the contents of the counter in response to an input of the scan pulse or a synchronization request signal; A speed detection device comprising: an O latch buffer that latches the contents of the N' latch buffer according to an input; and an arithmetic processing device that reads the contents of the N latch buffer and the O latch buffer to calculate a speed. .