JPH01238055A - Charge transfer type solid-state image sensing device - Google Patents

Abstract

PURPOSE:To improve transfer efficiency between horizontal CCD by making a clearance between a horizontal transfer gate and a horizontal CCD, or a clearance between horizontal CCD and a transfer gate not exceed a specific size. CONSTITUTION:Plane is shaped by providing an impurity layer 14 to make CCD a buried layer and an electrode 12 of horizontal CCD, and by making a clearance 11-1 from a horizontal transfer gate 4-1 to horizontal CCD or a clearance 11-2 from horizontal CCD to a horizontal transfer gate 4-2 not exceeding 1mum. According to this constitution, it is possible to eliminate electric potential generated in horizontal CCDF, to reduce leaving of charge, to improve transfer efficiency, and to prevent development of color mixture or fixed pattern noises.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a photoelectric conversion element on a semiconductor substrate, and a charge transfer element for reading out optical information of each element.
The present invention relates to a solid-state image sensor using a coupled device (hereinafter abbreviated as CCD).

[Conventional technology]

Solid-state image sensors require a resolution equivalent to that of the imaging electron tubes used in current television broadcasting, and for this reason they use picture elements (photoelectric conversion elements) arranged in approximately 500 pixels in the vertical direction and 500 to 1000 pixels in the horizontal direction. ) matrix and corresponding scanning element are required. In addition, as a color image sensor, in order to efficiently separate color signals, multiple columns (2
It is conceivable to use horizontal CCDs (1 or more), thereby making it possible to read the color signals independently and reducing the driving frequency of the horizontal CCDs. However, this requires a transfer gate (with a switch mechanism) that serves as a bridge between the horizontal CCDs.

FIG. 3 shows the basic configuration of a solid-state image sensor using multiple rows of horizontal CCDs (regarding multiple rows of horizontal CCDs, there is a prior invention patent application No. 1983-248116, etc.).

Here, 1 is a photoelectric conversion element made of, for example, a photodiode, 2 is a vertical CCD that sends signal charges accumulated in the photoelectric conversion element group to a horizontal CCD shift register, 5-1.5-
2 is the output terminal for the signal from the vertical CCD, 6-1.6-2
horizontal CCDs (only two are shown in this figure, but any number may be provided) for sending the signal to the camera. Here 7-1.7-2.7-3.7-4 is a vertical clock pulse generator and 8-1.8-2 is a horizontal clock pulse generator. Here, the vertical CCD is driven by a 4-phase clock and the horizontal CCD is driven by a 2-phase clock pulse, but each has 2 phases.

It may be driven using three phases, four phases, etc., and 3 sends the charges accumulated in the photoelectric conversion element to the vertical CCD shift register. Vertical transfer gates 4-1 and 4-2 are vertical CCDs.
A horizontal transfer gate is shown that sends the signal charge of the shift register to the horizontal CCD shift register. Here, transfer gate 4
-1 can be omitted if unnecessary, 0, and 9-1
, 9-2 indicates the direction in which signals flow from the vertical CCD shift register to the output terminal. If the nine elements are left as they are, they will be black and white elements, but if a color filter is stacked on top of the photoelectric conversion element, each photoelectric conversion element will has color information and becomes a color element.

[Problem that the invention seeks to solve]

In the above-mentioned conventional technology, when the signal charge of the vertical CCD shift register is sent to the horizontal CCD shift register using the transfer gate 4-1 (having a switch mechanism) as a bridge, or when the signal charge of the horizontal CCD shift register is sent to the horizontal CCD shift register using the transfer gate 4-1 (having a switch mechanism) as a bridge,
2 (with a switch mechanism) as a bridge to the next stage (outer) horizontal CCD shift register, the joint between the transfer gate and the horizontal CCD (the gap that inevitably exists between the gate and the CCD) ) Alternatively, no consideration was given to the planar configuration of the transfer gate, resulting in a problem of deterioration of transfer efficiency.

Below, using FIG. 4, the configuration around the transfer gate in question and the cause of the deterioration of transfer efficiency in that part will be explained.

FIG. 4(a) is a diagram showing a planar layout configuration of a portion indicated by 10 of the element shown in FIG. 3.

4-1.4-2 is a horizontal transfer gate (for example, first layer of polycrystalline silicon), and 12 is an electrode forming a horizontal CCD (for example, second layer of polycrystalline silicon).

3J1 polycrystalline silicon may be used. ), 14 is CCD
An impurity layer (for example, an n-layer) that makes it an embedded type.

This layer is not necessary if the CCD is a surface type).

11-1.11-2 is the gap from the transfer gate to the buried channel of the horizontal CCD, or the horizontal CCD.
It represents the gap from CD to the transfer gate, and L indicates the gap dimension.

Figure 4(b) shows the cross-sectional structure when signal charges are transferred in the vertical direction (this is the cross-sectional structure when cut along the section A-A' in Figure 4(a)). be). Here, 13 indicates an insulating film.

FIG. 4(c) shows the potential formed during signal transfer in each region of the structure shown in FIG. 4(b).

During the horizontal blanking period, the charge Qs is sent from the vertical CCD to the horizontal CCD through the horizontal transfer gate, shown as 4-1, and the clocked charge Qs is the high level that was applied to the gate electrode of the horizontal CCD. By turning off the voltage, the potential increases by ΔVt and is sent below the horizontal transfer gate electrode, indicated at 4-2. Here, a gap (L) of several μm usually occurs in the region shown at 11 in FIG. 4(a) (between the transfer gate and the horizontal CCD). As a result, as shown in FIG. 4C, a potential barrier (δ) is formed, resulting in charge remaining QR, which poses a problem in terms of transfer efficiency. The reason why a potential barrier occurs here is that the channel width is actually different between the part 11 and the horizontal CCD part 14, so a so-called narrow channel effect occurs in the narrow region 11. As a result, the threshold value VT in the region indicated by 11 increases, and a potential barrier occurs.

The remaining charge QR causes color mixture and noise. In order to suppress this color mixture and noise to a non-problematic level, it is necessary to reduce the loss due to leftovers to less than 0.2% (transfer efficiency is 99.8%).
% or more).

FIG. 5 shows the relationship between transfer efficiency and gap size measured using a prototype device manufactured by the inventors. This measurement result shows that the larger the gap, the lower the transfer efficiency, and in order to satisfy the transfer efficiency of 99.8%, the gap size must be increased by 1.
It can be seen that it must be less than μm.

The purpose of the present invention is to reduce the potential barrier generated in the portion shown by 11 in FIG.
The objective is to improve the transfer efficiency between horizontal CCDs without causing deterioration in the transfer efficiency of D itself.

[Means for solving problems]

The above purpose is to reduce the gap between the horizontal transfer gate and the horizontal CCD, or the gap between the horizontal CCD and the transfer gate to 1 μm or less,
Furthermore, this can be achieved by devising the planar configuration of the gap.

〔Example〕

Hereinafter, the details of the present invention will be explained using examples.

Figure 2 shows a general charge transfer type image sensor using multiple rows (n rows in this case) of horizontal CCDs. In this figure, the 4-1st transfer gate may or may not be used. ), FIG. 1 is similar to FIG. 2, 10-1.10-2.・
. . . shows the layout configuration of the portion indicated by 10-1 and 10-2 of the portion indicated by 10-n according to the present invention.

In FIG. 1, 4-1 is the first horizontal transfer gate 4-2.
14 is a second horizontal transfer gate, and 14 is an impurity layer (for example, an n-layer) that makes the CCD a buried layer.

(Not required if the CCD is a surface type), 12 is a horizontal C
CD electrodes 11-1.11-2 are from the transfer gate,
It represents the gap leading to the horizontal CCD, and L indicates its dimension. Here, the difference between this embodiment and the conventional example shown in FIG. 4(a) is that the gap between the horizontal transfer gate and the horizontal CCD,
Alternatively, a planar configuration is adopted in which the gap from the horizontal CCD to the horizontal transfer gate is 1 μm or less. As a result, the potential barrier that has conventionally been generated under the electrodes of the horizontal CCD becomes sufficiently low, and the transfer efficiency can be improved, making it possible to obtain a transfer efficiency of 99.8% or more.

Further, FIG. 6 shows a planar configuration in which the present invention exhibits the most effect. This embodiment shows a planar configuration in which there is no gap between the horizontal transfer gate and the horizontal CCD, or a gap between the horizontal CCD and the transfer gate (that is, the gap size is 0 μm).

Other embodiments are shown in FIGS. 7 and 8. In FIG. 7(a), the gap size is 0 μm and the configuration is the same as that shown in FIG. 6, but the width Wb of the portion where the horizontal transfer gate is coupled to the horizontal CCD is made smaller than the portion indicated by W&. It is configured as follows. Figures (b) and (c) are diagrams showing the effects of this embodiment. Figure (b) has the same shape as Figure 6, when the transfer gate causes mask shift toward the horizontal CCD side. It shows. Further, arrow a indicates the direction in which an electric field is applied when charges are transferred in the direction of arrow 6 in the horizontal CCD. The figure (c) has the shape of the figure (a),
FIG. 7B is a diagram showing the direction of the electric field when a mask shift similar to that in FIG. 7(b) occurs. As can be seen by comparing Fig. 7(b) and (Q), the electric field during horizontal CCD charge transfer is more likely to be applied when the configuration is such that Wa>Wb than when the configuration is such that Wa=Wb. Therefore, there is an advantage that transfer between the transfer gate and the horizontal CCD can be performed efficiently without deteriorating the transfer efficiency of the horizontal CCD itself.

That is, in FIG. 7(b), the electric field in the b direction is O, but
In Figure 7(c), the electric field in the b direction has a quantity C,
Transfer efficiency during horizontal CCD charge transfer can be maintained in a good state.

FIG. 8 is an embodiment having the same effect as FIG. 7(,).

FIG. 9 shows an embodiment of a driving method for further increasing transfer efficiency. First, FIG. 9(b) shows the potential relationship between the transfer gate and the horizontal CCD in the conventional driving method. φ
TG(L) e φ↑a(H) is a potential formed on the transfer gate electrode F when a low level voltage and a high level voltage are respectively applied to the transfer gate. φCCD(L) t
φcaD(H') is a potential at which a CCDCD electrode is formed when a low level voltage and a high level voltage are applied to each horizontal CCD. In this driving method, the potential relationship between the transfer gate and the horizontal CCD is φTO(L) >φcCn(+
,)>φcaD()I)>φTO(H), and when the transfer goo1-pulse moves from high level to low level, part of the charge -p- flows back to the inner horizontal CCD 14-1 (arrow B) As a result, transfer efficiency deteriorates. (Originally, it is desirable that all the main charges be transferred to the horizontal CCD 14-2 (arrow F)).

On the other hand, FIG. 9(c) shows the potential relationship formed in the transfer gate F and the horizontal CCDF by the driving method of the present invention.
' TO (L), φ' T (II (H) are the potentials formed when low level voltage and high level voltage are applied to the transfer gate, respectively, φ' CcD (L,) l φ' cc
o(o) are potentials formed when a low level voltage and a high level voltage are applied to the horizontal CCD, respectively. In the driving method of the present invention, the potential relationship between the transfer gate and the horizontal CCD is φ'C0D(L)>φ'To(L)>φ' ra
(o)>φ' C0D(H), and the operation in which a portion of the transferred charge is temporarily accumulated in the transfer gate F disappears. Therefore, when the transfer gate pulse goes from high level to low level, some of the charge is transferred from the transfer gate to the inner horizontal CC.
The phenomenon of backflow to D14-1 disappears, and all charges are directed toward the outer horizontal CCD (for example, 14-2) (
Arrow y=”) transfer becomes possible.

〔Effect of the invention〕

According to the invention, from the transfer gate to the horizontal CCD.

Alternatively, by reducing the gap from the horizontal CCI (horizontal CCI) to the transfer gate to 1 μm or less, the generation of potential that can occur in the horizontal CCDF can be eliminated, tl! This has the effect of reducing the number of items left behind and improving transfer efficiency.

As a result, it is possible to prevent the occurrence of color mixture and fixed pattern noise, and it is possible to significantly improve the image efficiency.

Furthermore, in the portion where the transfer gate is adjacent to the horizontal CCD, the pattern of the transfer gate is sloped as shown in FIG. This makes it easier to apply an electric field in the direction shown), thereby increasing the transfer efficiency of the horizontal CCD itself.

[Brief explanation of the drawing]

FIG. 1 is an enlarged plan view of essential parts of a solid-state imaging device according to an embodiment of the present invention, FIG. 2 is a plan view of the imaging device shown in FIG. 1, and FIG. 3 is a plan view of a conventional solid-state imaging device. FIG. 4 is an enlarged plan view of the main parts of a conventional solid-state image sensor, a corresponding cross-sectional view, and a potential distribution diagram, FIG. 5 is a correlation diagram between transfer efficiency and gap size, and FIGS. FIG. 9 is an enlarged plan view of a main part of a solid-state image sensor according to an embodiment of the present invention, and FIG. 9 is a plan view and a potential distribution diagram showing a solid-state image sensor according to still another embodiment of the present invention. 1... Photoelectric conversion element, 2... Vertical CCD, 3...
Vertical transfer gate, 6-1.6-2 to 6-n,...signal output end, ? -1.7-2.7-3.7-4...Vertical drive pulse generator, 8-1. ．． 8-2...Horizontal drive pulse generator, 5...Horizontal CCD, 4-1.4-2 to 4-
n...Horizontal transfer gate, 11...Region from the transfer gate to the horizontal CCD, 13...Oxide film, 14...Buried channel layer, ■,...Horizontal CC from the transfer gate
Gap size up to D, 15... P-type well layer, 16.
...N-type substrate, Qs...signal charge, QR...remaining potential, Wa, Wb-transfer gate width, 10-1.10
-2 to 10-n...transfer gate region.庬 l Concave 躬 2 Ward g-/g-' 躬 3 Concave 4- Concave 5th figure "O/ 2 3 Opening': r method L (tl wide) 6th article 7I2] (a) Hen 3 figure b shot diagram

Claims (1)

[Claims] 1. A photoelectric conversion element group, an optical signal charge accumulated in the photoelectric conversion element, a vertical CCD shift register group for taking out the optical signal charge, a horizontal CCD shift register group, and the vertical CCD shift register group on the same semiconductor substrate. horizontal CCD
In a charge transfer solid-state image sensor that integrates a group of transfer gates that connect shift registers or between horizontal CCD shift registers, a charge transfer type solid-state image sensor that exists between the transfer gate and the horizontal CCD shift register or between the horizontal CCD and the transfer gate. A charge transfer type solid-state imaging device characterized in that a gap between a channel region (a region serving as a charge transfer path) is 1 μm or less.