JPH01233787A - Circuit device and its manufacture - Google Patents
Circuit device and its manufactureInfo
- Publication number
- JPH01233787A JPH01233787A JP5923788A JP5923788A JPH01233787A JP H01233787 A JPH01233787 A JP H01233787A JP 5923788 A JP5923788 A JP 5923788A JP 5923788 A JP5923788 A JP 5923788A JP H01233787 A JPH01233787 A JP H01233787A
- Authority
- JP
- Japan
- Prior art keywords
- board
- sub
- main board
- hole
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 229910000679 solder Inorganic materials 0.000 claims abstract description 24
- 239000000919 ceramic Substances 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims abstract description 4
- 239000000758 substrate Substances 0.000 claims description 21
- 239000000853 adhesive Substances 0.000 description 6
- 230000001070 adhesive effect Effects 0.000 description 6
- 238000012360 testing method Methods 0.000 description 4
- 238000004806 packaging method and process Methods 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000003908 quality control method Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/36—Assembling printed circuits with other printed circuits
- H05K3/368—Assembling printed circuits with other printed circuits parallel to each other
Abstract
Description
【発明の詳細な説明】 ［産業上の利用分野］ 本発明は回路装置に関するものである。[Detailed description of the invention] [Industrial application field] The present invention relates to a circuit device.
［従来の技術］
従来、へイブリッドＩＣを構成する主基板と副基板の接
続方法は、第６図に示すような電極（２１）を設けた副
基板（２０）と第７図に示す電極（２３）を設けた主基
板（２２）を位置合わせして、半田（２４）により電極
（２１）と電極（２３）を接着していた。しかしこの方
法であると電極（２１） 、 （２３）が外部より視認
出来ないため、位置合せの際、上記両基板の端部な基準
としなければならず、電ａ （２１）、 （２３）のパ
ターンの位置精度に高精度を必要とする。また接続の部
分である半田（２４）。[Prior Art] Conventionally, a method for connecting a main board and a sub-board constituting a hybrid IC is to connect a sub-board (20) provided with an electrode (21) as shown in FIG. 6 and an electrode (20) as shown in FIG. The main substrate (22) provided with the electrodes (23) was aligned, and the electrodes (21) and the electrodes (23) were bonded together with solder (24). However, with this method, the electrodes (21) and (23) cannot be seen from the outside, so when aligning the electrodes (21) and (23), it is necessary to use the ends of the two substrates as a reference. requires high accuracy in positioning the pattern. Also solder (24) which is the connection part.
電極（２１）、 （２３）の外側に露出している部分が
少ないので、検査用のピン等を接触させにくく、そのた
め副基板（２０）及び主基板（２２）にテスト用の端子
を設ける必要がある。そして接続の状態を目視によって
外観検査できない。更に製造上の“問題として、半田量
が適量より多い時、隣接の電極と短絡する危険性がある
。また主基板（２２）又は副基板（２０）をホットプレ
ート等で熱上げするので、該ホットプレート等に接触す
る主基板（２２）又は副基板（２，０）の面には部品を
搭載できない欠点があり、高密度実装化の重大な障害に
なっていた。Since there are few exposed parts of the electrodes (21) and (23) on the outside, it is difficult to make contact with test pins, etc. Therefore, it is necessary to provide test terminals on the sub-board (20) and main board (22). There is. Moreover, the state of the connection cannot be visually inspected. Furthermore, as a manufacturing problem, when the amount of solder is larger than the appropriate amount, there is a risk of shorting with adjacent electrodes.Also, since the main board (22) or the sub-board (20) is heated with a hot plate, etc. There is a drawback that components cannot be mounted on the surface of the main board (22) or the sub-board (2, 0) that comes into contact with a hot plate or the like, which has been a serious obstacle to high-density packaging.
［発明の解決しようとする課題］
本発明の目的は、従来技術が有していた前述の欠点を解
稍しようとするものであり、従来知られていなかった回
路装置を新規に提供することを目的とするものである。[Problems to be Solved by the Invention] The purpose of the present invention is to solve the above-mentioned drawbacks of the prior art, and to provide a new circuit device that was previously unknown. This is the purpose.
［課題を解決するための手段］
（１）構成の表示
本発明は、前述の課題を解決すべくなされたものであり
、主基板とセラミックス多層基板からなる副基板とを主
基板に設けられた電極の面を内側にして積層し、上記副
基板に設けられた穴と上記電極の位置を一致させて、該
穴に注入された半田によって上記主基板に設けられた電
極と上記穴部に設けられた副基板の電極とを接続し、主
基板と副基板の回路網を結線することを特徴とする回路
装置を提供するものである。[Means for Solving the Problems] (1) Display of Structure The present invention has been made to solve the above-mentioned problems. Laminate the electrodes with their surfaces facing inside, match the positions of the holes provided in the sub-board with the electrodes, and use the solder injected into the holes to connect the electrodes provided in the main board with the holes. The present invention provides a circuit device characterized in that the circuit network of the main substrate and the sub-board is connected by connecting the electrodes of the sub-board that are connected to each other.
（２）構成の詳細説明
以下本発明の回路装置について図面に従って詳細に説明
する。(2) Detailed description of configuration The circuit device of the present invention will be described in detail below with reference to the drawings.
第１図は、本発明の基本的構成の断面図であり、（１）
は副基板、（２）は主基板、（３）は半田付は等又は導
電性接着剤（以下半田と総称する） 、 （４）は主基
板（２）上の電極、（５）は副基板（１）上の電極、（
６）は回路網を形成している導体パターン、（７）は副
基板の穴、（８）は電気接続部（接続部）を示している
。（１）はセラミックス多層基板であり、低温焼成多層
基板あるいはアルミナ多層基板等が通常使用される。主
基板（２）はセラミックス基板２含成樹脂基板。FIG. 1 is a sectional view of the basic configuration of the present invention, (1)
is the sub-board, (2) is the main board, (3) is the soldering material or conductive adhesive (hereinafter collectively referred to as solder), (4) is the electrode on the main board (2), and (5) is the sub-board. The electrode on the substrate (1), (
6) shows a conductor pattern forming a circuit network, (7) shows a hole in the sub-board, and (8) shows an electrical connection part (connection part). (1) is a ceramic multilayer substrate, and a low temperature fired multilayer substrate or an alumina multilayer substrate is usually used. The main substrate (2) is a resin substrate containing a ceramic substrate 2.
フィルム基板、ホーロー基板等いずれでもよい。半田等
又は導電性接着剤（３）の導電性接着剤は導電性粒子、
ファイバーを含有したものが通常使用される。電極（４
）の形状は丸型が適当であるが、必ずしも形状は限、定
されない、電極（５）は少なくとも半田（３）が付着可
能な大きさであればよく、副基板上の穴（７）の壁面に
設けられてもよい、そして副基板（１）と主基盤（２）
を、電極（４） と穴（７）が合致するように位置合わ
せな行ない、上方より半田（３）を流し込み、固化させ
ることによって、電！ （４）と電極（５）を接続させ
、主基盤（２）と副基盤（１）の回路網を結線させる。Either a film substrate, a hollow substrate, etc. may be used. The conductive adhesive of solder or conductive adhesive (3) contains conductive particles,
Those containing fibers are usually used. Electrode (4
) is suitably round, but the shape is not necessarily limited.The electrode (5) should be at least large enough to allow the solder (3) to adhere to it, and the shape of the electrode (5) should be round (7) on the sub-board. It may be provided on the wall surface, and the sub-board (1) and the main board (2)
Align the electrodes (4) and holes (7) so that they match, then pour the solder (3) from above and allow it to solidify, then the electric! (4) and the electrode (5) to connect the circuit networks of the main board (2) and the sub-board (1).
第２図に本発明の一実施例にかかる回路装置の斜視図を
示す、第２図において（９）は表面実装型モールドＩＣ
等の電子部品を示す。該実施例においては、主基盤（２
）の中央部付近に副基盤（１）が実装されている。FIG. 2 shows a perspective view of a circuit device according to an embodiment of the present invention. In FIG. 2, (9) is a surface-mounted molded IC.
Indicates electronic components such as. In this embodiment, the main substrate (2
) A sub-board (1) is mounted near the center of the board.
第３図は第２図において使用された副基盤（１）の平面
図であり、該副基盤（１）上にベアーチップＩ Ｃ（１
０）やその他の電子部品が搭載される。第３図において
、穴（１１）は穴（７） と同一のものであるが、電子
部品等の下に隠れている。FIG. 3 is a plan view of the sub-board (1) used in FIG. 2, and a bare chip IC (1
0) and other electronic components are installed. In FIG. 3, hole (11) is the same as hole (7), but is hidden under electronic components, etc.
このように穴（７）は通常は表面に現われているが、穴
（１１）のように表面□実装型モールドＩＣ等の電子部
品の下にあってもよい、第３図において副基盤（１）に
は主にベアーチップＩＣや印刷抵抗等のモールドするこ
とが必要な電子部品を搭載し、主基盤（２）では主にモ
ールドすることが不要なモールドされたＩＣやトランジ
スタ等の電子部品を搭載して、原則として副基盤（１）
の接続部を除いた部分全体にモールドを施す。In this way, the hole (7) usually appears on the surface, but like the hole (11), it may also be under the surface □ electronic component such as a molded IC. ) is mainly equipped with electronic parts that need to be molded, such as bare chip ICs and printed resistors, and the main board (2) is mainly equipped with electronic parts such as molded ICs and transistors that do not need to be molded. Equipped with, in principle, a sub-base (1)
Apply mold to the entire part except the connecting part.
このようにする□ことによって製造工程数の削減や、品
質管理の手間を少なくすることができる。By doing this □, it is possible to reduce the number of manufacturing steps and the effort required for quality control.
第４図は副基盤（１） と主基盤（２）の形状を一致さ
せた本発明の一実施例にかかる回路装置を示し、第５図
は第４図の側面図である。第４図において、（１４）は
リード端子、（１５）は上部主基板、（１６）は下部主
基板である。該実施例では上部主基板（１５）と下部主
基板（１６）の接続は、リード端子（１４）において行
ない、上部主基板（１５）。FIG. 4 shows a circuit device according to an embodiment of the present invention in which the sub-board (1) and the main board (2) have the same shape, and FIG. 5 is a side view of FIG. 4. In FIG. 4, (14) is a lead terminal, (15) is an upper main board, and (16) is a lower main board. In this embodiment, the upper main board (15) and the lower main board (16) are connected through lead terminals (14).
下部主基板（１６）と副基板（２）間の接続は接続部（
８）によって行なっている。The connection between the lower main board (16) and the sub board (2) is at the connection part (
8).
これより本発明の回路装置の製造工程のいくつかの具体
例を第１図を使用して述べる。主基板（２）と副基板（
１）の位置合わせなした後、穴（７）上より溶解した半
田等を流してもよいが、このようにする前にあらかじめ
、電ａ （４）、 （５）のそれぞれに溶解した半田等
を付着させた後、上記の如く行なうと接続が確実である
。この場合、主基板（２）と副基板（１）を密着させる
ためには、電極（４）の径は穴（７）の径より小さくし
たほうが望ましい、主基板（２）と副基板（１）の間隔
をあける時は、電極（４）の径は穴（７）の径より大き
いほうが接続の信頼性は高い。Hereinafter, some specific examples of the manufacturing process of the circuit device of the present invention will be described using FIG. Main board (2) and sub board (
After alignment in step 1), melted solder, etc. may be poured from above the hole (7), but before doing so, pour the melted solder, etc. into each of electrodes (4) and (5) in advance. After attaching it, follow the steps above to ensure a secure connection. In this case, in order to bring the main substrate (2) and the sub-board (1) into close contact, it is desirable that the diameter of the electrode (4) be smaller than the diameter of the hole (7). ), the reliability of the connection is higher if the diameter of the electrode (4) is larger than the diameter of the hole (7).
また第１図において、主基板（２）に穴（７）のほぼ中
心に、穴（７）より小さい径の孔（不図示）をあけ、穴
（７）に導電性接着剤等をデイスペンサニ又はスクリー
ン印刷等によって注入しながら主基板（２）の下から、
上記孔を通して吸引する。このような方法で、上記導電
性接着剤が注入され、その後固化させると信頼性の高い
接続が得られる。このように主基板に上記吸引用の穴を
設けることは半田等に対しても有効である。更に半田（
３）として特公昭４５−２１５８０号公報に示されてい
るセラミックス用゛半田を超音波振動を与えながら、穴
（７）に流すと上記セラミックス用半田は電極（４）
、 （５）及び穴（７）の壁面にも付着して、接着強度
のある信頼性の高い接続が可能となる。In addition, in Fig. 1, a hole (not shown) with a smaller diameter than the hole (7) is made in the main board (2) almost at the center of the hole (7), and a conductive adhesive or the like is applied to the hole (7) with a dispenser or From below the main board (2) while injecting by screen printing etc.
Aspirate through the hole. In this way, the conductive adhesive is injected and then allowed to solidify, resulting in a reliable connection. Providing the suction hole in the main board in this way is also effective for solder and the like. Furthermore, solder (
3) When the solder for ceramics shown in Japanese Patent Publication No. 45-21580 is poured into the hole (7) while applying ultrasonic vibration, the solder for ceramics will form an electrode (4).
, (5) and the wall of the hole (7), allowing for a highly reliable connection with adhesive strength.
［作用・効果］
本発明の回路装置は、副基板に設けられた穴から主基板
上の電極を視認することができ、主基板と副基板の位置
合せが容易にできる。また上記穴上に半田が露出してい
るため、検査用のピン等を接触させやすく、主基板及び
副基板にテスト用の端子を設ける必要がない。更に上記
穴の上より接続の状態を視認することができる。また上
記穴の中に注入する半田等の量が適切な量よりも多少多
かったとしても、上記穴の上に余分な量が突出するだけ
で、該半田等の余分な量が主基板と副基板の間に広がり
、隣接した電極と短絡するようなことはない、そして上
記半田を使用する場合でも主基板、副基板全体を熱上げ
する必要がないので、該両基板の相対向している以外の
面に部品を搭載することができるため、高密度実装化に
寄与するところが大きい。[Operations and Effects] In the circuit device of the present invention, the electrodes on the main board can be visually recognized through the holes provided in the sub-board, and the main board and the sub-board can be easily aligned. Further, since the solder is exposed on the hole, it is easy to contact pins for testing, and there is no need to provide terminals for testing on the main board and the sub board. Furthermore, the state of the connection can be visually checked from above the hole. Furthermore, even if the amount of solder, etc. injected into the hole is slightly larger than the appropriate amount, the extra amount will just protrude above the hole, and the extra amount of solder, etc. will be connected to the main board and the secondary board. It does not spread between the substrates and short-circuit with adjacent electrodes, and even when using the above solder, there is no need to heat up the entire main and sub-boards, so the two substrates are facing each other. Since components can be mounted on other surfaces, it greatly contributes to high-density packaging.
第１図工本発明の回路装置の基本的構成を示す断面図
第２図工本発明の実施例にかかる回路装置の斜視図
第３図：第２図に示す回路装置に使用された副基板の平
面図
第４図：本発明の実施例にかかる主基板と副基板の形状
が一致した回路装置の斜視図
第５図：第４図の回路装置の側面図
第６図：従来のへイブリッドＩＣの副基板の斜視図
第７図：従来のへウブリッドＩＣの主基板と副基板を接
着した部分の側面図
１：副基板
２：主基板
３：半田
４．５：電極
７：穴
第１図
乃
第 ？ ）刀
第 ５ 図Fig. 1: A sectional view showing the basic structure of the circuit device of the present invention Fig. 2: A perspective view of the circuit device according to the embodiment of the present invention Fig. 3: Plane of the sub-board used in the circuit device shown in Fig. 2 Figure 4: A perspective view of a circuit device in which the main board and sub-board have the same shape according to an embodiment of the present invention. Figure 5: A side view of the circuit device shown in Figure 4. Figure 6: A conventional hybrid IC. Perspective view of sub-board Figure 7: Side view of the part where the main board and sub-board of a conventional hebride IC are bonded 1: Sub-board 2: Main board 3: Solder 4.5: Electrode 7: Hole Fig. 1 No. ? ) Sword Figure 5
Claims (4)
を主基板に設けられた電極の面を内側にして積層し、上
記副基板に設けられた穴と上記電極の位置を一致させて
、該穴に注入された半田によって上記主基板に設けられ
た電極と上記穴部に設けられた副基板の電極とを接続し
、主基板と副基板の回路網を結線することを特徴とする
回路装置。(1) Laminate the main substrate and a sub-substrate made of a ceramic multilayer substrate with the electrodes provided on the main substrate facing inside, align the holes provided in the sub-substrate with the positions of the electrodes, and A circuit device characterized in that the electrode provided on the main board and the electrode of the sub board provided in the hole are connected by solder injected into the hole, thereby connecting the circuit network of the main board and the sub board. .
を特徴とする第１項記載の回路装置。(2) The circuit device according to item 1, wherein the main board and the sub-board have the same shape.
とを特徴とする第１項又は第２項記載の回路装置。(3) The circuit device according to item 1 or 2, characterized in that a suction hole is provided at the position of the electrode of the main board.
、上記穴に該セラミックス用半田を注入する際、超音波
振動を与えることを特徴とする第１項又は第２項又は第
３項記載の回路装置の製造方法。(4) The method according to item 1, item 2, or item 3, wherein a ceramic solder is used instead of the solder, and ultrasonic vibration is applied when the ceramic solder is injected into the hole. A method of manufacturing a circuit device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5923788A JPH01233787A (en) | 1988-03-15 | 1988-03-15 | Circuit device and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5923788A JPH01233787A (en) | 1988-03-15 | 1988-03-15 | Circuit device and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01233787A true JPH01233787A (en) | 1989-09-19 |
Family
ID=13107574
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5923788A Pending JPH01233787A (en) | 1988-03-15 | 1988-03-15 | Circuit device and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01233787A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02140874U (en) * | 1989-04-28 | 1990-11-26 |
-
1988
- 1988-03-15 JP JP5923788A patent/JPH01233787A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02140874U (en) * | 1989-04-28 | 1990-11-26 |
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