JPH01233749A - Formation of active layer laminated device - Google Patents
Formation of active layer laminated deviceInfo
- Publication number
- JPH01233749A JPH01233749A JP63060901A JP6090188A JPH01233749A JP H01233749 A JPH01233749 A JP H01233749A JP 63060901 A JP63060901 A JP 63060901A JP 6090188 A JP6090188 A JP 6090188A JP H01233749 A JPH01233749 A JP H01233749A
- Authority
- JP
- Japan
- Prior art keywords
- pad
- active layer
- semiconductor element
- test use
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015572 biosynthetic process Effects 0.000 title abstract description 7
- 239000004065 semiconductor Substances 0.000 claims abstract description 40
- 238000012360 testing method Methods 0.000 claims abstract description 19
- 238000000034 method Methods 0.000 claims abstract description 9
- 238000005259 measurement Methods 0.000 claims abstract description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 10
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 10
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 35
- 239000010408 film Substances 0.000 description 22
- 239000000758 substrate Substances 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 239000010409 thin film Substances 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 210000004709 eyebrow Anatomy 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
Landscapes
- Tests Of Electronic Circuits (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体素子を含む能動層を積層化して形成する
能動層積層デバイスの形成方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for forming an active layer stacked device in which active layers including semiconductor elements are stacked.
従来、半導体素子を含む能動層を積層化して、能動層積
層デバイスを作成する際には次の方法が用いられている
。以下第2図の断面図を用いて説明する。Conventionally, the following method has been used to create an active layer stacked device by stacking active layers including semiconductor elements. This will be explained below using the cross-sectional view of FIG.
まず、シリコン基板1とフィールド酸化膜2と、それぞ
れ多結晶シリコン膜からなるゲート電極3Aと層内配置
14Aと眉間配線6A等により、能動層第1層目のデバ
イスを形成する。さらに眉間絶縁膜としてのシリコン酸
化膜5Aを形成した後、エッチバック法等によりシリコ
ン酸化膜5Aの表面を平坦化する。次に、アイランド状
のシリコン膜8とゲート電極3Bと層内配線4Bと眉間
配線6B等により、能動層第2層目のデバイスを形成す
る4層間絶縁膜としてのシリコン酸化膜5Bは、能動層
第1層目の場合と同様に、エッチバック法等によりその
表面を平坦化する。能動層第3層目以降は、能動層第2
層目と同様の方法で形成する。最後に、シリコン酸化膜
5C上に、配線および、測定装置端子用のパッド7をア
ルミにより形成する。First, a device in the first layer of the active layer is formed by the silicon substrate 1, the field oxide film 2, the gate electrode 3A each made of a polycrystalline silicon film, the intralayer arrangement 14A, the glabella wiring 6A, and the like. Furthermore, after forming a silicon oxide film 5A as a glabellar insulating film, the surface of the silicon oxide film 5A is planarized by an etch-back method or the like. Next, the silicon oxide film 5B as a four-layer insulating film that forms a device in the second layer of the active layer is formed by the island-shaped silicon film 8, the gate electrode 3B, the intralayer wiring 4B, the glabella wiring 6B, etc. As in the case of the first layer, the surface is planarized by an etch-back method or the like. After the third active layer, the second active layer
It is formed in the same way as the layer. Finally, wiring and pads 7 for measuring device terminals are formed of aluminum on the silicon oxide film 5C.
上述の方法により能動層積層デバイスは作成される。こ
の様な技術は、例えば、第4回新機能素子技術シンポジ
ウム予稿集、第251頁に記載されている、三橋克典の
論文等で紹介されている。An active layer stack device is fabricated by the method described above. Such technology is introduced, for example, in the paper by Katsunori Mitsuhashi, etc., listed on page 251 of the Proceedings of the 4th New Functional Device Technology Symposium.
上述した従来の能動層積層デバイスの形成方法において
は、測定装置の測定端子用のパッドは、能動層積層デバ
イス試作の最終工程であるアルミ配線形成時にのみ作成
される。このため、各能動層内の半導体素子の動作確認
も試作の最終工程以降にしか行なえなかった。In the above-described conventional method for forming an active layer stacked device, pads for measurement terminals of a measuring device are created only during aluminum wiring formation, which is the final step of prototyping an active layer stacked device. For this reason, the operation of the semiconductor elements in each active layer could only be confirmed after the final step of prototyping.
このため、いずれかの能動層内の半導体素子の素子特性
が悪かったり、或いは動作しなかった場合でも、それ以
降の能動層形成にフィードバックをかけることが出来ず
、デバイス試作は続行される。その結果、試作された能
動層積層デバイスの素子特性が悪かったり、デバイス形
成の歩留りが低下したりする欠点がある。Therefore, even if a semiconductor element in any active layer has poor device characteristics or fails to operate, no feedback can be applied to subsequent active layer formation, and device prototype fabrication continues. As a result, there are drawbacks such as poor device characteristics of the prototype active layer stacked device and a decrease in the yield of device formation.
本発明の能動層積層デバイスの形成方法は、半導体素子
を含む能動層を積層化する際に、半導体素子の特性を測
定するための測定装置の測定端子を接触させるためのパ
ッドを有するテスト用半導体素子を各能動層内に形成す
るものである。The method for forming an active layer stacked device of the present invention includes a test semiconductor having a pad for contacting a measurement terminal of a measuring device for measuring the characteristics of the semiconductor element when stacking active layers including a semiconductor element. A device is formed within each active layer.
以下、本発明について図面を用いて説明する。 Hereinafter, the present invention will be explained using the drawings.
第1図は本発明の一実施例を説明するためのテスト用半
導体素子の斜視図である0本実施例においては、半導体
薄膜として多結晶シリコン薄膜、眉間絶縁膜としてシリ
コン酸化膜、半導体基板としてシリコン基板、テスト用
半導体素子としてMOSFETを用いている。テスト用
半導体素子の作成は、試作デバイス作成と同時に行なう
。FIG. 1 is a perspective view of a test semiconductor device for explaining an embodiment of the present invention. In this embodiment, a polycrystalline silicon thin film is used as a semiconductor thin film, a silicon oxide film is used as an insulating film between the eyebrows, and a semiconductor substrate is used as a semiconductor substrate. A silicon substrate and a MOSFET are used as test semiconductor elements. The test semiconductor device is created at the same time as the prototype device is created.
まず、シリコン基板1に選択酸化を行ない、フィールド
酸化膜2を形成し、素子分離を行なう。First, selective oxidation is performed on a silicon substrate 1 to form a field oxide film 2 and perform element isolation.
次に多結晶シリコンからなるゲート電極3を形成し、そ
の後不純物のイオン注入等によりソース・ドレイン領域
を形成する。次に層内配線4を多結晶シリコン膜により
形成した後、眉間配線とパッド7Aを多結晶シリコン膜
により形成する。この時、パッド7Aには、テスト用半
導体素子の特性を測定するための測定装置の測定端子が
楽に接触できる様に十分広い面積をもたせる。その後、
CVD法等によりシリコン酸化膜5の表面を平坦化する
。この平坦化時に、パッド7Aの表面が露出する様に、
シリコン酸化膜5の膜厚を調整する0以上の工程により
、能動層第1層目にパッド7Aを有するテスト用半導体
素子が形成される。Next, a gate electrode 3 made of polycrystalline silicon is formed, and then source/drain regions are formed by ion implantation of impurities or the like. Next, after the intralayer wiring 4 is formed of a polycrystalline silicon film, the glabella wiring and the pad 7A are formed of a polycrystalline silicon film. At this time, the pad 7A is made to have a sufficiently large area so that a measuring terminal of a measuring device for measuring the characteristics of the test semiconductor element can easily come into contact with the pad 7A. after that,
The surface of silicon oxide film 5 is planarized by CVD method or the like. During this flattening, the surface of the pad 7A is exposed.
Through zero or more steps of adjusting the thickness of the silicon oxide film 5, a test semiconductor element having the pad 7A in the first active layer is formed.
このテスト用半導体素子゛のパッド7Aには、測定装置
の測定端子を楽に接触することが出来るので、能動層形
成直後にテスト用半導体素子の動作特性を容易に確認す
ることができる。Since the pad 7A of the test semiconductor device can be easily contacted with the measurement terminal of the measurement device, the operating characteristics of the test semiconductor device can be easily checked immediately after the active layer is formed.
能動層2層目以降にも同様にパッドを有するテスト用半
導体素子を各能動層ごとに形成する。その結果、各能動
層形成直後に半導体素子の動作を確認しながら、能動層
を積層化しデバイスを作成できる。Test semiconductor elements having pads are similarly formed for each active layer in the second and subsequent active layers. As a result, devices can be fabricated by laminating active layers while checking the operation of the semiconductor element immediately after forming each active layer.
以上の実施例においては、半導体薄膜として、多結晶シ
リコン薄膜、層間絶縁膜としてシリコン酸化膜、半導体
基板としてシリコン基板、テスト用半導体素子としてM
OSFETを用いたが、他の半導体薄膜、他の眉間絶縁
膜、他の半導体基板、他のテスト用半導体素子にも適用
できる。またパッドの材料としては後工程で他の半導体
素子に影響を与えない半導体材料や高融点金属が望まし
い。In the above embodiments, the semiconductor thin film is a polycrystalline silicon thin film, the interlayer insulating film is a silicon oxide film, the semiconductor substrate is a silicon substrate, and the test semiconductor element is an M
Although OSFET is used, it can also be applied to other semiconductor thin films, other glabella insulating films, other semiconductor substrates, and other semiconductor devices for testing. Further, as the material for the pad, it is desirable to use a semiconductor material or a high melting point metal that does not affect other semiconductor elements in subsequent steps.
以上説明した様に本発明は、各能動層ごとに測定用のパ
ッドを有するテスト用半導体素子を設けることにより、
能動層積層デバイス試作工程の各能動層形成直後ごとに
、その能動層に含まれる半導体素子の特性および動作を
確認することができ、その結果を以後の試作にフィード
バックできるので、能動層積層デバイスの素子特性やデ
バイス形成の歩留りを向上させることができる。As explained above, the present invention provides a test semiconductor element having a measurement pad for each active layer.
Immediately after forming each active layer in the active layer stacked device prototyping process, it is possible to check the characteristics and operation of the semiconductor element included in that active layer, and the results can be fed back to subsequent prototypes. Element characteristics and yield of device formation can be improved.
第1図は本発明の一実施例を説明するためのテスト用半
導体素子の斜視図、第2図は従来の能動層積層デバイス
の断面図である。
1・・・シリコン基板、2・・・フィールド酸化膜、3
.3A、3B、3C・・・ゲート電極、4.4A。
4B、4C・・・層内配線、5.5A、5B、5C・・
・シリコン酸化膜、6A、6B、6C・・・層間配線、
7.7A・・・パッド、8・・・アイランド状シリコン
膜。FIG. 1 is a perspective view of a test semiconductor device for explaining an embodiment of the present invention, and FIG. 2 is a sectional view of a conventional active layer stacked device. 1... Silicon substrate, 2... Field oxide film, 3
.. 3A, 3B, 3C...gate electrode, 4.4A. 4B, 4C... In-layer wiring, 5.5A, 5B, 5C...
・Silicon oxide film, 6A, 6B, 6C...interlayer wiring,
7.7A...pad, 8...island silicon film.
Claims (1)
子の特性を測定するための測定装置の測定端子を接触さ
せるためのパッドを有するテスト用半導体素子を各能動
層内に形成することを特徴とする能動層積層デバイスの
形成方法。When stacking active layers containing semiconductor elements, a semiconductor element for testing is formed in each active layer, the semiconductor element having a pad for contacting a measurement terminal of a measurement device for measuring the characteristics of the semiconductor element. A method for forming an active layer stacked device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63060901A JPH01233749A (en) | 1988-03-14 | 1988-03-14 | Formation of active layer laminated device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63060901A JPH01233749A (en) | 1988-03-14 | 1988-03-14 | Formation of active layer laminated device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01233749A true JPH01233749A (en) | 1989-09-19 |
Family
ID=13155723
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63060901A Pending JPH01233749A (en) | 1988-03-14 | 1988-03-14 | Formation of active layer laminated device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01233749A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5684304A (en) * | 1993-12-27 | 1997-11-04 | Sgs-Thomsn Microelectronics S.A. | Structure for testing integrated circuits |
JP2005094023A (en) * | 2004-10-01 | 2005-04-07 | Renesas Technology Corp | Semiconductor device |
-
1988
- 1988-03-14 JP JP63060901A patent/JPH01233749A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5684304A (en) * | 1993-12-27 | 1997-11-04 | Sgs-Thomsn Microelectronics S.A. | Structure for testing integrated circuits |
JP2005094023A (en) * | 2004-10-01 | 2005-04-07 | Renesas Technology Corp | Semiconductor device |
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