JPH01233537A - Information processor provided with cache memory - Google Patents

Abstract

PURPOSE:To enlarge the degree of freedom of a utilization type of a cache memory and to improve the execution efficiency and the execution speed of a program by changing the constituting system and the capacity of the cache memory in accordance with the program to be executed. CONSTITUTION:In case of two ways, command information X, Y becomes '0' and '1', a control signal B becomes active, and an address of 9 bits of address information 7 is decoded by a decoder 5. By a decoded output, one entry is selected from cache memories 1a, 1b or cache memories 1c, 1d, given to the respective selectors 17a, 17c or 17b, 17d, and by selecting information of 2-3 bits of the address information 7, one set of data is selected against the respective selectors 17a, 17c. Subsequently, by a coincidence signal from comparators 15a-15c, one set of data is selected by a selector 23 and outputted through a selector 25.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention 1 (Field of Industrial Application) The present invention relates to an information processing device equipped with a cache memory, and particularly relates to an information processing device equipped with a cache memory whose usage mode can be changed.

(Prior Art) In one computer system, a high-speed cache memory is sometimes placed between the CPU cycle time and the main memory access time in order to bridge the difference between the two. Cache memory is located at an intermediate level between the CPU and main memory, and is invisible to programs.

This kind of cache memory was first used in general-purpose large computers, but now it is also beginning to be used in microcomputers.

In modern microprocessors, the processor is formed and the cache memory is formed on the chip of Shuichi.
Some are on-chip.

The configuration method of such an on-chip cache memory is described, for example, in the document "Processor MC68
020 (manufactured by Motorola) User's Manual, Chapter 7, P2J, [Clipper Seminar Text (
There are various types, as described in Fairchild Inc.), P45J, etc. For example, even if the memory is configured using the set associative (S6tA5sociative) method, there are some that have different sizes and numbers of divided units (lines) to be associated with the main memory.

Furthermore, an on-chip cache memory is used exclusively for data or instructions, and a processor is equipped with one or both of a data cache and an instruction cache.

Such an on-chip cache memory is configured such that a user can select whether or not to use it. That is, as shown in the following document, an on-chip cache memory is selected by an external signal applied from outside the chip or a signal applied from an internal register.

(Reference “Processor MC68020 (manufactured by Motorola)
User's Manual 5, Chapter 7, P1-P4'', r
7Dt Sensor Z80.000CD Technical Manual, Chapter 2, P4J, [Semiconductor Technical Data for Processor MC68030 (manufactured by Motorola Corporation, P8)].

On the other hand, the configuration method and number of cache memories depends on the program being executed. That is, the effect does not necessarily increase as the capacity increases, and there are optimum capacities depending on each program to be executed. For example, even if there is only a small amount of data 0 to be handled, if the scale of the program is large, it is desirable to have a larger capacity for the instruction cache than for the data cache.

(Problems to be Solved by the Invention) However, in the conventional on-chip cache memory, its configuration method and capacity for the type of information stored are predetermined depending on the processor. For this reason, it has not been possible to optimally change the configuration method and capacity depending on the program.

However, it has been difficult to fully utilize the effects of using the cache memory, and it has been difficult to fully utilize the capabilities of the processor.

This has caused a problem in that the program execution efficiency and execution speed are not maximized.

Therefore, the present invention has been made in view of the above, and its purpose is to create a cache memory that is formed on the same chip by changing the configuration method and capacity of the cache memory according to a program. An object of the present invention is to provide an information processing device equipped with a cache memory that fully utilizes the capabilities of the information processing device and improves program execution efficiency and execution speed.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the first invention provides a cache memory consisting of a plurality of blocks, and supplying an address to a predetermined block of the cache memory. an address supplying means; a changing means for changing the configuration of addresses supplied from the address supplying means and blocks to which the addresses are supplied according to command information for instructing a configuration change of the cache memory; selection means for selecting predetermined information to be read from a plurality of pieces of information output from a predetermined block of the cache memory according to an address of the cache memory; and a plurality of pieces of information output from a predetermined plot of the cache memory. and control means for instructing the selection means to select information according to tag information added to the tag information and address information given from the outside.

Further, the second invention provides a cache memory consisting of a plurality of blocks, and the type of information to be stored and the attributes of the cache memory being changeably specified and defined for each cache memory consisting of the plurality of blocks. It consists of a specification definition means.

<Operations> In one of the above configurations, the first invention appropriately changes the configuration method and capacity of the cache memory composed of the plurality of blocks by changing the structure of the addresses given to the plurality of blocks and the blocks to which the addresses are given. I try to do that.

Further, in the other configuration, the second invention specifies and defines the type of information to be stored and the attributes of the cache memory for each block of the cache memory consisting of a plurality of blocks, The capacity is made variable for the information stored.

(Example) The present invention will be described in detail below using the drawings.

FIG. 1 is a diagram showing the main part configuration of a processor equipped with a cache memory according to a first embodiment of the present invention. The processor shown in the figure is equipped with a cache memory having a total of 16 bytes and configured as an associative system with a 4-way Φ set. This first embodiment uses the cache memory configured in this way as a two-way set.
This figure shows the configuration when used as an associative method.

In Figure 1, the cache memory of 16 bytes is
It consists of four similarly configured cache memories 1a to 1d of 4 to 4 bytes.

Each cache memory 1a-1d is composed of 256 entries (E1-E2se). Each entry has a tag (T) consisting of a 20-pit address.
AG) section and 4-byte lines each (L+ to L4)
It consists of a 16-byte line size data section consisting of:

The configuration and capacity of the 16-byte cache memory ' thus configured are changed in accordance with control signals A to D output from the decoder (DEC) 3.

The decoder 3 decodes and decodes 2-bit command information (X, Y) that commands the number of ways and capacity of the cache, and provides one of the control signals A to D. That is,
The decoder 3 activates any one of the control signals @A to D as shown in FIG. 2 in response to the given command information, and determines the configuration and capacity of the cache. This first
・In the embodiment, the cache memory is 4-way,
Since the byte is changed from 16 to 2-way 16 byte, the command information changes from (1, 1) to (0, 1), and the active control signal changes to I control signal eight hera control signal B. . These control signals are given to decoder 5.

When the cache memory is used as a 4-way cache memory, the decoder 5 decodes 8 bits from the 4th bit to the 11th bit of the 32-bit address information 7 according to the v4tIl signal 8, and decodes each cache memory. Select one of the 256 entries. On the other hand, when the cache memory is used as a 2-way, the decoder 5 decodes the 9th bit from the 4th bit to the 12th bit of the address 7 in accordance with the III tll signal, and stores it in the cache memories 1a and 1b. Select one entry from cache memories 1c and 1d.
Select one entry. - Therefore, in the case of 4-way, the decoder 5 outputs 256 decoded outputs A to the cache memories 1a, 1c and the selector 9.
The data is given to the cache memories 1b and 1d' via the memory. On the other hand, in the case of 2-way, 512 decode outputs (A, B
), the decoded output A is sent to the cache memory 1a, 1
c, the decode output B is sent to the cache memory 1t), Id
give to

The address of the tag part of the entries in each of the cache memories 1a to 1d selected by the decoder 5 is as follows:
Selectors 11a to 11d (selector 11C) provided corresponding to each cache memory 1a to 1d
, lid are not shown).

The selector 11a selects the 19-bit address of the tag part selected and given from the cache memory 1a11b or the 20-bit address of the tag part selected and given from the cache memory 1a.

That is, in the case of 4-way, selector 11a selects the 20-bit address provided from cache memory 1a, and in the case of 2-way, selector 11a selects the 20-bit address given from cache memory 1a.
Select the 19-bit address given from a and ib.

The selector 11b selects a 20-bit address given from the cache memory 16 in the case of 4-way in response to the control signal A. The selector 11C111d functions similarly to the selectors 11a and 11b for the corresponding cache memories 1c and Id, respectively.

Further, selectors 138 to 13d (13b to 13d are not shown) are provided corresponding to the respective selectors 11a to 11d. In the case of 4-way, the selectors 13a to 13d select the 20-bit address from the 12th to 31st bits of the 32-bit address information 7 in accordance with the control signal A. On the other hand, in the case of 2-way, 13 to 31 of address information 7 according to control signal B.
Select the 19th bit address.

Respective selectors 11a to 11d and 13a to 13
The respective addresses selected by
Comparators (CM
P) 15a to 15d (15b to 15d are not shown), respectively.

Comparator 15a compares the addresses selected by selector 11a and selector 13a, and outputs a match signal if there is a matching address. That is, the comparator 15a detects whether the entry output from the cache memory 1a is data to be read.

Even if there are comparators 1b to 1d, they function in the same way as comparator 1a.

On the other hand, the entries output from the cache memories 18 to 1d have their 16-byte data portions set to the selectors 178 to 1d.
17d.

In the case of 4-way, the selector 17a selects 2 to 3 of the 32-bit address information 7 because it is among the four data (1 to 4) output from the cache memory 1a.
One piece of data of 4 bytes is selected based on the selection information of the 2nd bit of the bit.

On the other hand, in the case of 2-way, one 4-byte data is selected from among the four data in the cache memory 1a or the cache memory 1b selected by the selector 19b according to the 2-bit selection information.

In the case of 4-way, the selector 17b is the selector 19b.
One piece of 4-byte data is selected from among the four pieces of data in the cache memory 1b selected by , according to the 2-bit selection information.

Selectors 17c and 17d select selector 11a for corresponding cache memories 1c and 1d, respectively.
, 11b.

The respective data selected by the respective selectors 17a to 17d are provided to the selector 21, and the data selected by the selectors 17a and 17C are further provided to the selector 23.

The selector 21 receives the data selected by the respective selectors 17a-17d, and selects one data from among them according to the match signal output from the comparators 15a-15d.

That is, in the case of 4-way, the selector 21 selects data in the cache memories 1a-1d corresponding to the match signals of the comparators 15a-15d.

The selector 23 receives the data selected by the selector 17a117c and selects one data from among them according to the match signal output from the comparators 15a and 15c. That is, in the case of 2-way, the selector 23 selects data in the cache memories 18 to 1d corresponding to the match signals from the comparators 15a and i5c. The data selected by each selector 21, 23 is given to the selector 25.

In the case of 4-way, the selector 25 selects the output of the selector 21 according to the control signal, and in the case of 2-way,
The output of the selector 23 is selected by the control signal B.

Next, the operation of this first embodiment will be explained.

First, a case where the cache memories 18 to 1d are used as a 4-way system will be described.

In the case of 4-way, command information (X, Y) is (1, 1)
Therefore, control signal A becomes active. As a result, the 8-bit address of the 4th to 11th bits of the address information 7 is decoded by the decoder 5, and one entry is selected from each of the cache memories 1a to 1d by the decoded output.

The 20-bit address of the tag part of the selected entry is given to the corresponding comparators 158-15d via the corresponding selectors 118-11d, respectively. Each address given to the comparators 158-15d is compared with the 20-bit address of the 12th to 31st bits of the address information 7, and if there is a matching address, the matching signal is sent to the corresponding comparators 158-15d. It is output from 15d.

On the other hand, among the selected entries, four data (Ll"L4) of 16 bytes in the data section are given to the corresponding selectors 17a to 17d.The four data given to the respective selectors 1 and 78 to 17d One piece of data is selected according to the selection information of the second and third bits of the address information 7.

The four data of 4 bytes each selected by the respective selectors 17a to 17d are sent to the comparators 15a to 1.
Selector 2 according to the match signal output from 5d.
1 selects one piece of data. For example, when data to be read exists in the cache memory 1a, the data output from the selector 17a is passed to the selector 21 by the match signal output from the comparator 15a.
selected. The 4-byte data selected by selector 21 is read out via selector 25.

Next, a case will be described in which the configuration method is changed from 4-way to 2-way without changing the total cache capacity.

In the case of 2-way, the command information (X, Y) is (0, 1)
Therefore, control signal B becomes active. As a result, the 9-bit address of the 4th to 12th bits of the address information 7 is decoded by the decoder 5, and one entry is selected from the cache memory 1a11b by the decoded output, and one entry is selected from the cache memories ic and ld. be done.

The 19-bit address of the tag part of the entries selected from the cache memories 1a and 1b is ', and the selector 11
a to the comparator 15a. On the other hand, the 19-bit address of the tag part of the entries selected from the cache memories 1c and 1d is given to the comparator 15C via the selector 11C.

Each address given to the comparator 15a115C is compared with the 19th address of the 13th to 31st bits of the address information 9117, and if there is a matching address, a matching signal is sent to the corresponding comparator 15a or comparator 15c. is output from.

On the other hand, the selected entry is cache memory 1a, i
In case c, the four pieces of data in the data portion of the entry are directly given to the corresponding selectors 17a and 17C. Also, the selected entry is ``cache memory 1b11d''.
In this case, the four sets of data in the data section of the entry are provided to the corresponding selectors 17b and 17d via the corresponding selectors 19b and 119d (not shown).

Of the four sets of data given to the respective selectors 17a and 170, one set of data is selected for each selector 17a117c based on the selection information of the second and third pits of the address information 7. One set of the selected two sets of 4-byte data is selected by the selector 23 in accordance with the match signal output from the comparator 15a1150. The selected 4 bytes of data are read out via the selector 25.

In this way, by using the cache memories 1a, 1b and the cache memories 1c, 1d as one set of ways, a two-way configuration system is realized without changing the storage space. Therefore, in the configuration shown in FIG.
) from (1, 1) to (1, O), the configuration method can be changed from 4-way to 2-way.

This expands the degree of freedom in how the cache memory is used, and makes it possible to create an optimal configuration for the program. Therefore, the capabilities of the processor are fully utilized and programs can be executed efficiently.

FIG. 3 is a diagram showing the main part configuration of a processor equipped with a cache memory according to a second embodiment of the present invention. Note that in FIG. 3, components having the same reference numerals as those in FIG. 1 have the same functions, and their explanations will be omitted.

In this second embodiment, by changing the command information from (1, 1) to (0, O), the cache memory that was used for 4 ways and 16 bytes can be used for 2 ways and 8 bytes. This shows cases in which changes are made. In this case, the cache memories 1c, ld and selector 17c117d become unnecessary.

The feature of this second embodiment is that when used in two-way, the decoding result of the decoder 5 is supplied to the cache memories 1C and 1d according to a signal obtained by inverting the control signal C by an inverter 31. It is stopped by the address buffer 33 controlled, and the inverter 31
The reason is that the operation of the selectors 17c and 17d is stopped by the output.

With this configuration, when used as a 2-way, the cache memory IJIC11d becomes unnecessary.
In addition, the power consumption of the selectors 17c and 17d can be reduced, and the wasted power of the processor as a whole can be reduced.

FIG. 4 is a diagram showing the main part configuration of a processor equipped with a cache memory according to a third embodiment of the present invention. A processor 41 shown in the figure determines the functions of cache memories A and B integrated on the same chip using a function definition circuit 43.

The function definition circuit 43 uses the cache memories A and B for instructions or for data according to 2-bit function definition signals PCI and Fe2 applied from outside the processor 41, as shown in FIG. Decide whether to use both or neither.

Therefore, the function definition circuit 43 allows the cache memories A and B to be used separately for instructions or data, depending on the program.

Furthermore, by adding 2-bit function definition signals FC3 and Fe2 given from the outside of the processor 41, the function definition circuit 43 controls the cache memory ASB as shown in FIG.
Define as user area or supervisor area,
The respective cache memories A and 8 may be used.

Note that the function definition signal may be provided to the function definition circuit 43 from a register provided inside the processor.

For example, in a processor equipped with three cache memories, information in 4-bit registers 01 to C4 provided inside the processor determines the number of cache memories that function for instructions or data and the number of cache memories that are not used. It can also be defined as shown in Figure 7.

In addition, the eighth
As shown in the figure, an instruction (
1) In addition to information that distinguishes data (D), user area (U), and supervisor area (S), information that distinguishes between readable and writable (W) and read only (R) is provided,
The function of each cache memory may be selected.

FIG. 9 is a diagram showing the main part configuration of a processor equipped with a cache memory according to a fourth embodiment of the present invention.

The feature of this fourth embodiment is that 2-bit function definition bits C1 and C2 are provided for each of the n cache memories 1 to n, and these function definition bits C
1. The functions of C2 and the cache memory are made to correspond as shown in FIG. 10, and the functions of n cache memories are controlled.

In this way, in the third and fourth embodiments, the functions of a plurality of on-chip cache memories are selected corresponding to each cache memory, so that The degree of freedom of each function can be greatly expanded. This allows the cache memory to have an optimal configuration for the program.

Furthermore, by performing control corresponding to each cache memory, access speed and wasteful power consumption can be reduced.

[Effects of the Invention] As explained above, according to the first and second inventions, the configuration method and capacity of the cache memory are changed depending on the program to be executed. can greatly expand the degree of freedom in how it can be used.

As a result, an information processing device equipped with such a cache memory is able to fully utilize its capabilities, and the efficiency and speed of program execution can be improved.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of a first embodiment of the present invention, and FIG.
3 is a diagram showing the configuration of the second embodiment of the present invention. FIG. 4 is a diagram showing the configuration of the third embodiment of the present invention. Figures to Figures 8 are
FIG. 9 is a diagram showing the configuration of the fourth embodiment of the present invention, and FIG. 10 is an explanatory diagram of the operation of the fourth embodiment. 1a to 1d... Cache memory 3.5... Decoder 7... Address information 9.11a to 11d, 13a to 13d, 17a
~17d, 21.23...Selector 153-15d...Comparator 43...Function definition circuit

Claims (2)

[Claims] (1) A cache memory consisting of a plurality of blocks, an address supply means for supplying an address to a predetermined block of the cache memory, and a configuration of the address supplied from the address supply means and a block to which the address is supplied to the cache memory. changing means for changing the configuration of the memory in accordance with command information that instructs to change the configuration of the memory, and reading out from among the plurality of pieces of information output from a predetermined block of the cache memory according to the address supplied from the address supplying means. selecting means for selecting predetermined information to be selected, and instructing the selecting means to select information according to tag information added to a plurality of pieces of information outputted from a predetermined block of the cache memory and address information given from the outside. 1. An information processing device equipped with a cache memory, characterized in that it has a control means for controlling. (2) A cache memory consisting of a plurality of blocks, and a specification definition means for specifying and defining the type of information to be stored and the attributes of the cache memory so as to be changeable for each cache memory consisting of the plurality of blocks. An information processing device comprising a cache memory.