JP2000099399A - Way predictive cache memory and access method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce energy consumption without decelerating an access speed by providing a way predictive flag for selecting any way independently of tag comparison and a way predictive table for storing that flag, and controlling the operation of the way based on the signal of the way predictive table. SOLUTION: While receiving the status information of ways 21-24 and the signals of comparators 31-34, a predictive update circuit 5 outputs information showing either predictive hit or error and information showing cache error and updates the way predictive flag by predicting the way when a set referred to at present is next accessed. While receiving the predicted result, a way predictive table 6 records a flag designating the way. While receiving this information, an access controller 1 commands which way is to be made active. In the case of predictive hit, an encoder 4 receives the predictive flag of the way predictive table 6 and commands a selector 7 so as to output only the data of the relevant way.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an access method for reducing the energy consumption of an on-chip cache memory.

[0002]

2. Description of the Related Art With the spread of portable electronic equipment systems typified by PDAs and notebook PCs, demands for high performance and low energy consumption of CPUs are increasing. However, performance and energy consumption are generally in a trade-off relationship, and satisfying one of the requirements requires sacrificing the other. A means for simultaneously satisfying these conflicting demands is to mount an on-chip cache. According to this technology, when a hit occurs in the on-chip cache, high performance is achieved by hiding the access latency to the external memory, and low energy consumption is achieved by eliminating external input / output pin driving. However, the cache size has been increasing year by year for the purpose of achieving a higher hit ratio with a steady improvement in transistor integration, and the energy consumption in cache access has been remarkably increased, and the overall CPU consumption has been increased. It has a large effect on energy. The reduction in energy consumption of the cache is an indispensable technical element for realizing energy saving of the entire chip.

[0003] Many conventional high performance CPUs employ a set associative cache system in order to achieve a high hit rate while avoiding cache conflicts. In order to explain such prior art, a general 4-way set associative
The cache will be described with reference to the drawings. FIG. 4 is a diagram showing a configuration of a 4-way set associative cache, which is referred to as a conventional cache here. In the figure, reference numerals 21, 22, 23, and 24 denote memories for holding tags and lines, respectively. When a command is given, tags of all ways are stored in reference addresses in the reference addresses issued by the processors by comparators 31, 32, 33, and 34. The value is compared with the value of the tag field, and the result is output to the encoder 4. The encoder 4 receiving this tag comparison result outputs a control signal of the selector 7 for selecting the only reference line storing the reference data requested by the processor from all the lines corresponding to each way. I do. In the figure, a line refers to a set of data in the cache corresponding to a certain tag address. When there is a mistake, that is, when the data to be referred to is not in the cache, data replacement is performed in line units. Will be A way refers to a set of one tag subarray and a corresponding line subarray. When the degree of association is 4, there are four ways. A set refers to a set of tags and lines having the same index in each way. When the associativity is 4, one set is composed of four sets of tags and lines. The search set is a set that is specified by the index field of the reference address when a memory reference from the processor occurs, and is a target for tag search. A reference line is a line in which data to be referred to by the processor is stored. In the case of a hit, one reference line exists in the search set. In the case of a miss, the reference line exists in the cache. do not do.

Next, the operation of the cache memory having such a configuration will be described with reference to FIGS. FIG. 5 is a flowchart showing a procedure for operating a conventional 4-way set associative cache when a memory reference from a processor occurs. In the first step (S1) of the flow, first, the address output by the processor is decoded. In step (S2), a search set is determined based on the decoding result. In step (S3), tags and lines corresponding to all ways in the search set are simultaneously read from the tag sub-array and the line sub-array. In step (S4), the four read tags are compared with the value of the tag field of the reference address output by the processor, and if any of the results match, the process proceeds to step (S5); Proceed to step (S6). In step (S5), a reference line is selected from the four lines read in step (S3) based on the tag comparison result. Also, the data specified by the offset field of the reference address is selected from within the reference line, and the cache access ends. In step (S6), all four lines read in step (S3) are discarded, and cache replacement is performed. FIG. 6 shows the step (S3).
The point where the information is output from the step (S5) to the step (S5) is indicated by a thick arrow, indicating that all the ways are activated. As described above, in the above-described conventional cache, four tags and four lines are read for each cache access regardless of hit / miss, so that tag comparison and line reference are completed in one access. And operate at high speed.

[0005] On the other hand, a staged cache is configured so as to reduce power consumption as compared with the conventional cache. FIGS. 7A and 7B show the active state in the cache in two steps taken by the staged cache. In the first stage (a), only the tag of each way is read and compared with the information of the reference address of the processor to determine whether there is a way to be referred to. If it is found that any of the ways is referred to, the second stage (b)
Then, only the line of the relevant way is read as a reference line and output from the selector. In the case of this staged cache, the number of tags and lines activated through two stages is five, which is approximately halved compared to the eight positions of the conventional cache shown in FIG. Therefore, the power required for accessing the cache memory is greatly reduced.

[0006]

However, in the above-mentioned conventional cache, tag reading and line reading occur for every way every time a cache access occurs, so that every way consumes power every access. There is a disadvantage of doing so. On the other hand, the above-mentioned tiered cache has half the power as compared with the conventional cache, but at the time of a cache hit, it takes two steps to access it for a long time and operates at high speed. The original effect of the cache memory is halved. The present invention solves the contradictory problems of high speed and low power consumption of a cache memory without trade-off, and a way prediction type cache memory that enables low energy consumption without lowering access speed. And to provide access to it.

[0007]

SUMMARY OF THE INVENTION Accordingly, a way prediction cache memory according to the present invention provides a plurality of ways, an access controller for controlling the operation of the ways, information on tags stored in the ways, and output from a processor. In a cache memory comprising a comparator for comparing information of a tag of a reference address and a selector for outputting a line of a way in which the signal of the comparator is on, a method for selecting a way independently of tag comparison is provided. A way prediction flag, a way prediction table for storing the same, and a signal of the comparator and a signal indicating a way to be replaced at the time of a cache miss are input, and the way prediction flag of the way prediction table for the next access. And a way prediction updating circuit for updating the way prediction table based on a signal of the way prediction table. It is characterized by comprising an access controller for controlling the operation of E i. When the way prediction updating circuit updates the way prediction flag and designates a way in advance, the way designation flag designates the flag corresponding to the most recently referred way, or designates the flag corresponding to the way at random. It is characterized by: The method of accessing a way prediction type cache memory according to claim 4, further comprising: a plurality of ways; an access controller for controlling an operation of the way; information on a tag stored in the way; and a reference address output by the processor. In a cache memory consisting of a comparator for comparing information of a tag and a selector for outputting data of a way in which the signal of the comparator is turned on, any one of the ways is designated in advance, and only one designated way is designated. Read the tag and line information of the way and compare it with the tag information of the reference address output by the processor. If the way is to be read, finish reading that information. Tag and line information is read out, and if any tag comparison result is on, it is turned on. Select the line corresponding to Tsu with a tag supplies reference data to the processor, if also an on any tag comparison, is characterized by performing the replacement of the line according to the cache replacement algorithm. 6. The access method for a way predictive cache memory according to claim 5, wherein the plurality of ways, an access controller for controlling the operation of the way, the tag information stored in the way and the tag of the reference address output by the processor. In a cache memory consisting of a comparator for comparing the information of the way and a selector for outputting data of the way in which the signal of the comparator is turned on, any of the ways is designated in advance, and only the designated way is designated. Reads the tag and line information, compares it with the tag information of the reference address output by the processor, if it is a way to be read, finishes reading that information, and if it is not a way to read, specifies all unspecified ways Tag information and read the tag field of any tag and the reference address output by the processor. There has been characterized by performing replacement of the line according to the based on the tag comparison result is supplied to only the read processor reference line ,, matched unless replacement algorithm if they match. Furthermore, when a way is specified in advance by the access method of the way prediction type cache memory according to claim 4 or 5, the way is specified to the most recently referred way or specified at random. I have. With such a configuration or method, in the case of a prediction hit, it is possible to significantly reduce the energy consumption without impairing the cache performance, and even if there is a prediction miss, the ratio of the prediction miss to all accesses by the processor. Is so small that energy consumption can be reduced as a whole.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a cache memory according to the present invention, FIG. 2 is a flowchart showing an access method thereof, and FIG. 3 is a diagram showing a situation in which a way in a cache is active during access. In FIG. 1, ways 21, 22, 23, 2
4 and the comparators 31, 32, 33, and 34 and the selector 7 are the same as those shown in FIG.
Since the function of the encoder 4 is slightly added to that of FIG. 1 is way 21, 2
This is an access controller that can independently control the operations of 2, 23, and 24, and is a circuit that is an extension of the conventional SRAM access controller. 5 is way 21, 2
2, 23, 24 status information and comparators 31, 32,
In response to the signals 33 and 34, information indicating whether the prediction has been hit or missed and information indicating whether a cache miss has been made are output, and the currently referenced set is accessed when the set is accessed next time. And updates the way prediction flag. Reference numeral 6 denotes a way prediction table for recording a flag designating a way in response to a result predicted by the way prediction update circuit 5. The access controller 1 receives the information of the prediction update circuit 5 and the way prediction flag of the way prediction table 6 and outputs a command indicating which way is to be activated. Encoder 4
Receives a way prediction flag in the way prediction table 6 when a prediction hits, and sends a command to the selector 7 to output only data of the corresponding way. The way in which the prediction update circuit 5 updates the way prediction flag of the way prediction table 6 for prediction includes a method of making the most recently referred way a prospective way and a method of randomly selecting a way as a prospective way. Depends on the program to be used and the cache memory, and the overall effect is compared and determined to determine which one to adopt.

The way prediction type cache memory having such a configuration operates according to the procedure shown in the flowchart of FIG. The procedure is as follows. In the first step (S1), a prediction flag is called from the way prediction table 6 as soon as a reference address is generated, and a prospective way, that is, a way predicted to be referred to by the processor is determined. Can be In step (S2), cache access is started, and the address output by the processor is decoded. Then, the corresponding way is selected by the access controller 2. In step (S3), tags and lines are read from the way selected corresponding to the prospective way. In step (S4), it is determined whether or not the tag of the way corresponding to the prospective way matches the value of the tag field TG of the reference address output by the processor. If they match, the reference data in the line is selected in step (S5) and serviced by the processor to complete the processing, that is, the access to the cache memory. If they do not match in step (S4), in step (S6), the access controller 1 specifies all the ways except the prospective way, and the corresponding tags and lines are called simultaneously. In step (S7), it is determined whether any tag matches the tag field TG of the reference address output by the processor. Specifically, if the two inputs of the comparators do not match, L is output, and if they match, H is output. If they match, in step (S8), the reference line of the corresponding way is selected based on the tag comparison result, the reference data is serviced by the processor, and the process proceeds to step (S10). At this time, for example, if only the way 1 (22) matches in the tag comparison, and the comparator (32) outputs 1,
Encoder 4 controls selector 7 to control way 1 (22)
Is selected and output. If they do not match in step (S7), the line is replaced in step (S9) according to the same replacement algorithm as in the past. The operation procedure of the replacement is publicly known, and the description is omitted. In step (S10),
In the case of a prediction error, the address of the way in which the reference line exists is registered in the way prediction table 6 based on the tag comparison result. For example, in step (S3), way 1 (2
2) does not correspond to the expected way and the output of the comparator 32 is L
, The tags of way 0 (21), way 2 (23), and way 3 (24) are compared, and if the tag of way 2 (23) matches, the cache memory of way 0, 1, 2, 3 Are 00, 01, 10, 11
, Address 10 of way 2 (23)
Is output from the way prediction updating circuit 5 to the way prediction table 6, and the way prediction flag is updated and registered. In the case of a cache miss, that is, when the data referred to by the processor is not in the cache memory, the address of the way to be replaced is registered in the way prediction table 6, and the processing, that is, the access to the cache memory is completed. For example, way 3 (2
If 4) has been updated the oldest, the data set to be replaced-in is stored in way 3 (24), and the information that way 3 (24) has been updated most recently and its address 11 are stored in way 3 (24). It is stored in the way prediction table 6 as a prediction flag.

FIG. 3 is a diagram showing an operation state of a way in such an operation procedure. (A) is a step (S3)
From the step (S5) to the step (S5), and shows that, of the four ways, only the prospective way that matches the reference address is active. In this case, there are only two hits in the first stage and active.
(B) shows the situation of the second stage when the values do not match in step (S4), and shows the situation where the way is active between steps (S6) and (S9). Except for the way that was missed in the first stage, it is active, and when this stage has elapsed, a total of eight are active. At this stage, the power consumption is the same as compared with the conventional cache, and the access time is doubled. Next, a method in which a stepwise cache procedure is incorporated into the above-described way prediction type cache memory access method will be described with reference to FIG. In this method, the steps up to step (S5) in FIG. 2 are the same, but a step-by-step cache procedure is added thereafter. If there is no match in the comparison in step (S4),
In step (S6), the access controller 1 specifies all the ways except the prospective way, and only the corresponding tags are read. However, at this step, the lines have not yet been read. Step (S7)
Then, any tag and the tag field T of the reference address
It is determined whether or not G matches. Specifically, if the two inputs of the comparators do not match, L is output, and if they match, H is output. If they match, in step (S8), only the reference line of the relevant way is read based on the tag comparison result, and in step (S9), the reference data is serviced by the processor, and the process proceeds to step (S11). At this time, for example, if only the way 1 (22) matches in the tag comparison, and the comparator (32) outputs 1,
Encoder 4 controls selector 7 to control way 1 (22)
Is selected and output. If they do not match in step (S7), line replacement is performed in step (S10) according to the same replacement algorithm as in the past. The replacement procedure is as described above.
In step (S11), in the case of a prediction error, the address of the way in which the reference line exists is registered in the way prediction table 6 based on the tag comparison result. The operation state of each way according to this method is as follows.
The third and third stages are a combination of (a) and (b) in FIG. In the embodiment, the case where the number of ways is four is shown.
If there is more than one, they operate in the same way, so they may be determined in consideration of overall speed and energy consumption. When the present invention is applied, there are cases where the process ends up to the first stage and cases where the process requires the second stage or the third stage. In view of the actual operation and characteristics of the CPU, recently cited data is re-cited. Very often, and very often end up with the first stage. Specifically, the average access status shows that although the access time has increased by 10% compared to the conventional cache, the energy consumption has increased by 70%.
It turns out that it can be reduced. As described above, since the cache memory of the present invention and the access method thereof utilize the characteristics of the CPU and determine the expected way to access, the power consumption of the entire cache memory is significantly reduced as compared with the conventional type. You can do it.

[0011]

As described above, according to the present invention, the power consumption can be greatly reduced by only slightly suppressing the decrease in the access speed of the cache memory. There is an effect that it can be increased.

[Brief description of the drawings]

FIG. 1 is a block diagram of a way prediction type cache memory according to the present invention.

FIG. 2 is a flowchart showing a procedure of an access method of the present invention.

FIG. 3 is a diagram illustrating the operation of a way prediction cache memory according to the present invention;

FIG. 4 is a block diagram of a conventional cache memory.

FIG. 5 is a flowchart showing a procedure of a conventional access method.

FIG. 6 is a diagram illustrating the operation of a conventional cache memory.

FIG. 7 is a diagram illustrating the operation of a conventional cache memory.

FIG. 8 is a flowchart showing a procedure of a second access method of the present invention.

[Explanation of symbols]

 Reference Signs List 1 access controller 21, 22, 23, 24 way 31, 32, 33, 34 comparator 4 encoder 5 prediction update circuit 6 way prediction table 7 selector

Claims (7)

[Claims] 1. A plurality of ways, an access controller for controlling the operation of the ways, a comparator for comparing information of a tag stored in the way with information of a tag of a reference address output by a processor, and the comparison Memory, comprising a selector for outputting data of a way whose signal is turned on, a way prediction flag for performing way selection independently of tag comparison, and a way prediction table for storing the same. A way prediction update circuit for updating the way prediction flag of the way prediction table for the next access by inputting a signal of the comparator and a signal indicating a way to be replaced at the time of a cache miss; An access controller for controlling the operation of the way based on a signal. Way predictive cache memory to be. 2. The method according to claim 1, wherein when the way prediction updating circuit updates the way prediction flag and specifies a way in advance, the way prediction update circuit specifies a flag corresponding to the most recently referred way. Way prediction cache memory. 3. The way prediction type according to claim 1, wherein when the way prediction updating circuit updates the way prediction flag and designates a way in advance, the way prediction type circuit randomly designates a flag corresponding to the way. Cache memory. 4. A plurality of ways, an access controller for controlling the operation of the ways, a comparator for comparing tag information stored in the ways with tag information of a reference address output by a processor, In a cache memory consisting of a selector that outputs data of a way whose signal is turned on, one of the ways is designated in advance, tag and line information of the designated unique way is read, and the processor outputs If the way is to be read in comparison with the tag information of the reference address specified, the reading of the information is finished. If the way is not the way to be read, the tag and line information is read by specifying all the unspecified ways. If the tag comparison result is ON, select the line corresponding to the tag that is ON and process the reference data Supplied, if also an on any tag comparison result way predictive cache memory access method and performing replacement of the line according to the cache replacement algorithm. 5. A plurality of ways, an access controller for controlling the operation of the ways, a comparator for comparing the information of the tags stored in the ways with the information of the tags of the reference addresses output by the processor, and the comparator In a cache memory consisting of a selector that outputs data of a way whose signal is turned on, one of the ways is designated in advance, tag and line information of the designated unique way is read, and the processor outputs If the way is to be read in comparison with the tag information of the reference address specified, the reading of the information is terminated. If the way is not the way to be read, the tag information is read by specifying all the unspecified ways. If the tag and the tag field of the reference address output by the processor match, the reference line based on the tag comparison result Only supplied to the read processor,
A method for accessing a way prediction type cache memory, characterized in that if they do not match, a line is replaced according to a replacement algorithm. 6. The method according to claim 4, wherein when the way is designated in advance, the way referred to most recently is designated.
Or the access method of the way prediction type cache memory according to 5. 7. The access method for a way prediction type cache memory according to claim 4, wherein when the way is designated in advance, the way is designated at random.