JPH0395649A - Cache device - Google Patents

Abstract

PURPOSE:To control the memory traffic when the context is switched by providing an index changing part as well as a tag changing part which changes the tag in accordance with the cache application size. CONSTITUTION:A tag changing part 10 changes a tag by rewriting several lower rank bits of a tag of 20 bits segmented out of an address into 0 in accordance with the cache application size information. At the same time, an index changing part 11 changes an index by rewriting several higher ran bits of an index of 8 bits segmented out of an address in accordance with the cache application size information. That is, the cache application size can be limited when the tag and the index are changed in accordance with the cache application size information. Then the cache capacity is effectively changed with change of the tag and the index which are used for retrieval of the data stored in a cache. Thus it is possible to control the traffic due to a writing operation applied to a memory at switch of the context.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a cache device for performing effective memory access at high speed, which can adjust memory traffic and efficiently store L data. be.

Conventional technology As a conventional cache device (for example, "cache memory" Nagashima and Hori, Information Processing El, VOI, 21, N
o. 4, 9.332-340, 1980, there is a sector type cache device. Sector-based cache device (Yo) Since the target of caching is a contiguous area in memory, the hit rate does not drop significantly and is small when only accesses to a very limited address range occur, such as in the stack. Caching can be implemented in hardware.

FIG. 5 shows the structure of a conventional cache device. 1 is a tag register, 2 is a comparison register that compares the tag part cut out from the address and the contents of tag register 1. 3
is a decoder' that decodes the index section cut out from the address, 4 is a data array, 5 is a valid flag array that indicates the validity of data in data array 4,
6 is an AND gate.

Also, the cache capacity is 256 bytes, and the address is 24
The bit and index are the lower 8 bits of the address, and the tag is the upper 16 bits of the address. The method for writing cache data into memory is the write-back method.

The operation of the conventional cache device configured as described above will be explained.

In the case of data reading, when an address is input, a comparator 2 compares the tag part of the address with the contents of the tag register 1. Simultaneously with the tag comparison, the decoder 3 selects one entry in the decode record data array 4 and the corresponding flag in the valid flag array 5 using the index part of the address.

Comparator 2 compares the tag part of the address with tag register 1.
When it is detected that the contents of {.
t, the HIT signal is activated by the AND gate 6, and data can be read from the corresponding entry in the data array 4 without accessing the memory.

When the tag part of the address and the contents of the tag register l match and the corresponding flag in the valid flag array 5 is inactive, the entry in the 4i data array 4 is invalid and an access to the memory occurs. The tag part of the address and the contents of tag register l do not match, and the signal TA
When GEQ is inactive, the contents of tag register 1 are rewritten using the tag part of the address. At the same time, all flags in valid flag array 5 are invalidated and the memory is accessed.

When writing data, Ci comparator 2 detects that the tag part of the address matches the contents of tag register 1, and when TAGEQ becomes active, data is written to the corresponding entry in data array 4.
Does not access memory.

At this time, if the corresponding flag in the valid flag array 5 is inactive, that flag is activated. The tag part of the address and the contents of tag register 1 do not match.1 When the signal TAGEQ is inactive (upper
Rewrite the contents of tag register 1 with the tag part of the address
At the same time, all flags in the valid flag array 5 are invalidated and the memory is accessed.

By the above-described operation, it is possible to effectively speed up memory access when a cache hit occurs.

Problem to be Solved by the Invention However, in the above structure, the size of the cache used remains the originally designed size,
When a context switch occurs and cache data needs to be written to memory, in some cases all data in the cache must be written.
% Therefore, the present invention, which had the problem of not being able to specify the traffic due to memory writing at the time of a context switch, aims to provide a cache device that can adjust the memory traffic at the time of a context switch in view of this problem.

Means for Solving the Problems The present invention provides a cache device including means for changing an index for determining a cache entry based on used capacity information, and means for changing an address tag based on used capacity information.

Operation The present invention makes it possible to change the size used as a cache using the above-described means, thereby making it possible to adjust traffic due to memory writing when a context switch occurs.

Embodiment FIG. 1 is a block diagram of a first embodiment of a cache device according to the present invention. ■ is a tag register, 2 is a comparison register that compares the tag part extracted from the address and the contents of tag register 1, 3 is a decoder' that decodes the index part extracted from the address, 4 is a data array, 5
1 is a valid flag array indicating the validity of data in the data array 4; 6 is an AND gate; IO is a tag change ridge for changing the tag according to the cache use size; 11 is an index change section for changing the index according to the cache use size.

The maximum capacity of the cache device in the first embodiment is 25
It is 6 bytes. The address is 24 bits, the index is the lower 8 bits of the address, and the tag is the upper 2 bits of the address.
It is 0 bit, and the tag and index have a 4-bit overlap. The method for writing cache data into memory is the write-back method.

The operation of the cache device of the first embodiment configured as described above will be explained below.

The tag change unit 10 changes the tag by rewriting the lower several bits of the 20-bit tag cut out from the address to O according to the cache usage size information.The index change unit 11 changes it according to the cache usage size Rewrite and change the upper few bits of the 8-bit index extracted from the address. Change the tag and index as shown in Figure 2 (L cache usage size can be limited).

In the case of data reading, when an address is input, the comparator 2 compares the tag changed by the tag changing unit 10 with the contents of the tag register l. At the same time as the tag comparison (to), the index changed by the index changing unit l1 is decoded by the decoder 3, and one entry in the data array 4 and the corresponding flag in the valid flag array 5 are selected.

If the comparator 2 detects that the content of the modified tag and the tag register 1 match, then the corresponding flag in the valid flag array 5 is active;
The HIT signal is activated by the ND gate 6,
Data can be read from the corresponding entry in the data array 4 without accessing the memory. If the change tag and the contents of free register 1 match, then when the corresponding flag in valid flag array 5 is inactive, the corresponding entry in data array 4 is invalid.
An access to memory occurs. When the contents of the change tag and the tag register 1 do not match and the signal TAGEQ is inactive, the contents of the tag register 1 are rewritten with the change tag, and at the same time all flags in the valid flag array 5 are invalidated and the memory is accessed.

In the case of data writing (above), when comparator 2 detects that the contents of the change tag and tag register l match and TAGEQ becomes active, data is written to the corresponding entry in data array 4. Do not access the memory (t) At this time, if the corresponding flag in the valid flag array 5 is inactive, that flag is activated. When the signal TAGEQ is inactive (Table 1), the contents of the tag register 1 are rewritten with the changed tag, and at the same time all flags in the valid flag array 5 are invalidated and the memory is accessed.

As described above, according to the first embodiment of the present invention
By changing the tag and index for searching data in the cache, it is possible to effectively change the cache capacity and adjust the traffic due to writes to memory during context switches and the like.

FIG. 3 is a configuration diagram of a second embodiment of the cache device of the present invention. The second embodiment is a cache device that allows the cache usage size to be changed and also allows multiple areas to be cached. It is. 1 is a tag register, 2 is a comparison register that compares the tag part extracted from the address and the contents of tag register 1, 3 is a decoder' that decodes the index part extracted from the address, 4 is a data array, and 5 is a data array in 4. 6 is an AND gate, 10 is a tag change function that changes the tag according to the cache usage size, l1 is an index change function that changes the index according to the cache usage size, 12 is a tag register as necessary. 13 is a tag register control unit that holds the contents of tag register 1 and switches the contents of tag register 1.
is a selector.

The maximum capacity of the cache device in the second embodiment is 25
It is 6 bytes. The address is 24 bits, the index is the lower 8 bits of the address, and the tag is the upper 2 bits of the address.
It is 0 bit, and the tag and index have a 4-bit overlap. The method for writing cache data into memory is the write-back method. Mana Two areas can be cached: user space and system space.

The operation of the cache device of the second embodiment configured as described above will be explained below.

The tag change unit 10 changes the lower several bits of the 20-bit tag extracted from the address to 0 according to the cache usage size information.The index change unit 1l changes the cache usage size and space information. Accordingly, the upper few bits of the 8-bit index extracted from the address are rewritten and changed.
As shown in the figure, you can change the cache usage size for user space and system space by changing tags and indexes.

The tag register control unit 12 rewrites the tag register 1 according to the system space and user space based on space information.

A tag for system space or user space is set in tag register 1 (according to space information). When reading data, when an address is input, the tag changed by tag change unit 10 and the contents of tag register 1 are set. are compared by comparator 2. At the same time as the tag comparison, the index changed by index change unit l1 is decoded by decoder 3, and one entry in data array 4 and the corresponding flag in valid flag array 5 are selected. .Comparator 2
When the corresponding flag in the valid flag array 5 is active, the HIT signal is activated by the AND gate 6, and the contents of the modified tag and the tag register 1 are matched. Data can be read from the corresponding entry in the data array 4 without access. When the change tag and the contents of the tag register 1 match, the corresponding flag in the valid flag array 5 is inactive, the corresponding entry in the data array 4 is invalid, and an access to the memory occurs. When the contents of the changed tag and the tag register 1 do not match and the signal TAGEQ is inactive, the contents of the tag register 1 are rewritten with the changed tag or the contents of the corresponding space held in the tag register control unit 12 are At the same time, all flags in the valid flag array 5 are invalidated, and when writing data to the memory, the comparator 2 confirms that the contents of the changed tag and the tag register 1 match. When detected and TAGEQ becomes active, the data is written to the corresponding entry in data array 4 and the memory is not accessed.At this time, if the corresponding flag in valid flag array 5 is inactive, the Activate flag: said change tag and tag register 1
When the contents do not match and the signal TAGEQ is inactive, the contents of the tag register l are rewritten with the change tag, and (1) the information held in the tag register control unit 12 for the corresponding space is rewritten. At the same time, invalidate all flags in valid flag array 5. Access the memory.

As described above, according to the second embodiment of the present invention,
By changing the tag and index for searching data in the cache, it is possible to effectively change the cache capacity and adjust the traffic due to writes to memory during context switches and the like. By using the tag register control unit 12, the contents of the tag register 1 can be switched according to the target area, thereby realizing efficient caching. Only L
In this embodiment, the force support is given in the case of two areas, but it is also possible to deal with three or more areas.

Mana Boundary of division by area in data array 4 (
It can be set arbitrarily as a power of 2, and the usage size can be set for each area.

However, it is clear that the present invention is effective not only in sector-based cache devices, but also in direct map systems, set associative systems, and the like.

Effects of the Invention As explained above, according to the present invention, by making it possible to change the size used as a cache, it is possible to adjust the traffic due to memory writes when a context switch occurs, and the practical effects are as follows. dog chicken

[Brief explanation of drawings]

FIG. 1 shows the structure of a first embodiment of the cache device of the present invention. FIG. 2 shows an example of changing the cache usage size due to changes in the tag changing unit and the index changing unit. FIG. 3 shows the cache of the present invention. FIG. 4 is a diagram showing the configuration of the first embodiment of the device, and FIG. 4 shows an example of changing tags and indexes when the cache is divided into multiple areas. FIG. It is a diagram. 1... Tag Regis long 2... Comparison @ 3... Missing decoder 4... Data array, 5... Valid flag array, 6... AND gate, lO... Tag change K
11... Index change R. 12...Tag register control K 13...Selector.

Claims (2)

[Claims] (1) A cache device comprising means for changing an index for determining a cache entry based on used capacity information, and means for changing an address tag based on used capacity information. (2) A means for changing an index for determining a cache entry based on used capacity information, a means for changing an address tag based on used capacity information, and a means for holding a plurality of tags and switching between the held tags. A cache device characterized by: