JPH01231460A - Integrated circuit for line data transmission/reception - Google Patents

Abstract

PURPOSE:To easily obtain a bit pattern on a line without requiring a special monitoring device or much hardware quantity and to attain fault analysis by storing a bit serial data sent to a line and devising the data to be outputted externally in parallel in a prescribed unit. CONSTITUTION:A shift register 17 storing tentatively a bit serial signal and the 2nd output terminal 30 through which the stored content of the shift register 17 is sent as a parallel output are provided to the circuit. A control circuit 18 informs it externally when the signal in the shift register 17 shifting and storing sequentially each bit to be sent to the line and connected to a selection circuit 18 reaches a preset bit number and the signal is read externally through the 2nd output terminal 30. Then the shift register 17 is reset when the signal therein is read externally and starts the shift storage again. Thus, the bit pattern on the line is easily obtained as a monitor output to attain fault analysis and the data inputted to a line data transmission reception integrated circuit for high speed line in the character interleave is monitored simply.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an integrated circuit for transmitting and receiving line data. In particular, the present invention relates to an integrated circuit for transmitting and receiving line data when monitoring transmitted data or when converting a low-speed line to a high-speed line using character increment.

〔overview〕

The present invention is an integrated circuit for transmitting/receiving line data that manually inputs data to be transmitted as a parallel signal of multiple bits and outputs it as bit serial data. By enabling parallel output to the outside, it is possible to easily monitor the bit pattern on the line without requiring special monitoring equipment or large amounts of hardware.

[Conventional technology]

Conventionally, with this type of integrated circuit for transmitting and receiving line data, the only way to monitor data sent to the line is to connect a monitoring device to the line. Generally, the data input to the line data transmission/reception integrated circuit and the data on the line do not match due to the addition of error detection control codes, so it is necessary to connect monitoring equipment to detect faults.

In addition, when converting a low-speed line to a high-speed line using character interleaving, it is necessary to generate a bit pattern to be sent on the line and input it as transmission data to the line data transmission/reception integrated circuit for the high-speed line, which requires a lot of hardware. "requires a large amount of wear".

[Problem that the invention seeks to solve]

The conventional integrated circuit for transmitting and receiving line data described above has the disadvantage that it requires special monitoring equipment or a large amount of hardware because it is difficult for the control unit that controls the integrated circuit from outside to monitor the line transmission data. be.

The present invention eliminates these drawbacks by making it possible to easily obtain the bit pattern on the line without requiring special monitoring equipment or a large amount of hardware, thereby making it possible to analyze failures. An object of the present invention is to provide an integrated circuit for transmitting and receiving line data that can easily obtain data that is manually input to the integrated circuit for transmitting and receiving line data for a high-speed line in a leave.

[Means for solving problems]

The present invention includes an input terminal for inputting data to be transmitted as a multi-bit parallel signal, means for converting the parallel signal of this input terminal into a bit serial signal, and a first output terminal for sending out this bit serial signal. An integrated circuit for transmitting/receiving line data comprising: a shift register that temporarily stores the bit serial signal; and a second output terminal that sends out the contents stored in the shift register as a parallel output.

[Effect]

The means for sequentially shifting and storing the data sent to the line bit by bit accumulates the data converted to bit serial data in a fixed unit for output to the line, and when the preset number of bits is reached, the data is stored. Output in parallel from the second output terminal.

After this output, it is reset and starts the shift storage operation again.

In this way, the bit pattern on the line can be easily obtained as a monitor output, making it possible to analyze faults and easily monitoring the data input to the integrated circuit for transmitting and receiving line data for high-speed lines with character interleaving. be able to.

〔Example〕

Next, embodiments of the present invention will be described based on the drawings.

The figure is a block diagram showing the configuration of an embodiment of the present invention.

The line data transmission/reception integrated circuit 10 according to the embodiment of the present invention includes an input terminal 20 for manually inputting data to be transmitted as a multi-bit parallel signal, and registers 11 and 12 for converting the parallel signal of the input terminal 20 into a bit serial signal. Selection circuit 1
3 and a shift register 14, and a first output terminal 40 that sends out this bit serial signal, and as a feature of the present invention, a shift register 17 that temporarily stores the bit serial signal, and a shift register 17 that stores the stored contents of this shift register 17 in parallel. and a second output terminal 30 for sending out output.

Further, an error detection code generation circuit 15 connected to the shift register 14, a selection circuit 16 connected to the shift register 14 and the error detection code generation circuit 15, and a signal line 5
0 and a control circuit 18 connected to 0.

Each of the above circuits is a general register, shift register, or selector, and the error detection code generation circuit 15 is a CR
It has functions such as C calculation or parity generation, and is composed of a set of adders and gates.

Next, the general transmission operation of the line data transmission/reception integrated circuit 10 will be described. First, the contents of the register 11 are transferred to the shift register 14, shifted bit by bit, and sent to the line via the selection circuit 16 via the first output terminal 40. General data is then transferred from register 12 to shift register 14 and similarly to first terminal 40.
At the same time, it is input to the error detection code generation circuit 15 to generate an error detection code, and if it is a parity bit for each character, the contents of the error detection code generation circuit 15 are sent to the shift register 140 line. Selection circuit 1
6 to the line.

The above is the general operation of the conventional line data transmission/reception integrated circuit, but the operation of the shift register 17 according to the present invention, which operates in addition to this, will be explained.

The shift register 17 is a register that is connected to the selection circuit 16 and sequentially shifts and stores each bit sent to the line. When this shift register 17 reaches a preset number of bits, the control circuit 18 notifies the outside.
The second output terminal 30 allows the data to be read out to the outside. When read externally, it is reset and the shift/storage operation starts again. Incidentally, in order to increase the time margin for reading, the shift register 17 can also include a reading buffer register.

〔Effect of the invention〕

As explained above, according to the present invention, by accumulating bit serial data sent to a line and making it possible to output it in parallel to the outside in fixed units, special monitoring equipment or a large amount of hardware can be saved. Since the pit pattern on the line can be easily obtained without the need for additional data, failure analysis becomes possible, and the data that can be input manually to the integrated circuit for transmitting/receiving line data for high-speed lines in character increments can be easily obtained. be.

[Brief explanation of the drawing]

The figure is a block diagram showing the configuration of an embodiment of the present invention. IO... integrated circuit for transmitting and receiving line data, 11-12.
...Register, 13...Selection circuit, 14...Shift register, 15...Error detection code generation circuit, 16...
- Selection circuit, 17... Shift register, 18... Control circuit, 20... Input terminal, 30... Second output terminal, 40... First output terminal, 50... Signal line.

Claims (1)

[Claims] 1. An input terminal (20) for inputting data to be transmitted as a parallel signal of multiple bits, and means (11, 12, 13, 14) for converting the parallel signal of this input terminal into a bit serial signal. ) and a first output terminal (40) for transmitting the bit serial signal, the shift register (17) temporarily stores the bit serial signal.
), and a second output terminal (30) that sends out the contents stored in the shift register as a parallel output.