JPH01230151A - Memory - Google Patents

Abstract

PURPOSE:To enhance a processing speed by clearing-processing data whose transfer has been completed in a bit map memory in parallel with a processing to transfer the data from the bit map memory to a recording part. CONSTITUTION:One of the data in plural bit map memory areas designated by transferred dressing information is transferred to a recording part 107, and a data transfer setting means to transfer the clearing information to the other data is provided. Consequently, when the data are transferred to the recording part 107, since the data of the memory whose transfer to a bit map memory 104 is completed are simultaneously zero-cleared, the next data can be immediately developed after the completion of the all data transfer in the bit map 104. Thus, the processing speed in the whole device can be enhanced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a recording device having a bitmap memory.

[Prior Art] Conventionally, in this type of recording device, when developing recorded dot data on a bitmap memory, the print pattern is developed only in a portion where there is print information. -No processing is performed on the margins other than those listed above. For this reason,
After transferring the data from the bitmap memory to the recording section,
When developing new recorded data on the bitmap memory, it is necessary to clear the bitmap memory, and this clearing is performed independently of other processing.

[Problems to be Solved by the Invention] However, in the above conventional example, since the process of clearing the bitmap memory to O cannot be performed in parallel with other processes, a separate processing time is required for clearing the bitmap memory to O, and as a result, There was a problem in that the processing speed of the entire recording apparatus decreased.

The present invention has been made in view of these conventional problems, and its purpose is to solve the problems of the hit map memory.
It is an object of the present invention to provide a recording device in which the processing speed of the entire device is improved by enabling clearing to be performed in parallel with other processing.

[Means for Solving the Problems] To achieve this goal, the present invention provides a recording device that transfers data developed in a bitmap memory to a recording section and performs recording, in which a plurality of bitmap memory areas constituting the bitmap memory and , address transfer setting means for transferring address information having a predetermined mutual relationship to each of the plurality of bitmap memory areas; The present invention is characterized by comprising data transfer setting means for transferring one data to the recording section and transferring clear information to other data.

[Operation] According to the above configuration, in parallel with the process of transferring data from the bitmap memory to the recording section, it is possible to perform a process of clearing data that has already been transferred in the bitmap memory.

[Embodiments] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

1 to 6 show a first embodiment of the present invention, and FIG. 1 is a block diagram showing the configuration of the device of the embodiment. In the same figure, 101 is a host computer interface that directly receives recorded data from the host computer;
Reference numeral 2 denotes a page buffer memory which temporarily stores the recorded data received by the interface 101 and sends the recorded data at a predetermined timing, and 103 converts the recorded data sent from the page buffer memory 102 from code data to dot data. Character generator, 104
is a bitmap memory that develops the dot data converted by the character generator 103 in the actual recording mode;
105 is a printer interface that outputs the recording data on the bitmap memory to a printer recording section; 107 is a printer recording section that records dot data on a recording medium; and 108 is a control section that controls processing in each of the above sections.

In the above-described configuration, the recording code data received by the host computer interface 101 is stored on the page buffer memory 102 and is not page-managed by the control unit 108, so that it is stored in the character generator 1.
Sent to 03. In the character generator 103,
A dot pattern is generated based on the coat data and developed onto the bitmap memory 104. The recorded dot data on the bitmap memory 104 is transferred to the printer interface 105 at a predetermined timing, and here the data is outputted to the printer recording unit 107 according to the recording sequence, and is recorded by, for example, ink transfer, ink sheet, or laser beam. It will be done.

2 shows the details of the bitmap memory shown in FIG. 1. In FIG. A bus controller 5203 that changes the bus for data transfer is a subtraction circuit that subtracts 2 from the address, and a bus controller 204 is used to transfer data to and from the control unit 108, transfer recording data from the character generator 103, or transfer data to the recording unit. 205 is an address bus switching circuit that selects an address bus based on a signal from the bus controller 202; 206 is a data bus switch that selects a data bus based on a signal from the bus controller 202; Circuits A and B are bitmap memories each showing the bitmap memory 104 divided by address.

Bitmap memory A and bitmap memory B are 16
It is configured to be accessed alternately bit by bit, ie, every two bytes (one word), depending on the address.

FIG. 3 shows the structure of the bitmap memory. One address corresponds to one byte of memory space, and as described above, bitmap memory A and bitmap memory B are accessed alternately in units of two bytes. When reading or writing in the bitmap memory other than when transferring recording data to the bitmap memory or transferring data from the bitmap memory to the recording unit 107 via the slinter TF 105, switch as shown in FIG. In the section 205 or 206, data flows as indicated by arrows C or D in the same figure, and the memory is accessed in the same way as normal reading and writing. In this case, since the data addresses in bitmap A and bitmap B are different, only one of them is accessed in one process.

On the other hand, FIG. 4 shows the flow of data when recording data is transferred from the bitmap memory A to the recording section 107 via the printer interface 105. That is, the data flow in the address switching circuit 205 is set by the bus controller 202 as shown by the arrow in the figure, and the read address is set to bit map A, and the address obtained by subtracting 2 from the read address, that is, the process immediately before this transfer process, is The address at which the transfer has been completed is given to bitmap B.

The bus controller 202 also includes a data bus switching circuit 2.
Set the data flow in 06 as shown by the arrow in the figure,
Data read from bitmap A is sent to data bus 204, and data O is given to bitmap B. In this way, while reading from bitmap A, 0 is simultaneously written to the data at the address where transfer has ended on bitmap B, thereby realizing 0 clearing at the end of the transfer.

Normally, in the bitmap memory 104, recorded data is developed in consecutive addresses, so when the transfer of one word (2 bytes) is completed, the data at the address incremented by 2 becomes the next transfer word. Therefore, recording data is read from bitmap B this time, and 0 is written to the data at the address obtained by subtracting 2 from the read address in bitmap A.

FIG. 5 shows the state at this time, and the switching circuits 205 and 206 are set as indicated by the arrows in the figure. As explained above, when recording data is transferred using consecutive addresses, 0 of the data transferred to the recording unit 107 is
Clearing can be done automatically.

FIG. 6 shows each processing step during the above transfer. Here, it is assumed that data is transferred to m+2 addresses from address neo to address n+m+1. First, in step SO, 16
Transfer by reading bit width. Next, in step S1, O is written to the memory at the address read in step SO, and at the same time, addresses n+2 and n+ are written.
Read and transfer the data of 3.

Thereafter, steps 52, 53...S(m/2.) are used as decoys to transfer the data by reading to addresses n+m and n+m+1, and step S(m/2+1
), the memory at addresses n+m and n++r1 is cleared to O, and data transfer on the bitmap 104 is completed.

As explained above, according to this embodiment, at the same time as the data is transferred to the recording unit 107, the data in the bitmap memory 104 whose transfer has been completed is cleared to 0, so that after all the data in the bitmap 104 is transferred, , you can immediately expand the next data.

FIG. 7 is a block diagram of a bitmap memory configuration according to a second embodiment of the present invention, in which elements similar to those shown in FIG. 2 are given the same reference numerals and have similar functions. The explanation of the elements will be simplified. In the figure, 30-1 is an address bus, 302 is a bus controller that switches between bitmap memory A or bitmap memory B, and the memory that sends and receives data, and 309 and 310 are bitmap memory A and bitmap memory B enabled. This is the control line.

FIG. 8 shows the address structure of bitmap memory A and bitmap memory B in this embodiment. In this embodiment, as shown in FIG.
and bitmap memory B each consist of consecutive addresses, and the lower bit information at these addresses indicates individual addresses in bitmap memories A and B, and the corresponding lower bit information in memories A and B is the same. It is. Further, either bitmap memory A or B is selected depending on the upper bit information. Furthermore, the configuration shown in FIG. 7 also has the function of allowing simultaneous access to both bitmap memories.

In addition to transferring data to the recording unit 107, when reading or writing such as expanding dot data, the bus controller 302 turns on the enable signal of the control line 309 that is manually input to the bitmap A, and the switching circuit 206 is switched on as shown in FIG. Bitmap A is accessed as shown in FIG. Further, when accessing bitmap B in a similar manner, the enable signal on the control line 310 is turned on and the switching circuit 206 is configured as shown in FIG. This allows bitmap memory A and bitmap memory B to be used in a general memory format.

On the other hand, when transferring the recording "dot data expanded from the bitmap memory A to the recording section 107 via the printer IF 105, the bus controller 302
The enable signals 310 and 310 are both turned on, and the switching circuit 206 is set as shown in FIG. As a result, data bus 204 is connected to bitmap memory A, and data O is output to bitmap memory B. As a result,
At the same time as reading recorded data for transfer from bitmap memory A, bitmap memory B is cleared to O.

Similarly, when reading recorded data from bitmap memory B, the enable signals of control lines 309 and 310 are both turned ON, and switching circuit 206 connects data bus 204 to bitmap memory B as shown in FIG. , outputs data O to bitmap A. Thereby, when reading recorded data from bitmap B, bitmap A can be cleared at the same time.

In the first embodiment, bitmap A and bitmap B were switched for each word, but in this embodiment, bitmap A and bitmap
It becomes possible to treat the bitmap memory and bitmap B as one memory block, develop recorded data in either one, and develop new data in the other bitmap memory, which is cleared O at the same time as the recorded data is transferred.

FIG. 13 shows each step in the process of transferring data in the bitmap memory in this embodiment. In the figure, step Tl-76 indicates each step of the transfer process during the recording operation of the recording section 107. In each of bitmap memories A and B, addresses from the top to the bottom in the figure are continuous. First, in step T1, development of recorded dot data on bitmap A is started, and in step T2, the development is completed. Next, in step T3, data transfer to the recording unit 107 via the printer IF 105 is started. At the same time, the corresponding address portion of bitmap B is cleared to 0. At step T4, the transfer and O-clearing in bitmap A and bitmap B are continued, and at the same time, new data is started to be developed in the part of bitmap B that has already been cleared to zero. This process is continued until the data transfer of bitmap A is completed.

Next, in step T5, data transfer is started from the part where the expansion started in step T4 has ended, and at the same time bitmap A is cleared to 0. At step T6, the above transfer is completed, and at the same time, new data begins to be developed in the part of bitmap A that has been cleared to 0. Thereafter, T1 to T6 are repeated.

As described above, even if this method is used, O can be cleared in the bitmap memory while data is being transferred from the bitmap memory to the recording section, and the processing time for clearing the bitmap memory to 0 can be saved.

[Effects of the Invention] As is clear from the above description, according to the present invention, in parallel with the process of transferring data from the bitmap memory to the recording unit, the process of clearing the data that has already been transferred in the bitmap memory is carried out. It becomes possible to do so.

As a result, there is no need to separately set the time required to clear the transferred data in the bitmap memory, resulting in an effect that the processing speed of the entire apparatus is improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. FIG. 2 is a block diagram showing the bitmap memory configuration of the first embodiment of the present invention. FIG. 3 is a block diagram showing the bitmap memory configuration of the first embodiment of the present invention. 4 and 5 are block diagrams showing the bitmap memory structure of the first embodiment. FIG. 6 is a conceptual diagram showing the data transfer and 0 clearing process in the first embodiment. The figure is a block diagram showing the bitmap memory configuration of the second embodiment. Figure 8 is a conceptual diagram of the bitmap memory address configuration of the second embodiment. Figures 9 to 12 are the bitmap memory configuration of the second embodiment. - A block diagram showing the configuration. FIG. 13 is a conceptual diagram showing data transfer and 0 clear processing in the second embodiment. 101... Host computer interface, 102... Page buffer memory, 103... Character generator, 104, A, B
...Bit map memory, 105...Printer interface, 107...Printer recording section, 108...Control section, 201.301...Address bus, 202.302...Bus controller, 203...・
Subtraction circuit, 204...Data bus, 205...Address bus switching circuit, 206...Data bus switching circuit, 309.310...Control line. Fig. 3: Let's repulse the enemy. 1 Arobi, 7 Toma, 7 Pume Shiri Do. To Tobe) To agony? -1
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Claims (1)

[Claims] 1) A recording device that transfers data developed in a bitmap memory to a recording unit and performs recording, comprising: a plurality of bitmap memory areas constituting the bitmap memory; and the plurality of bitmaps. Address transfer setting means for transferring address information having a predetermined relationship to each of the memory areas; and one of the data in the plurality of bitmap memory areas respectively designated by the transferred address information.
1. A recording device comprising: data transfer setting means for transferring one data to the recording section and transferring clear information to other data.