JPH01229322A - Micro processor with decimal multiplier - Google Patents

Abstract

PURPOSE:To directly execute the multiplication of the multiplicand data of an integer and multiplier data of a decimal by providing a multiplication control block which sets an arithmetic logical operation means to add data in which a previous addition result is shifted right to multiplicand data. CONSTITUTION:In a micro processor having a decimal multiplier, a multiplication control circuit 41 consisting of a decoder 34 and a bit AND circuit 31 discriminates values for the bits of multiplicand data supplied through a data bus 10 by the signal of a multiplication control circuit 35 and the multiplication control block 30 which drives a switch group 32 by said result and which sets an arithmetic logical operation unit ALU 20 to add data in which the previous addition result is shifted right 33 to multiplicand data supplied from the bus 10 is provided. With such a constitution, multiplicand data of the integer and multiplication data can directly be added and an execution speed can be made faster than a multiplier which deals only integers.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a microprocessor having a fractional multiplier suitable for controlling equipment. Conventional technology Many modern microprocessors are equipped with multiplication instructions, and general-purpose microprocessors are equipped with integer multipliers, which are used for signal processing and equipment control. Equipped with a multiplier. Now, if we consider the case where the main part of a motor rotational speed control device as shown in FIG. After performing compensation in the frequency domain, it is converted into a DC voltage by the DA converter 3. By the way, as is well known, this type of digital filter generally uses decimal numbers as multipliers. On the other hand, what is manually input to the digital filter 2 is integer error detection data. As such a multiplier, a multiplier that handles only integers or a large-scale floating point multiplier is used. Problems to be Solved by the Invention However, the conventional microprocessor multiplier as described above has a problem in that it cannot directly multiply an integer multiplicand by a decimal multiplier. Therefore, a multiplier that handles only integers requires a large number of multipliers in order to speed up execution, which increases the area of the IC and also causes high costs. Means for Solving the Problems In order to solve the above-mentioned problems, a microprocessor having a decimal multiplier according to the present invention determines the value of each bit of multiplier data supplied via a data bus. A multiplication open side block is provided for causing an arithmetic and logic operation means to add data obtained by right-shifting the previous addition result and multiplicand data supplied from the data bus. Operation According to the present invention, the above-described configuration provides a microprocessor having a multiplication aQ that can directly perform multiplication of integer multiplicand data and decimal multiplier data. EXAMPLES Hereinafter, examples of the present invention will be described with reference to the drawings. FIG. 1 shows a block diagram of a fractional multiplier portion of a microprocessor in one embodiment of the present invention. A transfer path for the multiplicand data supplied from the data bus 10 to the multiplicand register 11 to the ALU (arithmetic logic unit 1-) 20 includes a switch group 32 of 16 bits 7) that is opened and closed by the output of the bit AND circuit 31. The output data of the AL'U 20 is returned to the input side of the ALU 20 via the output register 21, the 16-bit feedback bus 22, and the right shifter 33. Further, multiplier data is supplied to one input side of the bit AND circuit 31 from the data bus 10 via the multiplier register 12, and bit position selection data from the multiplication control circuit 35 is supplied to the other input side via the decoder 34. signal is supplied and AL
U20 receives an addition command signal ADD from the multiplication control circuit 36.
is supplied. Note that a bit position selection signal is supplied from the multiplication control circuit 36 to the decoder 34 as numerical data from 0 to 16, and the decoder 34 performs a bit AND operation on the 16-bit data in which the bit position corresponding to this numerical data is set. The signal is sent to the circuit 31. The bit AND circuit 31 performs an AND operation on the multiplier data and the data from the decoder 34, converts the result into 1 bit, and sends it to the switch group 32. In the switch group 32, the output of the bit AND circuit 31 is "1"
If it is "0", it is in a closed state, and on the other hand, if it is "0", it is in an open state. Note that when the switch group 32 is in the open state, zero is supplied to the multiplicand side of the ALU 20. The right shifter 33 shifts the input data in the direction of decreasing value and supplies it to the input side of the ALU 20, but the addition result of the ALU 20 is supplied as the input data. Now, assuming that the multiplicand data is in hexadecimal number C4E20), that is, 20000 in decimal number, and the multiplier data is [8000] in hexadecimal number and 32768 in decimal number, the multiplication control circuit 35 transfers the data to the bit AND circuit 31. Numerical data from 0 to 15 is supplied to the bit discriminator 4Q configured by the decoder 34, and at the same time the AL
When a 16-cycle pulse signal is supplied to U20, the output data Rn of the decoder 34, the output Cn of the bit discriminator 40, and the output data D of the output register 21
n. The output data Sn of the right shifter 33 transitions as follows. It is assumed here that the output register 21 holds the previous value as its output data until the addition operation is completed. (＞・I'p light screen) n Rn Cn Dn
5n(1) Cool) [:o] Co
ooo〕 (oooo〕(2) Cooo2)
[:o) (oooo) Coooo) (3)
[0004:) CD) (0000] (00
00,:] (4) C00O8) (O]
[0000) (00001(5) Coolo
:] Col Coooo) (oooo) (6
) [0020] [0] [0000] [000
0] (7) (0040) [:0] [00
00) (000,0:](3) [:0080)
Co) C00OOI C00OO) (9
) (0100] [:0] [0000] (
0000] αI [0200) Co) (0
000] (0000)Ql) (0400:l
Co) (0000) (0000) (LID
l:0800] CO) (0000] (00
00) α3 [1000:] (0) [00
001 [0000) Q station [20001CO) (
0000) (0000) αQ (4000)
(0) (0000] (0000) αG (a
ooo:l CD (4E20:] Coooo
) The multiplication result is equal to the multiplicand (4E 201:l multiplied by the decimal 1.0.) Similarly, if the multiplicand data is (4E20) in hexadecimal and the multiplier data is (ssss) in hexadecimal, , 21845 in decimal notation, when numerical data from 0 to 16 is supplied from the multiplication control circuit 35 to the bit discriminator 40, and at the same time a 16-cycle pulse signal is supplied to the ALU 20, the decoder 34 output data Rn, bit discriminator 4°chi output Cn, ALU 20 output data Dn, and right shifter 33 output data Sn transition as follows: n Rn Cn Dn 5n (1
) [0001:II (1) C4E20)
(0000)(3) Coooa) [1]
(61As) (1388)(4) [0008]
(0) (30D4) (30D4) (5)
(0010) (1:) (668A) (1
86A) (6) [0020) [:O) [3
345) (3345:](7) [0040)
[1) (67C2] (19A2) (s) (o
oso〕Co〕[:33E1] (33E1] (9)
Co1oo) [:D [6810] (19F
'o] α0 [0200) CO) (3408
) (3408]1.11) [0400) [
1) (6824] CIAO4) (2) Coao
o] (0) (3412) [3412] α3 (1
0001 [1) [6829) (IAO9) (1
, Ill [2000] [0] [5414] [6414]
85 [4000) CD C682A] (
IAOA) Qe Caooo) (01(3415
) (3415) In this case, the multiplication result is 1 in decimal
3333, and the decimal 0.6 is added to the multiplicand C4E20]
1, that is, equal to the product multiplied by (20ωq/32767). In the end, in the decimal multiplier shown in FIG. 1, the multiplication result A is calculated from the multiplicand data value D and the multiplier data value M as follows. D = dls・215+d14・214+...+d
2-22+d1-21+dO-20-=-...(1
) M= ml 5・215+ m14-2” 4+-・
・+ml・2 +m1・2 10-・20 ・・・
(2) Here, dls and m1s are multiplicand data D, respectively. In the most significant focus value of the multiplier data M, do and mo are the values of the least significant bit of the multiplicand data D9 and the multiplier data M, respectively. Addition result a when the first addition operation is completed
O is aO=ω・D・・・・・・・・・
・(3) When the second addition operation is completed, the addition result a1 is O a1=m1・D+− When the third addition operation is completed, the addition result a2 is: a2=D threat m2− Therefore, in this way, the decimal multiplier of FIG. 1 can easily perform multiplication of integer multiplicand data and decimal multiplier data. In addition, in conventional integer multiplication, when 16-bit data is multiplied, 32 bits are required to store the result.
It requires a bit register or memory area, but
In the decimal multiplier of FIG. 1, overflow does not occur unless the value of the multiplier data exceeds 1, so the number of bits required to store the multiplication result can be reduced. Now, FIG. 2 shows another embodiment of the present invention. In the decimal multiplier shown in FIG. A right shift command signal consisting of a 16-cycle pulse train, which is the same as the addition command signal ADD supplied to the ALU 20, is supplied from the multiplication control circuit 36 to the shift register 36, and the switch group is shifted by the shift carry from the shift register 36. 32 is opened and closed. Note that in this embodiment, both the multiplicand data and the multiplier data are 1.
Although the case of 6 bits has been explained, it is not necessary that the two bits have the same number of bits. For example, if the multiplier data is 8 pits in FIG.
It is sufficient to generate a pulse train of cycles, in which case the multiplication is completed more quickly. Furthermore, although multiplicand data and multiplier data have been distinguished for convenience of explanation, it is clear from equations (1) to (6) that there is no problem even if they are interchanged. By the way, the ALU 20 shown in FIGS. 1 and 2 can use what is originally provided in a microprocessor, and the output register 21 . The same applies to the multiplicand register 112 and the multiplier register 12. Therefore, the first
Regarding the illustrated embodiment, bit AND circuit 31. Switch group 32° right shifter 33. Multiplication control block 30'z configured by decoder 342 multiplication control circuit 36
Just add it to the core of the microprocessor. In the embodiment of FIG. 2, the switch group 32. Right shifter 332 Multiplication control circuit 36. The shift register 36 constitutes a multiplication control block 30 similar to that shown in FIG. As is clear from the above description, the microprocessor having a decimal multiplier according to the present embodiment includes an ALU 20 that performs addition and subtraction of data supplied via the data bus 1o, and multiplier data supplied via the data bus 1o. The multiplication control block determines the value of each bit, and uses the result to cause the ALU to add the data obtained by shifting the previous addition result to the right and the multiplicand data supplied from the data bus. , a direct multiplication of the integer multiplicand data and the decimal multiplier data can be performed, which eliminates the dog effect. Further, in this embodiment, a bit discriminating means (bit discriminating section 4o or shift register 36) for discriminating the value of each bit of multiplier data, and an AL from the data bus according to an output from the bit discriminating means.
Switch means (switch group 32) that opens and closes the transfer path of multiplicand data to tJ 20, and the output of ALU 20
Feedback means (feedback bus 22) returns to the input side of U20, sends a predetermined number of bit position selection signals to the bit discrimination means, and sends an addition command signal to the ALU2.
Since it is constituted by the multiplication control circuit 36 that sends out 0, the entire decimal multiplication function can be easily realized. Effects of the Invention As described above, according to the present invention, multiplication of multiple multiplicand data and decimal multiplier data can be directly executed with a simple configuration, and the execution speed can be faster than that of a multiplier that handles only integers. Can be configured at low cost.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a decimal multiplier showing one embodiment of the present invention, Fig. 2 is a block diagram of a decimal multiplier showing another embodiment of the invention, and Fig. 3 requires a decimal multiplier. FIG. 2 is a block diagram of a control device. 10...Data bus, 2o...8 LU, 2
0...Return bus, 3o...Multiplication collateral block, 32...Switch group, 33...
・Right shifter, 35... Multiplication control circuit, 36...
...Shift register, 4o...Bit discrimination section.

Claims (3)

[Claims] (1) Arithmetic and logic operation means for adding and subtracting data supplied via the data bus, and determining the value of each bit of the multiplier data supplied via the data bus, and based on the result, the previous addition result A microprocessor having a decimal multiplier comprising a multiplication control block for causing the arithmetic and logic operation means to add right-shifted data and multiplicand data supplied from the data bus. (2) bit discrimination means for discriminating the value of each bit of multiplier data, and according to the output from the bit discrimination means,
switch means for opening and closing a transfer path for multiplicand data from the data bus to the arithmetic and logic operation means; feedback means for returning the output of the arithmetic and logic operation means to the input side of the arithmetic and logic operation means; and a predetermined number of bits. 2. A microprocessor having a decimal multiplier according to claim 1, further comprising a multiplication control circuit for sending a position selection signal to said bit discrimination means and for sending an addition command signal to said arithmetic and logic operation means. (3) bit discrimination means for discriminating the value of each bit of multiplier data, and according to the output from the bit discrimination means,
switch means for opening and closing a transfer path for multiplicand data from the data bus to the arithmetic and logic operation means; and a switch means for shifting the output data of the arithmetic and logic operation means in a direction in which the value thereof decreases and supplying the output data to the arithmetic and logic operation means. 2. The decimal multiplication device according to claim 1, further comprising a shifter and a multiplication control circuit for sending a predetermined number of bit position selection signals to said bit discrimination means and for sending an addition command signal to said arithmetic and logic operation means. A microprocessor with a device.