JPS63298526A - Floating decimal point adder - Google Patents

Abstract

PURPOSE:To curtail the required quantity of a shift function by providing the shifting means of a mantissa part for sharing the two shifts of an alingnment shift and a normalize shift by a storing means for temporarily storing the output of an adding means disposed in the post step of an adding means for adding the mantissa. CONSTITUTION:A barrel shifter 21 shared for the alingnment shift and the normalized shift shifts rightward in the alignment shift and leftward in the normalized shift, however, since the shifting direction of the barrel shifter is one direction, the mantissa before the addition and the mantissa after the addition are inputted in an opposite direction. A register 22 for latching the added output of a mantissa adder 7 and feeding the output to a priority encoder 9 and the barrel shifter 21 is provided. Namely, after data after the mantissa is added is maintained, it is inputted to shift the using timing in the pipe lines of the first step and the second step of the barrel shifter 21 and execute the normalized shift. Thereby, the quantity of the hardware can be saved.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a floating point addition device for adding binary numbers in a pipelined floating point representation used for numerical calculations in a computer.

(Prior Art) There are many ways to represent binary numbers for performing numerical calculations in computers, but it is convenient to use binary numbers expressed as floating point numbers in scientific calculations. The IEEE floating point arithmetic standard has been established and used as a method for displaying floating point numbers. This single-precision display method has a configuration as shown in FIG. In the figure, 31 is a sign part representing a positive or negative sign, and 1+0 is positive.
++.

1" is given to the negative value. 32 is the exponent part, which is made up of 8 bits and is expressed as "2 days - 127'. 33 is the mantissa part consisting of 23 bits, the decimal point is on the left end, and the integer 1 is always present.
It is not displayed because it always exists. The number n is expressed by the following formula.

n-8-'2ε-127, (1, r) where S: sign E: finger full f: mantissa Therefore, when adding two numbers with an adder (including subtraction), the exponent part and mantissa part If the exponents are different, perform digit alignment (alignment shift), then add the mantissas, and perform addition 11.
1 E E E calculation standard Performs a normalization shift of the mantissa for display. As this floating point adder, a Vibrine type floating point adder is used because if the calculation is divided into two stages, the calculation speed will be approximately doubled when processing a large amount of data.

FIG. 4 is a block diagram of a conventional two-stage pipeline type floating point adder.

In the figure, the two-person operand AI, A2 (assumed to be <A1>A2) arriving from the data bus is separated into an exponent part and a mantissa part, and the exponent part of operand A1 is latched (A2).
1. The exponent part of operand A2 is latch (B)2. The mantissa part of operand A1 is latch (C)3. The mantissa part of operand A2 is latched in each latch (D)4. 5 is operand A of the output of latch (A) 1 and latch (B) 2
1 and the exponent part of operand A2, and calculates the shift number of the mantissa based on the difference in the exponents.The shift number calculation unit inputs the calculated shift number to the barrel shifter 6. The barrel shifter 6 performs an alignment shift to shift the mantissa of the smaller operand A2 among the outputs of the latch (C) 3° and the latch (D) 4 to the right by the shift number output from the shift number calculation unit 5. The mantissa of operand A1 and the shifted mantissa of operand A2 are added in mantissa adder 7. 8 is latch (A)1. This is an exponent selection section that selects and outputs the exponent of operand A1, which in this case is the larger output from latch (B)2. As described above, from the latch (A) 1 to the index selection section 8 is the first stage of the pipeline.

Entering the second stage of the pipeline, 9 is a priority encoder that detects the position of the first "1" from the output of the operation result of the mantissa adder 7, and its output is sent to the barrel shifter 10 and the exponential shift counter 11. is input. The barrel shifter 10 normalizes the mantissa by shifting it to the left based on the output of the priority encoder 9. The shift direction is always to the left. The exponent shift counting section 11 decrements the exponent by a number equal to the number of shifts of the mantissa based on the output signal of the priority encoder 9. This index value is judged by the output judgment section 12 to see if there is any digit confusion. The output determination unit 12 also determines when the output is 0. Reference numeral 13 denotes an output judgment section consisting of an adder including a register, which temporarily holds the mantissa of the output of the barrel shifter 10 in a register, rounds the numerical value, and judges overflow. It is combined with the exponent of the output of 12 and output to the data bus.

(Problem to be Solved by the Invention) The above adder supports the 32-pit single-precision floating point data format of the rEEE performance standard, has the possibility of shifting 23 bits of the mantissa, and has the possibility of shifting 23 bits of the mantissa. Since it had two shifters, the hardware for the barrel shifter was quite large.

The present invention has been made in view of the above points, and its purpose is to realize a pipelined floating point adder in which the number of layers required for the largest shift function in hardware is reduced from two to one. be.

(Means for Solving the Problems) The present invention, which solves the above problems, separates the exponent part and the mantissa part of two operands, shifts the alignment of the mantissa part by the difference between the exponent parts, and converts the mantissa part into In a Vibration type floating point adder that normalizes and shifts the parts after addition and outputs the combination, a storage means for temporarily holding the output of the addition means provided after the addition means for adding the mantissa, and a storage means for temporarily holding the output of the addition means for adding the mantissa; The present invention is characterized in that it includes a mantissa shift means that is capable of performing two shifts: a shift and a normalization shift.

(Operation) The data after mantissa addition is held in the storage means and then inputted to the shift means that shifts the mantissa part of the input operand by 7 lines, and the data is inputted to the first and second stage pipelines of the shift means. Normalize shift is performed by shifting the timing of use.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. In the figure, parts equivalent to those in FIG. 4 are given the same reference numerals. In the figure, 21 is a barrel shifter used for both alignment shift and normalization shift.Alignment shift shifts to the right and normalization shift shifts to the left.However, since the barrel shifter shifts in one direction, the mantissa before addition The mantissa after addition is input in the opposite direction. 22 is a register that latches the addition output of the mantissa adder 7 and sends the output to the priority encoder 9 and the barrel shifter 21. Next, the operation of the embodiment configured as described above is explained in the time chart of FIG. This will be explained with reference to.

FIG. 2 shows a flowchart of arithmetic processing and its relationship with time. The clock is the master clock divided by 6 and T
The timing of the operation from o to T5 is created.

First, at the timing of the end of TO, operand △1 latches the exponent in latch (A) 1 and the mantissa in latch (C) 3, and at the timing of the end of T1, operand A2 latches the exponent in latch (B) 2. The mantissa is latched in (D>4. Here, for convenience of explanation, it is assumed that △1>A2. During timing T2, the shift number calculation unit 5 transfers the exponent of operand A1 from latch (A)1 to latch (B). )2, the exponent of operand A2 is input and compared, the larger exponent of operand A1 is determined, and the difference is calculated. During timing T3, the shift number calculation unit 5 sends information on the magnitude of the exponent to the barrel shifter 21, and inputs the mantissa of the smaller operand A2 from the latch (D) 4 to the barrel shifter 21. The larger operand A1 during timing T4
The mantissa is sent from the latch (C) 3 to the mantissa adder 7, where it is added to the mantissa of the operand A1 which has been aligned and shifted by the barrel shifter 21. At the end of T4, the addition result in the mantissa adder 7 is latched into the register 22. During the next timing T5, the register 22 outputs the addition result to the priority encoder 9 and barrel shifter 21. When entering the second stage of the vibration line, during timing To, the priority encoder 9 calculates the number of shifts to normalize and shift the leading "1". During timing T1, the mantissa is subjected to a normal Rice shift if necessary in the barrel shifter 21, and the mantissa of the operation result is normalized. At this time, the exponent shift counting unit 11 similarly receives the shift number of the mantissa shift from the priority encoder 9 and subtracts the exponent by the shift number. At the end of T1, the register of the output determination unit 13 latches the output of the barrel shifter 21. During the next timing 2 to T4, the output determination unit 12 determines whether there is an overflow in the exponent, and the output determination unit 13 receives the mantissa from the register and performs rounding if necessary.
Determines overflow, etc.

At timing T5, the output of the output determining section 13 is combined with the output of the output determining section 12 and output to the data bus.

During the above operation, the barrel shifter 21 shifts the mantissa of the small operand at timing 3 in the operation of the first stage of the vibe line, and receives the addition result at timing T5.

Further, at timing T1 of the second stage of the vibe line, the barrel shifter 21 normalizes and shifts the addition result. Therefore, the next operand is input and the vibe line 1
Even if the operation of the second step is performed, the timing is different from the timing when the barrel shifter 21 is used, and there is no overlap.

As explained above, even if the next operand is input when the addition operation of the first input operand advances to the second stage of the vibe line, there will be no confusion because the timing of using the barrel shifter 21 is different. . Therefore, according to this embodiment, only one barrel shifter is required even though addition is performed using a two-stage vibrating system, and the amount of hardware can be reduced.

(Effects of the Invention) It is now possible to perform floating point addition in a two-stage pipeline system using one barrel shifter, which has a great practical effect.

[Brief explanation of drawings]

Fig. 1 is a block diagram of the configuration of an embodiment of the present invention, Fig. 2 is a time chart of the operation of the device of the embodiment, and Fig. 3 is an IEE
FIG. 4, which is a diagram of the structure of numbers according to the E floating point arithmetic standard, is a block diagram of the structure of a conventional floating point addition device. 1.2.3.4... Latch 5... Shift number calculation section 6.10.21... Barrel shifter 7... Mantissa adder 8... Exponent selection section 9...
・Priority encoder 11...exponential shift counting section

Claims (1)

[Claims] In a pipelined floating point adder that separates the exponent and mantissa parts of two operands, shifts the alignment of the mantissa parts by the difference between the exponent parts, normalizes and shifts the mantissa parts after addition, and outputs the combination. A storage means for temporarily holding the output of the addition means provided after the addition means for adding the mantissa; and a storage means for temporarily holding the output of the addition means for adding the mantissa; A floating point addition device comprising: a shift means.