JPH01100626A - Decimal fraction multiplier - Google Patents

Abstract

PURPOSE:To directly multiply an integer by a decimal fraction by being equipped with a bit discriminating means, a switching means to be operated with an output, a feedback means of an adder, and a multiplication control circuit. CONSTITUTION:A switch group to be operated by the output of a bit AND circuit 51 of a bit discriminating block 10 is provided at a multiplicand transferring path to an adder 50, and the output of the adder is fed back through a feedback bus 60 and a right shifter 53 on an input side. A bit position selective signal is supplied from a multiplication control circuit 55 through a multiplier and a decoder 54 to the AND circuit 51, and an adding instruction ADD is also given to the adder 50. The AND circuit 51 opens a switch group 52 at the time of '0', and a zero is supplied on the multiplicand side of the adder 50. Since the value of the multiplier is successively discriminated from the highest-order bit in units of a bit, the bit position selective signal is given for the prescribed times set beforehand, and the multiplier in the adder is controlled, the integer can be directly multiplied by the decimal fraction.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention provides a decimal multiplier suitable for being installed in a microprocessor for controlling equipment.

Conventional technology Many modern microprocessors are equipped with multiplication instructions; general-purpose microprocessors are equipped with integer multipliers, and signal processors used for signal processing and equipment control are equipped with floating-point multiplication instructions. equipment is installed.

Problems to be Solved by the Invention Now, if we consider the case where the main part of a motor rotational speed control device as shown in FIG. is output, compensated in the frequency domain by the digital filter 2, and then converted into a direct current by the DA converter 3. By the way, as is well known, this type of digital filter generally handles decimal numbers in multiplication. On the other hand, what is input to the digital filter 2 is integer error detection data. Therefore, it would be convenient if a microprocessor had a multiplier that could perform multiplication between an integer multiplicand and a decimal multiplier, but in reality, a multiplier that handles only integers or a large floating-point multiplier is required. equipment is used.

Means for Solving the Problems In order to solve the above-mentioned problems, the decimal multiplier of the present invention includes a bit discrimination means for discriminating the value of multiplier data in units of bits, and a response to the output from the bit discrimination means. switch means for opening and closing a transfer path for the multiplicand data to the adder; feedback means for returning the output of the adder to the input side of the adder; and sending a bit position M selection signal to the bit discrimination means. , a multiplication control circuit that sends an addition command signal to the adder.

Operation According to the present invention, the above-described configuration provides a multiplier that can directly perform multiplication of integer multiplicand data and decimal multiplier data.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 shows a block diagram of a fractional multiplier in one embodiment of the present invention. In Figure 1,
Since the arithmetic and logic operation unit 50 is used as an adder, it will be described as the adder 50 from now on. A 16-bit switch group 52 is provided on the transfer path of the multiplicand data to the adder 50, which is opened and closed by the output of the bit AND circuit 51, and the output data of the adder 50 is transferred to the 16-bit feedback bus. 60 and the right shifter 53, it is returned to the input side of the adder 50. Further, multiplier data is supplied to one input side of the bit AND circuit 51,
On the other input side, a multiplication control circuit 5 is connected via a decoder 54.
A bit position selection signal from the adder 5 is supplied to the adder 5.
0 is supplied with an addition command signal ADD from the multiplication control circuit 55. Note that the focus position selection signal is supplied from the multiplication control circuit 55 to the decoder 54 as numerical data from 0 to 15, and the decoder 54 receives 16-bit data in which the bit position corresponding to this numerical data is set. It is sent to the bit AND circuit 51. The bit AND circuit 51 outputs multiplier data and the decoder 54.
It performs an AND operation with the data from , converts the result into 1 bit, and sends it to the switch group 52 . The switch group 52 is in a closed state when the output of the bit AND circuit 51 is "1", and on the other hand, is in an open state when it is '0°.

Note that when the switch group 52 is in the open state,
Zero is supplied to the multiplicand side of the adder 50.

The right shifter 53 shifts the input data in the direction of decreasing its value and supplies it to the input side of the adder 50, and the addition result of the adder 50 is supplied as the input data.

Now, suppose that the multiplicand data is [4E20] in hexadecimal, that is, 20000 in decimal, and the multiplicand data is [8000] in hexadecimal, 32768 in decimal. When numerical data from 0 to 15 is supplied to the adder 50 and at the same time a 16-cycle pulse signal is supplied to the adder 50, the output data Rn of the decoder 54, the output Cn of the bit discrimination block 10, the adder 50 Output data Dn
, the output data Sn of the right shifter 53 transitions as follows. It is assumed here that the adder 50 retains the previous value as its output data until the addition operation is completed.

nRn'Cn Dn Sn■ [000
1] [0] Co 000 EO 000 ■ [
0002] [0] [0000] [0000
]■ [0004] [0] [0000 ko [0
000] ■ [0008] [0] [0000]
[0000]■[0010ko[0][0000][0
0001■ [0020] [0] [0000]
[0000] ■ [0040] [0] [0
0003 [0000] ■ [0080] [0]
[0000] [0000ko■ [0100F [
0] [0000] [0000ko@l[0200
][0ko[0000][00001■ [0400]
[0] [0000 ko [0000] @ [08
001 [0] [0000 ko [0000] @ [10
00 pieces [0] [0000] [0000 pieces■
[2000 pieces [0 pieces] [00001[0000]■
[4000] [0] [0000] [000
01@[8000] [1] [4E20] [
0000] The multiplication result is the multiplicand [4E20] and the decimal 0
．． It is equal to 1 multiplied by 1.

Similarly, if the multiplicand data is [4E20] in hexadecimal and the multiplier data is [5555 in hexadecimal and 21845 in decimal, then When the numerical data up to and at the same time a 16-cycle pulse signal is supplied to the adder 50, the output data Rn of the decoder 54, the output Cn of the bit discrimination block 1o, the output data Dn of the adder 50, The output data Sn of the right shifter 53 changes as follows.

n Rn Cn Dn Sn
■[0001] [1] [4E20] [00
001■ [0002ko [0] [2710]
[2710] ■ [0004] [1 piece [61A8
] [1388 ko ■ [0008] [0] [3
0D4] [30D4]■[0010] [1]
[668A] [186A] ■ [0020F [
01[3345] [3345]■ [0040ko
[1] [67C2] [19A2] ■ [018
0] [01[33E1] [33E1]■ [0
100 pieces [1] [6810 pieces [19FO
] [Phase] [0200] [0] [3408]
[3408] @ [0400] [1] [6824
Ko EIAO4ko@[08001[0ko [3412
] [3412 pieces ■ [1000] [1] [
6829] [IAO9ko■ [2000] [0
1[3414] [3414ko@[40001[1F
[682A] [IAOA co[phase] [80
00] E, 0 E3415E [3415] The multiplication result in this case is 13333 in decimal, and the multiplicand [4E20] is added to the decimal 0.61, that is, (20
000/32767).

In the end, in the decimal multiplier shown in FIG. 1, the multiplication result A is calculated from the multiplicand data value D and the multiplier data value M as follows.

D = d 15.2" + d 14.2" +...
...+ d 2,2g + 1.21 + d O,
2° ・Old...(1) M=m15.215+m1
4.2'4+--10d2.2"+m1.2'+m0.2
° ・Old...(2) Here, d15. m15 is the most significant bit value of multiplicand data D9 and multiplier dek M, respectively, and is dQ.

mO is the value of the least significant bit of multiplicand data D5 and multiplier data M, respectively. When the first addition operation is completed,
The addition result aO is a O=m O・D・Old・(3
The addition result a1 at the time when the 12th addition operation is completed is al-ml D+ − = m l−D +m O・---(The addition result a2 at the time the 413th addition operation is completed is a2=D−m2+− ・・・・・・(5) Therefore, 2° 21 0 mO・□ ・・・・・・(6) −M 8−□ ・・・・・・(7) I
5. In this manner, the decimal multiplier of FIG. 1 can easily perform multiplication of integer multiplicand data and decimal multiplier data. In addition, in conventional integer multiplication, when 16-bit data is multiplied, 3 bits are required to store the result.
Although a 2-bit register or memory area is required, in the decimal multiplier shown in Figure 1, overflow does not occur unless the multiplier data value exceeds 1, so the number of bits required to store the multiplication result is It also requires less.

Now, FIG. 2 shows another embodiment of the present invention. In the decimal multiplier shown in FIG. 56 is used, and a right shift command signal consisting of a pulse train of 16 cycles, which is the same as the addition command signal ADD supplied to the adder 50, is supplied from the multiplication control circuit 55 to the shift register 56, and a shift carry from the shift register is supplied. The switch group 52 is opened and closed.

Incidentally, in the embodiments shown in FIGS. 1 and 2, the bit values are determined in order from the least significant bit of the multiplier data, but as shown in FIG. It is also possible to configure the bit values to be determined in order from the most significant bits. That is, in the decimal multiplier of FIG. 3, the multiplicand data is supplied to the switch group 52 via the shift register 57, and the addition command signal ADD consisting of a 16-cycle pulse train is sent from the multiplication control circuit 55 to the adder 50. The shift registers 56 and 57 are supplied with a left shift command signal SHL and a right shift command signal SHR, respectively. In the decimal multiplier of FIG. 3, in the first cycle of the output pulse train of the multiplication control circuit 55, (6)
The first item on the right side of the equation is calculated and the result is returned to one input side of the adder 50, and in the second cycle,
An operation is performed to add the second item on the right side of equation (6) to the operation result of the first cycle. Therefore, even in the decimal multiplier shown in FIG. 3, the result shown in equation (6) can be obtained. However, in the decimal multiplier shown in Figure 3, the operation is the same as calculating each term on the right side of equation (6) individually and adding them together, so errors occur due to loss of digits due to the right shift of the multiplier data. , the precision of multiplication becomes worse.

In the example, both the multiplicand data and the multiplier data are 16.
Although the case of bits has been explained, the two do not necessarily have to have the same number of bits. For example, if the multiplier data in FIG. 1 is 8 bits, it is sufficient to generate an 8-cycle pulse train from the multiplication control circuit 55, and in that case, the multiplication can be performed faster. is completed. Furthermore, although multiplicand data and multiplier data have been distinguished for convenience of explanation, it is clear from equations (1) to (6) that there is no problem even if they are interchanged. Furthermore, as already explained, the adder 50 in FIGS. 1 to 3 is actually an arithmetic and logic operation unit, and if it is a microprocessor, it is equipped to perform normal addition, subtraction, logical operations, etc. ing. The same thing can also be said about registers. Therefore, the decimal multiplier of the present invention makes effective use of the arithmetic and logic unit and registers of the microprocessor, and performs logical shift functions and multiplication of the contents of the registers, even if it sacrifices the execution speed of multiplication to some extent. The functions of the control circuit 55 can also be realized by a program.

Of course, even in the case of a pure hardware configuration, the number of new hardware elements required for the processor can be considerably reduced.

Effects of the Invention As is clear from the above description, the decimal multiplier of the present invention includes an adder 50 and a bit discrimination means (bit discrimination means) that discriminates the value of multiplier data in bit units starting from the least significant bit or the most significant bit. determination block 10 or shift register 56); switch means (switch group 52) for opening and closing the transfer path of multiplicand data to the adder according to the output from the bit determination means; A multiplication control circuit 55 that sends a predetermined number of bit position selection signals to the bit discrimination means and sends an addition command signal to the adder. Therefore, direct multiplication of integer multiplicand data and decimal multiplier data can be performed, which has a great effect.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a decimal multiplier showing one embodiment of the present invention, FIGS. 2 and 3 are block diagrams of a decimal multiplier showing another embodiment of the present invention, and FIG. 4 is a block diagram of a decimal multiplier showing another embodiment of the present invention. 1 is a block diagram of a control device requiring a multiplier. 10...Bit discrimination block, 50...
・Adder, 52...Switch group, 53...
...Right sister, 55...Multiplication control circuit, 60.
...Return bus. Name of agent: Patent attorney Toshio Nakao Haka 1 person 2nd % 5. Figure 3

Claims (2)

[Claims] (1) An adder, a bit discrimination means for discriminating the value of multiplier data in bit units starting from the least significant bit or the most significant bit, and the multiplicand data is sent to the adder according to the output from the bit discrimination means. switch means for opening and closing the transfer path; feedback means for returning the output of the adder to the input side of the adder; and a feedback means for sending a predetermined number of bit position selection signals to the bit discrimination means, as well as an addition command signal. A decimal multiplier comprising a multiplication control circuit for sending data to the adder. (2) an adder, a bit discriminator that discriminates the value of the multiplication data in bit units starting from the least significant bit and the most significant bit, and transfer of the multiplicand data to the adder in accordance with the output from the bit discriminator. a right shifter that shifts the output data of the adder in a direction in which its value decreases and supplies it to the adder; and a predetermined number of bit position selection signals to the bit discrimination means. A decimal multiplier comprising a multiplication control circuit that sends out an addition command signal to the adder.