JPH01227475A - Amorphous silicon thin-film transistor - Google Patents
Amorphous silicon thin-film transistorInfo
- Publication number
- JPH01227475A JPH01227475A JP5390088A JP5390088A JPH01227475A JP H01227475 A JPH01227475 A JP H01227475A JP 5390088 A JP5390088 A JP 5390088A JP 5390088 A JP5390088 A JP 5390088A JP H01227475 A JPH01227475 A JP H01227475A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- film
- amorphous silicon
- shaped
- film transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910021417 amorphous silicon Inorganic materials 0.000 title claims abstract description 21
- 239000010409 thin film Substances 0.000 title claims abstract description 5
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 claims abstract description 16
- 238000005979 thermal decomposition reaction Methods 0.000 claims description 4
- 239000010408 film Substances 0.000 abstract description 27
- 238000000034 method Methods 0.000 abstract description 21
- 238000002230 thermal chemical vapour deposition Methods 0.000 abstract description 11
- 238000004519 manufacturing process Methods 0.000 abstract description 9
- 239000000758 substrate Substances 0.000 abstract description 7
- 239000011521 glass Substances 0.000 abstract description 5
- 238000002161 passivation Methods 0.000 abstract description 5
- 238000000059 patterning Methods 0.000 abstract description 4
- 230000007774 longterm Effects 0.000 abstract description 2
- 239000007789 gas Substances 0.000 description 6
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 4
- 230000006866 deterioration Effects 0.000 description 4
- 239000001257 hydrogen Substances 0.000 description 4
- 229910052739 hydrogen Inorganic materials 0.000 description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000011109 contamination Methods 0.000 description 3
- 239000000843 powder Substances 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 238000007865 diluting Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000001307 helium Substances 0.000 description 2
- 229910052734 helium Inorganic materials 0.000 description 2
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 229910016006 MoSi Inorganic materials 0.000 description 1
- 229910004205 SiNX Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052754 neon Inorganic materials 0.000 description 1
- GKAOGPIIYCISHV-UHFFFAOYSA-N neon atom Chemical compound [Ne] GKAOGPIIYCISHV-UHFFFAOYSA-N 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、アモルファスシリコン(以下a−5t トい
う、を用いた薄膜、、アジ8月以下4.という)に関す
るものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a thin film using amorphous silicon (hereinafter referred to as A-5T).
近年、a−5iを用いたTPTは、ガラス等の安価な基
板を使うことができ、また製造工程が少ないこと、など
の理由により、液晶パネル等表示装置の駆動素子として
研究開発が活発に行なわれている。In recent years, TPT using a-5i has been actively researched and developed as a driving element for display devices such as liquid crystal panels because it can use inexpensive substrates such as glass and requires fewer manufacturing steps. It is.
第1図にa−5t TFTの最も典型的な例を断面図で
示す。本JT (7)製造方法、よ、ガ、8基板、上、
ゲート電極2を形成し、その上にゲート絶縁膜3を形成
し、さらにa−5iの1層4及び1層5を連続形成する
。しかる後に所定のパターニングにより、a−5tパタ
ーン、及びソース、ドレイン電極グターン6を形成する
。最後にパッシベーション膜7を形成する。このような
TPTの製造において重要な点は、すぐれたオンオフ比
(オン電流とオフ電流の比)を有し、かつ長時間にわた
って安定に動作するものが、歩留り良く得られることで
ある。活性層であるa−3iの1層とオーミックコンタ
クト層であるa−Siのn層の形成方法としては、一般
には、プラズマCvD法が広く用いられ企業化されてい
る。FIG. 1 shows a cross-sectional view of the most typical example of an a-5t TFT. This JT (7) Manufacturing method, 8th board, top,
A gate electrode 2 is formed, a gate insulating film 3 is formed thereon, and 1 layer 4 and 1 layer 5 of a-5i are successively formed. Thereafter, an a-5t pattern and source and drain electrode patterns 6 are formed by predetermined patterning. Finally, a passivation film 7 is formed. What is important in manufacturing such TPTs is that they have a good on-off ratio (ratio of on-off current to off-current) and operate stably over a long period of time with a high yield. As a method for forming an a-3i layer as an active layer and an a-Si n layer as an ohmic contact layer, the plasma CVD method is generally widely used and commercialized.
ところが、プラズマcvn法においては粉の発生が多い
ため、装置の汚染、膜のピンホール等TPTの歩留りに
問題点が生じる。さらにプラズマの制御性に困難がある
ため、荷電粒子の衝突による膜質の劣化、TPTにおけ
る界面状態の劣化等a−Siの物性上による問題点も生
じる。However, since a large amount of powder is generated in the plasma CVN method, problems arise in the yield of TPT, such as equipment contamination and film pinholes. Furthermore, since it is difficult to control the plasma, problems arise due to the physical properties of a-Si, such as deterioration of film quality due to collisions of charged particles and deterioration of the interface state in TPT.
熱CVD法では、他め方法と比較して複雑で高価な装置
を必要とせずに容易に実施が可能である。Compared to other methods, the thermal CVD method can be easily implemented without requiring complicated and expensive equipment.
さらに粉発生が極めて少ないため、装置の汚染も少なく
、また得られた膜もピンホールフリーであり、TPT製
造における歩留りも大幅に向上する等の大きな利点を有
する。Furthermore, since the generation of powder is extremely low, there is little contamination of the equipment, and the obtained film is also pinhole-free, which has great advantages such as greatly improving the yield in TPT production.
ところがモノシランを用いた熱CVD法は550℃以上
の高温を必要とするためa−Stを堆積する基板の材質
が高価な石英ガラス、サファイア等に限定される。さら
に得られたa−3iは550℃以上の高温のためにSi
の微結晶化が生じており、また含有水素量も極めて少な
いために局在準位が多く存在し、その電気的及び光学的
特性は不十分なものであり、TPTの活性層として用い
ることは不可能であった。However, since the thermal CVD method using monosilane requires a high temperature of 550 DEG C. or higher, the material of the substrate on which a-St is deposited is limited to expensive quartz glass, sapphire, or the like. Furthermore, the obtained a-3i has Si due to the high temperature of 550°C or higher.
Microcrystallization has occurred, and since the amount of hydrogen contained is extremely small, there are many localized levels, and its electrical and optical properties are insufficient, so it cannot be used as the active layer of TPT. It was impossible.
本発明はかかる点に鑑みてなされたもので、a−Si
TFTにおいて、良好な特性を有するものを歩留り良く
提供することを目的としている。The present invention has been made in view of this point, and is based on a-Si.
The purpose is to provide TFTs with good characteristics at a high yield.
本発明は、上記の目的を達成するために、a−StTF
Tの製造工程において、ジシランを原料ガスとして用い
た熱CVD法によって得られたa−3i層をTPTに用
いることにより、良好な特性を有するa−St TFT
を歩留り良く製造可能とするものである。In order to achieve the above object, the present invention provides a-StTF
By using an a-3i layer obtained by a thermal CVD method using disilane as a raw material gas in the TPT manufacturing process, an a-St TFT with good characteristics can be obtained.
can be manufactured with high yield.
以下、本発明の詳細な説明する。The present invention will be explained in detail below.
本発明のa−SiTFTは、構造上の従来のもの(第1
図)と変わらない。ガラス等基板l上にcr+ Ti+
MoS i等温体層をゲート電極2として形成し、その
上にゲート絶縁膜3を形成し、さらにジシランを用いた
熱CVO法によりa−Siの1層4及びn層5を連続形
成する。しかる後に所定のパターニングにより、a−3
iパターン、及びCr、八1.Moなどを蒸着し、ソー
ス、ドレイン電極パターン6を形成する。最後に無機膜
あるいは有機膜によりパッシベーション膜7を形成する
。ゲート絶縁膜3は一般に窒化膜、酸化膜等が用いられ
、その形成方法はプラズマCVD法、熱CVD法、光C
VD法等種々の方法がある。The a-Si TFT of the present invention has a conventional structure (first
Figure) is the same. Cr+ Ti+ on a substrate such as glass
A MoSi isothermal layer is formed as a gate electrode 2, a gate insulating film 3 is formed thereon, and a first layer 4 and an n layer 5 of a-Si are successively formed by a thermal CVO method using disilane. After that, by predetermined patterning, a-3
i pattern, and Cr, 81. Source and drain electrode patterns 6 are formed by depositing Mo or the like. Finally, a passivation film 7 is formed using an inorganic or organic film. Generally, a nitride film, an oxide film, etc. are used for the gate insulating film 3, and its formation method is plasma CVD method, thermal CVD method, photochemical vapor deposition method, etc.
There are various methods such as the VD method.
ジシランを用いた熱CVD法によるa−Si層の形成に
おいて、ジシランガスは、無稀釈あるいは稀釈のいずれ
でもかまわない。稀釈する場合、稀釈ガスとして、ヘリ
ウム、ネオン、アルゴン、窒素、水素などの、ジシラン
とは不活性なガスが用いられる。In forming an a-Si layer by thermal CVD using disilane, disilane gas may be undiluted or diluted. When diluting, a gas inert to disilane, such as helium, neon, argon, nitrogen, or hydrogen, is used as the diluting gas.
本発明における熱CVO法の反応圧は、全圧が大気圧以
下のいかなる圧力をも採用できるが、膜厚の均一性が良
いためには減圧が望ましい。全圧が大気圧を越えると、
装置コストが上がり、操作もむずかしくなる。また膜厚
の均一性も悪くなる。As the reaction pressure of the thermal CVO method in the present invention, any pressure whose total pressure is below atmospheric pressure can be adopted, but a reduced pressure is preferable in order to obtain good film thickness uniformity. When the total pressure exceeds atmospheric pressure,
Equipment costs increase and operation becomes difficult. Furthermore, the uniformity of the film thickness also deteriorates.
また、熱分解温度はこの種の熱分解において一般に用い
られる250〜550℃特に300〜500℃が好まし
い。250℃未満では熱分解反応が充分行われず、55
0℃を越えると、微結晶化が生じる等のために充分な特
性を有すa−3iが得られない。Further, the thermal decomposition temperature is preferably 250 to 550°C, particularly 300 to 500°C, which is commonly used in this type of thermal decomposition. If the temperature is lower than 250°C, the thermal decomposition reaction will not take place sufficiently, and the
If the temperature exceeds 0°C, a-3i with sufficient properties cannot be obtained because microcrystalization occurs.
本発明は、TPTのa−Si層の形成において、ジシラ
ンを用いた熱CVD法によることで、モノシランをもち
いた熱CVO法よりも、低温で成膜が可能のため、安価
な基板が使用でき、また装置の耐熱性の低減も可能とな
る。ジシランを用いた熱CVD法において反応温度を2
50〜550℃好ましくは300〜500℃で成膜を行
った場合、得られたa−3iはモノシラを用いた熱CV
O法によるa−5iと比較して格段に優れたものが得ら
れる。The present invention uses a thermal CVD method using disilane to form the a-Si layer of TPT, which allows the film to be formed at a lower temperature than the thermal CVO method using monosilane, so that a cheaper substrate can be used. , it is also possible to reduce the heat resistance of the device. In the thermal CVD method using disilane, the reaction temperature is
When the film is formed at a temperature of 50 to 550°C, preferably 300 to 500°C, the obtained a-3i is subjected to thermal CV using monosilica.
A much superior product can be obtained compared to a-5i produced by the O method.
さらに重要な点は、プラズマCVD法と比較した場合、
粉発生が極めて少ないため、装置の汚染も少なく、また
得られた膜もピンホールフリーであり、TPT装置にお
ける歩留りも大幅に向上する。A more important point is that when compared with the plasma CVD method,
Since the generation of powder is extremely low, there is little contamination of the equipment, and the obtained film is also pinhole-free, which greatly improves the yield in the TPT equipment.
さらには、荷電が存在しないため、膜質の劣化、TPT
における界面状態の劣化等が極めて小さいために、TP
Tとして長時間にわたって安定に動作するものかえられ
る。 、
〔実施例〕
本発明のa−5iTFTは、構造上は従来のもの(第1
図)と変わらない。本発明の実施例を第1図を用いて説
明する。Furthermore, since there is no charge, the deterioration of film quality and TPT
Since the deterioration of the interface state in TP is extremely small,
You can change the T to one that operates stably over a long period of time. , [Example] The a-5i TFT of the present invention is structurally similar to the conventional one (first
Figure) is the same. An embodiment of the present invention will be described with reference to FIG.
叉旌開
ガラス基板1上にCrをゲート電極2として形成し、そ
の上にゲート絶縁膜3を形成し、さらにジシランを用い
た熱CVO法によりa−Siの1層4及び1層5を連続
形成する。しかる後に所定のパターニングにより、a−
3iパターン、及びANを蒸着し、ソース、ドレイン電
極パターン6を形成する。最後に無機膜によりパッシベ
ーション膜7を形成する。ゲートwA縁膜3はプラズマ
CVD法による窒化膜SiNxを用いた。Cr is formed as a gate electrode 2 on a split glass substrate 1, a gate insulating film 3 is formed thereon, and one layer 4 and one layer 5 of a-Si are successively formed by a thermal CVO method using disilane. Form. Thereafter, by predetermined patterning, a-
3i pattern and AN are deposited to form source and drain electrode patterns 6. Finally, a passivation film 7 is formed using an inorganic film. For the gate wA edge film 3, a nitride film SiNx formed by plasma CVD method was used.
本発明の実施例におけるa−3iの1層4はジシランを
用いた熱CVD法により以下の条件で形成される。ジシ
ランガスの流量I Qcc/m1n−、稀釈ヘリウム流
量50 cc/sin 、反応全圧200Torrであ
る。形成温度は450℃である。 a−3iの1層5は
、上記の条件でさらにPH3(Heベース1%)流量5
0cc/sinを加えることにより形成される。One layer 4 of a-3i in the embodiment of the present invention is formed by thermal CVD using disilane under the following conditions. The flow rate of disilane gas was IQcc/mln-, the flow rate of diluted helium was 50 cc/sin, and the total reaction pressure was 200 Torr. The formation temperature is 450°C. In the first layer 5 of a-3i, the PH3 (He base 1%) flow rate 5 was added under the above conditions.
It is formed by adding 0cc/sin.
を較■
a−5iの1層4及び1層5をプラズマCVD法により
形成した他は実施例と同じようにしてa−5i TFT
を製造した。a−Siは以下の条件で形成される。モノ
シランガス(水素ベースlO%)の流量100cc/l
l1ns反応圧Q、’l Torr、、高周波電力5W
である。形成温度は300℃である*a−5in層5は
、上記の条件でさらにPH3(水素ベース0.1%)流
量100 cc/sinを加えることにより形成される
。Comparison ■A-5i TFT
was manufactured. a-Si is formed under the following conditions. Flow rate of monosilane gas (hydrogen base 1O%) 100cc/l
l1ns reaction pressure Q, 'l Torr, high frequency power 5W
It is. The formation temperature is 300° C. *The a-5in layer 5 is formed under the above conditions by further adding a PH3 (hydrogen base 0.1%) flow rate of 100 cc/sin.
実施例、比較例において製造したa−SiTFTの特性
を測定し、結果を第1表に示した。The characteristics of the a-SiTFTs manufactured in Examples and Comparative Examples were measured, and the results are shown in Table 1.
第1表から明らかなように、ジシランを用いた熱CVD
法によって得られたa−5i層をTPTに用いることに
より、プラズマCVD法と比較して、オンオフ比は2X
10’から3×10−と10”以上の向上がみられ、ま
たオン電流の保持率も0.90から0.98へとばぼ1
に近いまでの向上がみられた。As is clear from Table 1, thermal CVD using disilane
By using the a-5i layer obtained by the method for TPT, the on-off ratio is 2X compared to the plasma CVD method.
There was an improvement of more than 10" from 10' to 3 x 10-, and the on-current retention rate increased from 0.90 to 0.98.
An improvement close to .
また良品率も0.70から0.97へと大幅な向上がみ
られた。In addition, there was a significant improvement in the non-defective product rate from 0.70 to 0.97.
以上述べたように本発明によれば、ジシランを用いた熱
CVD法によって得られたa−3i層をTFTに用いる
ことにより、TFTの電気特性や長期安定性を大幅に改
善させることができ、また製造における歩留りも大幅に
向上できる。このため、各種表示装置の駆動素子等に広
く利用が可能となり、実用上の効果は大きい。As described above, according to the present invention, by using an a-3i layer obtained by a thermal CVD method using disilane in a TFT, the electrical characteristics and long-term stability of the TFT can be significantly improved. Furthermore, the yield in manufacturing can be significantly improved. Therefore, it can be widely used as driving elements of various display devices, and has great practical effects.
第1図は、本発明のa−Si TPTの典型例を示す断
面図である。
l・・・ガラス基板、2・・・ゲート電極、3・・・ゲ
ート絶縁膜、4・・・アモルファス99371層(活性
層)、5・・・アモルファスシリコンn層(オーミック
コンタクト層)、6・・・ソース、ドレイン電極、7・
・・パッシベーション膜。
出 願人 昭和電工株式会社
猟1図FIG. 1 is a cross-sectional view showing a typical example of the a-Si TPT of the present invention. l... Glass substrate, 2... Gate electrode, 3... Gate insulating film, 4... Amorphous 99371 layer (active layer), 5... Amorphous silicon n layer (ohmic contact layer), 6... ...source, drain electrode, 7.
...Passivation film. Applicant: Showa Denko Co., Ltd.
Claims (1)
モルファスシリコン層を、ジシランガスの熱分解により
形成することを特徴とするアモルファスシリコン薄膜ト
ランジスタ。An amorphous silicon thin film transistor characterized in that an amorphous silicon layer is formed by thermal decomposition of disilane gas.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5390088A JPH01227475A (en) | 1988-03-07 | 1988-03-07 | Amorphous silicon thin-film transistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5390088A JPH01227475A (en) | 1988-03-07 | 1988-03-07 | Amorphous silicon thin-film transistor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01227475A true JPH01227475A (en) | 1989-09-11 |
Family
ID=12955595
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5390088A Pending JPH01227475A (en) | 1988-03-07 | 1988-03-07 | Amorphous silicon thin-film transistor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01227475A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5055899A (en) * | 1987-09-09 | 1991-10-08 | Casio Computer Co., Ltd. | Thin film transistor |
US5166085A (en) * | 1987-09-09 | 1992-11-24 | Casio Computer Co., Ltd. | Method of manufacturing a thin film transistor |
US5229644A (en) * | 1987-09-09 | 1993-07-20 | Casio Computer Co., Ltd. | Thin film transistor having a transparent electrode and substrate |
US5327001A (en) * | 1987-09-09 | 1994-07-05 | Casio Computer Co., Ltd. | Thin film transistor array having single light shield layer over transistors and gate and drain lines |
-
1988
- 1988-03-07 JP JP5390088A patent/JPH01227475A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5055899A (en) * | 1987-09-09 | 1991-10-08 | Casio Computer Co., Ltd. | Thin film transistor |
US5166085A (en) * | 1987-09-09 | 1992-11-24 | Casio Computer Co., Ltd. | Method of manufacturing a thin film transistor |
US5229644A (en) * | 1987-09-09 | 1993-07-20 | Casio Computer Co., Ltd. | Thin film transistor having a transparent electrode and substrate |
US5327001A (en) * | 1987-09-09 | 1994-07-05 | Casio Computer Co., Ltd. | Thin film transistor array having single light shield layer over transistors and gate and drain lines |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS633463A (en) | Manufacture of thin film transistor | |
JP2001274404A (en) | Thin-film transistor and method of manufacturing the same | |
US6869834B2 (en) | Method of forming a low temperature polysilicon thin film transistor | |
JPS63308384A (en) | Thin film transistor | |
JPH01227475A (en) | Amorphous silicon thin-film transistor | |
US6514803B1 (en) | Process for making an amorphous silicon thin film semiconductor device | |
JP3125931B2 (en) | Semiconductor fabrication method | |
Krishnan et al. | Fabrication of microcrystalline silicon TFTs using a high-density plasma approach | |
JPH03104209A (en) | Manufacture of semiconductor device | |
CN100555587C (en) | Low-temperature polysilicon film transistor and manufacture method thereof | |
JP2751420B2 (en) | Method for manufacturing semiconductor device | |
JP4892814B2 (en) | Method for producing organic thin film transistor | |
KR0139741B1 (en) | Fabrication method of tft | |
JPH0435019A (en) | Thin film transistor | |
US11069724B2 (en) | Array substrate, manufacturing method thereof and display device using the same | |
JP3325664B2 (en) | Thin film transistor and method of manufacturing the same | |
Yeh et al. | Amorphous-silicon thin-film transistor with liquid phase deposition of silicon dioxide gate insulator | |
JPH0661489A (en) | Manufacture of thin-film transistor | |
KR100571005B1 (en) | Method for fabrication of semiconductor devcie | |
JPH11163368A (en) | Substrate with conducting film and its manufacture | |
WO2019136873A1 (en) | Array substrate and manufacturing method thereof, display device | |
KR100709282B1 (en) | The manafacturing method of the silicon thin film transistor | |
KR930009547B1 (en) | Interface forming method of sinx/amorphous silicon | |
JP2012182225A (en) | Display device and method for manufacturing display device | |
JP3111488B2 (en) | Semiconductor device and manufacturing method thereof |