JPH01223747A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve the coverage of a wiring in the upper section of a contact hole and form a multilayer interconnection easily, and to enhance the degree of integration by forming the contact hole, through which excellent electrical continuity between a foundation metal and the wiring as an upper layer is acquired, through a lift-off method for the metal and an etchback method for an applied insulating film and flattening the wiring on the upper surface of the contact hole. CONSTITUTION:A gate electrode 2, an insulating film 3 and the pattern of a photo-resist 4 are formed onto a GaAs substrate 1, and a contact hole is shaped, using the photo-resist 4 as a mask. A metallic layer 7 is evaporated by utilizing the pattern of the photo-resist 4. When a lift-off method is employed under the state, the metallic layer 7 is left in the contact hole. SOG 6 is applied, and the head of the metallic layer 7 is exposed through etchback such as ion milling. Accordingly, the surfaces of the metallic layer 7, the SOG 6 and the insulating film 3 are flattened. When a wiring 5 is shaped, electrical continuity is obtained between the gate electrode 2 and the wiring 5 by the metallic layer 7. Since the surface of the wiring in the upper section of the contact hole is flattened, the title manufacture is suitable for multilayer interconnection.

Description

[Detailed Description of the Invention] [Field of Industrial Application] This invention stabilizes the electrical conduction between the underlying metal and the upper layer wiring by applying a metal lift-off method and an etch-back method of an insulating film such as SOG. The present invention relates to a method for manufacturing a semiconductor device that achieves flattening of wiring in a layer above a control hole.

[Conventional technology]

FIGS. 2(a) to 2(d) are process diagrams showing an example of a conventional method for manufacturing a semiconductor device. First, as shown in FIG. 2(a), Ga
After forming a pattern of a base metal 2 (referred to as a gate electrode here) on an As substrate 1, a film 3 is formed on the entire surface,
A photoresist 4 for forming a contact hole above the gate electrode 2 is patterned. Using this photoresist 1-4 as a protective film, the insulating film 3 is etched by RIE to form a contact hole as shown in FIG. 2(b). After that, by removing the photoresist 4, a pattern as shown in FIG. 2(C) is obtained, and by forming the upper layer wiring 5 on this, the pattern shown in FIG. 2(d) is obtained.
As shown, the data 1-electrode 2 and the wiring 5 are electrically connected through the insulating film 3.

[Problem to be solved by the invention]

Although the gate electrode 2 and the upper layer wiring 5 of the conventional semiconductor device are electrically connected through the minute contact hole as described above, the upper layer wiring 5 is not planarized, and therefore the cover of the wiring 5 is not flattened. However, there were problems such as poor connection and unstable electrical conduction with the underlying metal such as the gate electrode 2.

This invention was made in order to solve the above-mentioned problems, and it is possible to obtain stable electrical conduction between the underlying metal and the upper layer wiring, to form fine contact holes, and to form a contact hole in the upper layer of the collector hole. An object of the present invention is to obtain a method for manufacturing a semiconductor device that can flatten wiring.

[Means to solve the problem]

The method for manufacturing a semiconductor device according to the present invention uses a metal lift-off method and a coated insulating film etch-back method to form a contact hole that provides good electrical continuity between the underlying metal and the upper layer wiring. The wiring on the upper surface of the contact hole is flattened.

[Operation] In the present invention, the upper part of the contact hole is flattened, and the coverage of the wiring above the contact I/hole is improved.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIGS. 1(,) to (6) show the steps of the method for manufacturing a semiconductor device of the present invention. In Figure 1, 1 is Ga
An As substrate, 2 an electrode, 3 an insulating film, 4 a coated insulating film such as photoresist OG (hereinafter referred to as SOG), and 7 a metal layer.

Note that the applied insulating film is a material that can be coated and formed by processing, such as SOG6, and is different from the insulating film 3.

Next, the manufacturing process will be explained.

As shown in Fig. 1 (a) and (b), Fig. 2 (a3, (
Similar to the conventional example shown in b), data 1 is placed on the GaAs substrate 1.
- Patterns of the electrode 2, insulating film 3, and photo-sist 4 are formed, and furthermore, contact holes are formed using the resistors 1-4 as masks. Next, as shown in FIG. 1(c), a photoresist is applied. If a lift-off method is used in this state, the metal layer 7 remains within the contact hole, as shown in FIG. 1(d). Next, as shown in FIG. 1(e), after applying SOG 5, the metal layer 7 is etched back by ion milling or the like to locate the beginning of the metal layer 7, resulting in the result as shown in FIG. 1(f). As a result, the metal layer 7 and the S. O G 6 and insulating film 3
The surface of is flattened. Next, as shown in FIG. 1(g), when a wiring 5 is formed, electrical continuity is obtained between the gate electrode 2 and the wiring 5 through the metal layer 7. Since the wiring surface above the contact hole is flat, it is suitable for multilayer wiring.

In addition, in the above embodiment, the base metal is Ga) and the electrode 2.
However, any base metal may be used.

Further, not only the GaAs substrate 1 but also a substrate such as 81 may be used. Further, the SOG6 may be any other insulating film that can be formed by coating.

〔Effect of the invention〕

As explained above, the present invention forms a metal layer in a contact hole by applying a lift-off method and an etch-back method, and obtains electrical continuity between a base metal and an upper layer wiring through this metal layer. Therefore, the wiring in the upper layer comes into contact with the upper part of the flattened contact hole, and the gaps and twists of the wiring above the contact hole are improved.9 Multilayer wiring can be easily formed, and the degree of integration is improved.

[Brief explanation of the drawing]

FIG. 1 is a process sectional view of a method of manufacturing a semiconductor device showing an embodiment of the present invention, and FIG. 2 is a process sectional view of an example of a conventional method of manufacturing a semiconductor device. In the drawing, 1 is a GaAs substrate, 2 is a gate electrode, and 3 is a GaAs substrate.
4 is an insulating film, 4 is a photoresist line, 6 is SOG, and 7 is a metal layer. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa (2 others) Figure 1 1 Genus bud 1 Figure 1 5: SOG Figure 2 procedural amendment (voluntary)

Claims (1)

[Claims] A step of forming an insulating film over the entire surface of the substrate on which the underlying metal pattern is formed, and forming a photoresist pattern on this insulating film, and forming a contact hole in the insulating film using the photoresist pattern as a mask. process,
After forming a metal layer on the entire surface, the metal layer is left only in the contact hole by a lift-off method.After forming a coating insulating film on the entire surface, etching back until the top surface of the metal layer in the contact hole is exposed. A method of manufacturing a semiconductor device, comprising the step of forming an upper layer wiring over the entire surface.