JPS63287033A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS63287033A
JPS63287033A JP12200687A JP12200687A JPS63287033A JP S63287033 A JPS63287033 A JP S63287033A JP 12200687 A JP12200687 A JP 12200687A JP 12200687 A JP12200687 A JP 12200687A JP S63287033 A JPS63287033 A JP S63287033A
Authority
JP
Japan
Prior art keywords
metal pattern
metal
insulating film
wiring
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12200687A
Other languages
Japanese (ja)
Inventor
Hirobumi Nakano
博文 中野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP12200687A priority Critical patent/JPS63287033A/en
Publication of JPS63287033A publication Critical patent/JPS63287033A/en
Pending legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To prevent breakdown of a wiring, by forming a conducting metal pattern on a metal pattern on a semiconductor substrate, covering the pattern with an insulating film, flattening the surface with an applying material, etching the surface so as to expose the upper surface of the conducting metal, and providing a wiring metal. CONSTITUTION:A resist mask 3 is applied on a metal pattern 2 on a semiconductor substrate 1. A metal film 5a is formed on the entire surface. The resist 3 and the unnecessary metal film 5a are removed by lift-off. Thus a conducting metal pattern 5 is formed. Then an insulating film 6 is formed. Photoresist 7 is applied so that the upper part becomes flat. Then RIE is performed, and the upper surface of the conducting metal pattern 5 is exposed. After the unnecessary resist is removed, a wiring metal 8 is formed. In this constitution, breakdown of the wiring does not occur even if a fine conducting part is formed.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、絶縁膜の下層と上層に形成されるパターン
間で確実に電気的導通を得るようにした半導体装置の製
造方法に関するものである。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device that ensures electrical continuity between patterns formed in a lower layer and an upper layer of an insulating film. .

(従来の技術) 第2図(a)〜(e)は従来のこの種の半導体装置の製
造方法を示す工程断面図であり、1は半導体基板、2は
この半導体基板1上に形成された金属パターン、3はフ
ォトレジスト、4は絶縁膜、8は配線金属である。
(Prior Art) FIGS. 2(a) to 2(e) are process cross-sectional views showing a conventional manufacturing method of this type of semiconductor device, in which 1 is a semiconductor substrate, and 2 is a semiconductor device formed on this semiconductor substrate 1. A metal pattern, 3 is a photoresist, 4 is an insulating film, and 8 is a wiring metal.

゛ 次に製造工程について説明する。゛Next, the manufacturing process will be explained.

まず、第2図(a)に示すように、金属パターン2が形
成されている半導体基板1全面に絶縁膜4を形成し、次
いで、第2図(b)のように、絶縁膜4上にフォトレジ
スト3を塗布した後、通常の写真製版法を用い所望の部
分にフォトレジスト3の開口部を設ける。次に、第2図
(C)のように、フォトレジスト3をマスクとしてRI
E等により絶縁膜4をエツチング除去する。次に、フォ
トレジスト3を除去し、第2図(d)に示すような絶縁
膜4の開口部を得る。次に、第2図(e)のように、配
線金属8を形成する。
First, as shown in FIG. 2(a), an insulating film 4 is formed on the entire surface of the semiconductor substrate 1 on which the metal pattern 2 is formed, and then, as shown in FIG. 2(b), an insulating film 4 is formed on the insulating film 4. After applying the photoresist 3, an opening in the photoresist 3 is provided at a desired portion using a normal photolithography method. Next, as shown in FIG. 2(C), RI is performed using the photoresist 3 as a mask.
The insulating film 4 is removed by etching using E or the like. Next, the photoresist 3 is removed to obtain an opening in the insulating film 4 as shown in FIG. 2(d). Next, as shown in FIG. 2(e), wiring metal 8 is formed.

(発明が解決しようとする問題点) 従来の半導体装置の製造方法は、第2図(d)の工程で
絶縁膜4に開口部を形成後、上層に配線金属8を形成す
る場合、開口部の段差部分での配線金属8のカバレッジ
が悪く、配線金属8の段切れが発生する等の問題点があ
った。
(Problems to be Solved by the Invention) In the conventional manufacturing method of a semiconductor device, after forming an opening in the insulating film 4 in the step shown in FIG. There were problems such as poor coverage of the wiring metal 8 at the stepped portion, and step breaks in the wiring metal 8 occurring.

この発明は、上記のような問題点を解決するためになさ
れたものでミ絶縁膜の急峻な段差を形成することなしに
電気的導通を得ることにより、配線金属と下地パターン
とを確実に接続できるとともに、容易にパターンの集積
化が可能な半導体装置の製造方法を得ることを目的とす
る。
This invention was made to solve the above-mentioned problems, and it is possible to reliably connect the wiring metal and the underlying pattern by obtaining electrical continuity without forming steep steps in the insulation film. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can easily integrate patterns.

〔問題点を解決するための手段〕[Means for solving problems]

この発明に係る半導体装置の製造方法は、半導体基板上
に形成された金属パターンの上層に導通用金属パターン
を形成する工程と、全面に絶縁膜を形成した後、塗布材
料により平坦化し、エツチングにより導通用金属パター
ンの上面を露出させ、その上層に配線金属を形成するよ
うにしたものである。
The method for manufacturing a semiconductor device according to the present invention includes a step of forming a conductive metal pattern on the upper layer of a metal pattern formed on a semiconductor substrate, and after forming an insulating film on the entire surface, flattening it with a coating material and etching it. The upper surface of the conductive metal pattern is exposed, and a wiring metal is formed on the upper layer.

〔作用〕[Effect]

この発明においては、絶縁膜を形成する前に既存の金属
膜上に導通用金属−パターンを形成し、その後絶縁膜を
形成し、塗布材料による平坦化およびエツチングを用い
、導通用金属パターンの上面を露出させた後、配線金属
を形成することから絶縁膜が平坦化され、絶縁膜の段差
を乗りこえることなしに、配線金属が形成できる。
In this invention, before forming an insulating film, a conductive metal pattern is formed on an existing metal film, and then an insulating film is formed, and the top surface of the conductive metal pattern is flattened with a coating material and etched. Since the wiring metal is formed after exposing the insulating film, the insulating film is flattened, and the wiring metal can be formed without going over the step of the insulating film.

(実施例〕 以下、この発明の一実施例を第1図(a)〜(h)につ
いて説明する。第1図において、第2図と同一符号は同
一部分を示し、5は前記金属パターン2上に形成された
導通用金属パターン、6は前記導通用金属パターン5を
形成した後、全面に形成された絶縁膜、7は平坦化のた
めに塗布されたフォトレジストである。
(Embodiment) An embodiment of the present invention will be described below with reference to FIGS. 1(a) to (h). In FIG. 1, the same reference numerals as in FIG. The conductive metal pattern 6 formed on the conductive metal pattern 5 is an insulating film formed on the entire surface after forming the conductive metal pattern 5, and 7 is a photoresist coated for planarization.

次に、この製造工程について説明する。Next, this manufacturing process will be explained.

まず、第1図(a)に示すように、金属パターン2が形
成された半導体基板1上にフォトレジスト3を塗布する
。次に、通常のマスク合わせ露光、現像を行い、第1図
(b)に示すようなレジストパターンを形成する。次に
、第1図(C)に示すように、全面に金属膜5aを形成
する。次に、リフトオフにより第1図(d)に示すよう
に、フォトレジスト3とともに、不要の金属膜5aを除
去することにより導通用金属パターン5を得る。次に、
第1図(e)に示すように、全面に絶縁膜6を形成し、
さらに、その上層にフォトレジストアを上面が平坦とな
るように塗布する。
First, as shown in FIG. 1(a), a photoresist 3 is applied onto a semiconductor substrate 1 on which a metal pattern 2 is formed. Next, normal mask alignment exposure and development are performed to form a resist pattern as shown in FIG. 1(b). Next, as shown in FIG. 1(C), a metal film 5a is formed on the entire surface. Next, as shown in FIG. 1(d), the unnecessary metal film 5a is removed together with the photoresist 3 by lift-off, thereby obtaining the conductive metal pattern 5. next,
As shown in FIG. 1(e), an insulating film 6 is formed on the entire surface,
Furthermore, photoresist is applied to the upper layer so that the upper surface is flat.

次に、第1図Cf>に示すように、RIE等でエツチン
グし導通用金属パターン5の上面を露出させる。次に、
不要となったフォトレジストアを除去し、第1図(g)
のようなパターンを得る。その後、第1図(h)のよう
に配線金属8を形成する。
Next, as shown in FIG. 1Cf, etching is performed using RIE or the like to expose the upper surface of the conductive metal pattern 5. next,
Remove the unnecessary photoresist and remove it as shown in Figure 1 (g).
You will get a pattern like . Thereafter, wiring metal 8 is formed as shown in FIG. 1(h).

なお、上記実施例では平坦化に用いる膜にフォトレジス
トアを使用したものを示したが、エツチング可能な塗布
材料であればフォトレジストである必要はない。
In the above embodiment, a photoresist was used as the film used for planarization, but the film does not need to be a photoresist as long as it is an etchingable coating material.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、この発明は、半導体基板上に形成
された金属パターンの上層に導通用金属パターンを形成
する工程と、全面に絶縁膜を形成した後、塗布材料によ
り平坦化し、エツチングにより導通用金属パターンの上
面を露出させ、その上層に配線金属を形成するようにし
たので、配線金属が絶縁膜の段差を乗りこえることなし
に形成される。したがって、微細な導通部分を形成して
も配線金属の段切れ等がなく信頼性の高いものが得られ
る効果がある。
As explained above, the present invention includes a step of forming a conductive metal pattern on the upper layer of a metal pattern formed on a semiconductor substrate, and after forming an insulating film on the entire surface, flattening it with a coating material and conducting it by etching. Since the upper surface of the general metal pattern is exposed and the wiring metal is formed on the upper layer, the wiring metal can be formed without going over the step of the insulating film. Therefore, even if a minute conductive portion is formed, there is no disconnection of the wiring metal, and a highly reliable product can be obtained.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の一実施例を示す半導体装置の製造方
法の工程断面図、第2図は従来の半導体装置の製造方法
の工程断面図である。 図において、1は半導体基板、2は金属パターン、3は
フォトレジスト、5は導通用金属パターン、6は絶縁膜
、7はフォトレジスト、8は配線金属である。 なお、各図中の同一符号は同一または相当部分を示す。 代理人 大 岩 増 雄    (外2名)第1図 第1図
FIG. 1 is a process sectional view of a method of manufacturing a semiconductor device showing an embodiment of the present invention, and FIG. 2 is a process sectional view of a conventional method of manufacturing a semiconductor device. In the figure, 1 is a semiconductor substrate, 2 is a metal pattern, 3 is a photoresist, 5 is a conductive metal pattern, 6 is an insulating film, 7 is a photoresist, and 8 is a wiring metal. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa (2 others) Fig. 1 Fig. 1

Claims (1)

【特許請求の範囲】[Claims] 半導体基板上に形成された金属パターンの上層に導通用
金属パターンを形成する工程と、全面に絶縁膜を形成し
た後、塗布材料により平坦化し、エッチングにより導通
用金属パターンの上面を露出させ、その上層に配線金属
を形成することを特徴とする半導体装置の製造方法。
The process of forming a conductive metal pattern on the upper layer of the metal pattern formed on the semiconductor substrate, and after forming an insulating film on the entire surface, it is flattened with a coating material, and the top surface of the conductive metal pattern is exposed by etching. A method of manufacturing a semiconductor device, comprising forming a wiring metal in an upper layer.
JP12200687A 1987-05-19 1987-05-19 Manufacture of semiconductor device Pending JPS63287033A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12200687A JPS63287033A (en) 1987-05-19 1987-05-19 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12200687A JPS63287033A (en) 1987-05-19 1987-05-19 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS63287033A true JPS63287033A (en) 1988-11-24

Family

ID=14825230

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12200687A Pending JPS63287033A (en) 1987-05-19 1987-05-19 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS63287033A (en)

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