JPH01219932A - Bank switching device - Google Patents

Abstract

PURPOSE:To extend a memory address space even in an 8-bit CPU by incorporating a memory management function based on bank switching on the CPU side and providing a register which designates a switching address. CONSTITUTION:A bank switching device stores address data in a block register 13 for the purpose of designating an address area to be switched. The device stores a bank number, which designates a bank to be extended, in a register 14. When a CPU 12 accesses an address, access address data and address data in the register 13 are compared with each other. When they coincide with each other, a control circuit 16 outputs the bank number stored in the bank register 14 to an extended address line. Consequently, the address space of a memory is extended without adding a special external bank switching logic.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a bank switching device that expands the address space of a memory by switching banks.

<Conventional technology> 16-bit or higher CPUs (Central Processing Units) can handle a wide range of memory space, and by incorporating MMUs (Memory Management Units) or attaching MMU chips externally,
Memory space can be easily expanded and managed using the relocation method. On the other hand, on an 8-bit CPU, C
Due to the limited capacity of the PU, it is not possible to create a system with a large memory capacity using the relocation method.

However, in an 8-bit CPU, the memory space (logical address space) is limited to 64 bytes, and in a system that handles large amounts of memory with an 8-bit CPU, it is necessary to expand the memory space (physical address space) by some means. .

Conventionally, no system using an 8-bit CPU has built-in memory management using bank switching. Therefore, the user expands the physical address space by individually adding standard logic or gate array bank switching logic to the outside of the CPU via the 110 (input/output) port. Moreover, in this case, bank switching of only one fixed area is often performed.

On the other hand, some 8-bit CPUs have a built-in memory management function using a relocation method, but in such cases there are problems such as the inability to use conventional 8-bit CPU development tools.

There is also a type of memory (mask ROM) that has a built-in bank switching function, but since the bank address is fixed, it is limited to special usage.

<Problems to be Solved by the Invention> As mentioned above, various types of memory space expansion have been performed for conventional 8-bit CPUs. However, they all have the following problems. In other words,! If the user himself adds bank switching logic outside the CPU, he must design the memory management logic himself. Furthermore, a circuit is required for external connection to CPtJ.

2. With memory management using the relocation method, conventional development tools cannot be used even on CPUs with the same instruction system.

3. For those with a built-in bank switching function on the memory side,
Since the bank address is fixed, the bank switching address cannot be specified. Furthermore, it is not possible to develop only an arbitrary address area into a bank.

4. In a full-scale MMU, if an address other than the specified address is accessed, a trap or the like is generated and complicated processing is required.

5. CPU such as DMA (direct memory access)
In the case of a system in which there are multiple devices other than those that have the right to use the address bus (hereinafter referred to as path requesters), when the CPU turns on bank expansion in one fixed area as described above, the bank other than the one accessed by the CPU A path requester such as DMA cannot access this bank. In other words, although the CPU's memory access and the bus requester's memory access are independent, the bus requester can only access banks designated by the CPU. Conversely, the CPU cannot change banks carelessly.

There are other problems.

Therefore, an object of the present invention is to provide a built-in memory management function for bank switching on the CPU side and a register for specifying a bank switching address. An object of the present invention is to provide a bank switching device capable of expanding the address space of a memory by performing switching.

Means for Solving the Problems> In order to achieve the above object, the present invention provides a bank switching device that expands a limited logical address space of a memory to a larger physical address space, which a block register that stores address data that specifies a block register, a bank register that stores a bank number that specifies a bank that extends the address area specified by the address data stored in the block register, and a lower address line that is accessed by an address access means. A match detection circuit outputs a match signal when the address data output from the block register matches the address data stored in the block register, and the address access is performed based on the match signal output from the match detection circuit. When the address data from the means and the address data from the block register match, the bank number stored in the bank register is output to the extended address line, while when they do not match, the bank number is output to the extended address line, indicating that the address area will not be extended. The present invention is characterized in that it includes a control circuit that outputs the number 1 to the extended address line.

<Operation> Address data specifying the address area for bank switching is stored in advance in the block register, and a bank number specifying the bank to extend the address area specified by the address data stored in the block register is stored in the bank register. Stored in advance.

Then, the match detection circuit outputs a match signal when the address data outputted to the lower address line by the address access means matches the address data stored in advance in the block register. When the address data from the address access means matches the address data from the block register based on a match signal output from the match detection circuit, the bank number stored in the bank register is controlled. While output by the circuit to the extended address line,
If they do not match, the control circuit outputs a bank number indicating that the address area will not be expanded to the extended address line.

Therefore, banks can be switched by specifying only an arbitrary address area using the block register.

<Example> Hereinafter, the present invention will be explained in detail with reference to illustrated embodiments.

FIG. 1 shows an example of expansion from a logical address space to a physical address space according to the present invention.

The original logical address space of the CPU is a limited memory area in the block direction (vertical direction) of bank O, but according to the present invention, any bank switching designated area (block) can be developed in the bank direction (horizontal direction).

FIG. 2 is a block diagram showing one embodiment of the bank switching device of the present invention. This bank switching device is CPU2. Block register 13. Bank register 14. A coincidence detection circuit 15 and a control circuit 16 are built into one chip 11.

The block register 13 is a register that specifies the address area of the block to be changed banks, and the bank register 14 is a register that specifies the bank number of the bank to which the area specified by the block register 13 is to be expanded.

The bank switching device configured as described above stores address data outputted from the CPU 12 in advance in the block register 13 in order to designate the address area of the block to be changed over, and stores the address data outputted from the CPU 12 in advance in the block register 13 in order to designate the address area of the block to be expanded.
The bank number output from 2 is stored in the bank register 14.

Then, when the CPU 12 accesses the address, the C
A match detection circuit 15 checks whether the access address data output from the PU 12 and the address data stored in advance in the block register 13 and designated are matched. As a result, if a match is detected between the access address data output from the CPU 2 and the address data from the block register 13, the control circuit I6 stores the data in the bank register 14 based on the match signal output from the match detection circuit 15. The specified bank number is output to the extended address line. On the other hand, if the access address data of the CPU 2 does not match the address data stored and specified in the block register 13, the match detection circuit 1
5 does not output a coincidence signal. And bank register 1
The control circuit 16 inhibits the output of the bank number from 4 and outputs bank 0 to the extended address line.

Therefore, the memory address space can be expanded without adding any special external bank switching logic to the CPU 12, and any area can be specified for expansion, and areas that do not want to be expanded can be left as is. It becomes possible to access the original logical address space.

FIG. 3 is a block diagram showing a second embodiment of the bank switching device of the present invention. It is built into the chip 21. The first block register 231 is a register that stores the address area of the block for which bank switching is to be performed.
This register stores the bank number of the bank to be stored in and to expand the specified area.

In advance, address data output from the CPU 22 to specify the address area for bank switching is stored in the first block register 231, and a bank number output from the CPU 22 to specify the bank to be expanded is stored in the first bank register 231. 232. Then, C.P.
When U22 or a path requester such as a DMA (not shown) accesses the corresponding address, the first coincidence detection circuit 23
3 detects a match between the access address data from the CPU 22 or the path requester and the address data from the first block register 231, and
The bank number specified in step 2 is outputted to the multiplexer 25 by the first control circuit 234. Further, when a match is not detected, the first control circuit 234 outputs bank 0 to the multiplexer 25.

On the other hand, the first block register 231. First bank register 232. Similar to the first bank switching function block 23 consisting of a first coincidence detection circuit and a first control circuit 234, a second block register 241, a second bank register 242 . Second coincidence detection circuit 243 and second control circuit 2
A second bank switching function block 24 consisting of 34 is provided,
Similarly to the above, the bank number output from the second control circuit 244 and the bank number output from the first control circuit 234 are multiplexed by the multiplexer 25 and output to the extended address line.

The bank switching device of the second embodiment has a first bank switching function block 23 and a second bank switching function block 24.
For example, the first bank switching functional block specifies the address area for bank switching for the CPU 22 and the bank number to be expanded, and the second bank switching functional block specifies the bank switching for the path requester. The address area to be switched and the bank number to be expanded can be specified. Therefore, CPU2
Based on the access address data from 2, the first control circuit 234 outputs the bank number to be accessed by the CPU 22. On the other hand, the bank number accessed by the path requester is output from the second control circuit 244 based on the access address data from the path requester inputted via the lower address bus 26. That is, the path requester can access another bank independently of the CPU 22.

Although two bank switching function blocks are provided in the second embodiment, the present invention is not limited to this, and any number of bank switching function blocks may be provided depending on the number of path requesters.

<Effects of the Invention> As is clear from the above, the present invention stores in advance address data specifying an address area for bank switching in a block register, and stores a bank number in a bank register specifying a bank to which the address area is to be extended. is stored in advance, and when the address data from the address access means matches the address data from the block register, the bank number stored in the bank register is output to the extended address line by the control circuit. Even when used in an 8-bit CPU, the address space of the memory can be expanded by specifying only an arbitrary address area and switching banks without adding bank switching logic outside the CPU.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of expansion from a logical address space to a physical address space according to the present invention, FIG. 2 is a block diagram showing an example of an actual flow of a bank switching device according to the present invention, and FIG. 3 is a diagram different from the above embodiment. FIG. 7 is a block diagram showing a different second embodiment. 12.22...CPU. 13.231,241...Block register, 14.
232.242...Bank register, 15.233,
243... Match detection circuit, 16.234.244...
- Control circuit, 25... multiplexer.

Claims (1)

[Claims] (1) A bank switching device that expands the limited logical address space of a memory to a larger physical address space, which includes a block register that stores address data that specifies the address area for bank switching, and a block register that stores address data in the block register. A bank register that stores a bank number that specifies a bank to extend the address area specified by the address data, address data output to the lower address line by the address access means, and address data stored in the block register. and a match detection circuit that outputs a match signal when the match detection circuit matches the address data from the address access means and the address data from the block register based on the match signal output from the match detection circuit. In some cases, the control circuit outputs the bank number stored in the bank register to the extended address line, and when they do not match, outputs a bank number indicating that the address area will not be expanded to the extended address line. bank switching device.