JP2843329B2 - Bank switching device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bank switching apparatus for expanding a memory address space by performing bank switching.

<Conventional technology> A 16-bit or higher CPU (Central Processing Unit) can handle a large memory space, and a built-in MMU (Memory Management Unit) or external MMU chip enables the memory space to be relocated. Can be easily expanded and managed. On the other hand, with an 8-bit CPU, a system having a large capacity memory cannot be created by the relocation method due to the limitation of the CPU capacity. However, in an 8-bit CPU, the memory space (logical address space) is limited to 64 Kbytes, and in a system that handles the second capacity memory with an 8-bit CPU, it is necessary to expand the memory space (physical address space) by some means.

Conventionally, no system using an 8-bit CPU has a built-in memory management by bank switching. Therefore, the user adds the standard logic or the bank switching logic by the gate array to the outside of the CPU via the I / O (input / output) port to expand the physical address space. Moreover, in that case, only bank switching of one fixed area is often performed. On the other hand, some 8-bit CPUs have a built-in memory management function based on the relocation method. However, in that case, there are problems such as the inability to use a conventional 8-bit CPU development tool.

There is also a memory (mask ROM) having a bank switching function on the memory side, but the bank address is fixed, so that only a special use method is restricted.

<Problems to be Solved by the Invention> As described above, various memory spaces have been expanded in the conventional 8-bit CPU. However, both have the following problems. That is: 1. When the user himself / herself adds bank switching logic outside the CPU, the user himself / herself must design the memory management logic. Also, an external circuit for the CPU is required.

2. In memory management using the relocation method, conventional development tools cannot be used even with CPUs of the same instruction system.

3. If the memory has a bank switching function, the bank address is fixed, so the bank switching address cannot be specified. Further, it is not possible to develop only an arbitrary address area in a bank.

4. In a full-scale MMU, when an address other than the specified address is accessed, a trap or the like is generated and complicated processing is required.

5. In a system such as DMA (direct memory access) where there are multiple CPUs that have the right to use the address bus (hereinafter referred to as bus requesters) other than the CPU, as described above,
In the bank expansion in one fixed area by U, banks other than the bank accessed by the CPU cannot be accessed by the bus requester such as the DMA. In other words, although the memory access of the CPU and the memory access of the bus requester are independent, the bus requester
Can access only the specified bank. Conversely, the CPU cannot inadvertently switch banks.

There are problems such as.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a bank switching device in which a plurality of memory management functions by bank switching are built in a CPU side so that a bus requester can access a bank other than a bank accessed by the CPU.

<Means for Solving the Problems> In order to achieve the above object, the present invention relates to a bank switching device for expanding a limited logical address space of a memory to a larger physical address space, and comprises an address area for performing bank switching. And a bank register for storing a bank number for specifying a bank extending an address area specified by the address data stored in the block register. A match signal is output when the address data output to the lower address line or the address data input from the external bus requester via the bidirectional lower address line matches the address data stored in the block register. And a match detection circuit that outputs Address data from the central processing unit or address data input from the external bus requester via the bidirectional lower address line and address data from the block register based on the coincidence signal output from the block register. A bank which has a control circuit for outputting the bank number stored in the bank register to the extended address line when it matches, while outputting a bank number indicating that the address area is not extended to the extended line when it does not match A plurality of switching function blocks are provided on one chip together with the central processing unit.

<Operation> Address data specifying an address area for performing bank switching for the CPU and the bus requester is stored in advance in block registers of different bank switching function blocks. On the other hand, the bank numbers for the CPU and the bus requester that specify the bank that extends the address area specified by the address data stored in the block register are stored in advance in the bank registers of the different bank switching function blocks. Assume that address data is output from the CPU to the lower address line.

Then, the match detection circuit of each bank switching function block outputs a match signal when the address data output from the CPU to the lower address line matches the address data previously stored in the block register. When the address data from the CPU matches the address data from the block register based on the match signal output from the match detection circuit, the bank number stored in the bank register is expanded by the control circuit. While output to the address line,
If they do not match, a bank number indicating that the address area is not extended is output to the extended address line by the control circuit. In this way, a bank to be accessed by the CPU is set by the corresponding one bank switching function block.

On the other hand, when address data is input from the bus requester via the lower address line, the same operation as described above is performed by each bank switching function block.
Then, the bank number of the bank accessed by the bus requester is output to the extended address line by another corresponding bank switching function block, and the bank accessed by the bus requester is set.

Thus, the bus requester can access another bank independently of the CPU.

<Example> Hereinafter, the present invention will be described in detail with reference to an illustrated example.

FIG. 1 shows an example of extension from a logical address space to a physical address space according to the present invention. Although the original logical address space of the CPU is a limited memory area in the block direction (vertical direction) of bank 0, the present invention allows an arbitrary bank switching designation area (block) to be developed in the bank direction (horizontal direction).

FIG. 2 is a block diagram showing an embodiment of the bank switching device of the present invention, which is incorporated in one chip 21.
The first block register 231 is a register for storing an address area of a block for which bank switching is to be performed, and the first bank register 232 is a register for storing a bank number of a bank which is stored in the first block register 231 and extends a designated area. It is.

The address data output from the CPU 22 in advance to specify an address area for bank switching is stored in the first block register 231, and the bank number output from the CPU 22 to specify the bank to be expanded is stored in the first bank register. 232 is stored.

When the CPU 22 or a bus requester such as a DMA (not shown) accesses the corresponding address, the first match detection circuit 233 stores the access address data output from the CPU 22 or the bus requester and the first block register 231 in advance. Is detected with the address data specified. If they match, the first control circuit 234 outputs the specified bank number stored in the first bank register 232 to the multiplexer 25 based on the match signal output from the first match detection circuit 233. I do.

On the other hand, when the access address data of the CPU 22 does not match the address data specified and stored in the first block register 231, the first match detection circuit 233 does not output a match signal. As a result, the first bank register 232
Output of the bank number from the first control circuit 23 is prohibited.
4 outputs bank 0 to the extension address line.

Here, in the present embodiment, the above-described first block register 231, first bank register 232, first match detection circuit 23
Similarly to the first bank switching function block 23 including the third and first control circuits 234, the second bank switching including the second block register 241, the second bank register 242, the second match detection circuit 243, and the second control circuit 244. A function block 24 is provided. Then, the bank number to be accessed is output from the second control circuit 244 to the multiplexer 25 in the same manner as described above. Then, the multiplexer 25 multiplexes the bank number output from the second control circuit 244 and the bank number output from the first control circuit 234, and outputs the multiplexed address to the extended address line.

As described above, the bank switching device of the present embodiment includes the first bank switching function block 23 and the second bank switching function block 24.
The first bank switching function block specifies, for example, an address area for bank switching for the CPU 22 and an extended bank number in the first bank switching function block, and the second bank switching function block for the bus requester in the second bank switching function block. The address area for performing the bank switching and the bank number to be extended can be designated. At that time, the first control circuit 23 is controlled based on the access address data from the CPU 22.
The bank number accessed by the CPU 22 is output from 4. On the other hand, the bank number accessed by the bus requester is output from the second control circuit 244 based on the access address data from the bus requester input through the address bus 26 described below.

That is, the bus requester can access another bank independently of the CPU 22.

Although two bank switching function blocks are provided in the present embodiment, the present invention is not limited to this, and an arbitrary number may be provided according to the number of bus requesters.

<Effects of the Invention> As is apparent from the above description, the bank switching device according to the present invention includes a block register for storing address data for designating an address area for bank switching, and a bank number for designating a bank for extending the address area. Control circuit for outputting the bank number stored in the bank register to the extended address line when the address data from the CPU or the lower address line matches the address data stored in the block register. Since a plurality of bank switching function blocks composed of the above and the CPU are provided on one chip, it is necessary to specify an address area for performing bank switching for different address access means and a bank number to be extended for each bank switching function block. Can be.

Therefore, according to the present invention, even when used in an 8-bit CPU, the bus requester can access a bank other than the bank accessed by the CPU without adding bank switching logic outside the CPU.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of an extension from a logical address space to a physical address space according to the present invention, and FIG. 2 is a block diagram showing an embodiment of a bank switching device of the present invention. 22 ... CPU, 231,241 ... Block register, 232,242 ... Bank register, 233,243 ... Match detection circuit, 234,244 ... Control circuit, 25 ... Mux.

Claims (1)

(57) [Claims] 1. A bank switching device for expanding a limited logical address space of a memory to a larger physical address space, comprising: a block register for storing address data designating an address area for performing a bank switch; A bank register that stores a bank number that specifies a bank that extends the address area specified by the address data stored in the address data stored in the address data output from the central processing unit to the lower bidirectional address line or the bidirectional lower address line A match detection circuit that outputs a match signal when address data input from an external bus requester via the lower address line matches the address data stored in the block register; Based on the matching signal
When the address data from the central processing unit or the address data input from the external bus requester via the bidirectional lower address line matches the address data from the block register, the data is stored in the bank register. While the output bank number is output to the extension address line,
A bank switching device comprising a plurality of bank switching function blocks having a control circuit for outputting a bank number indicating that an address area is not extended to the extension line, together with the central processing unit, on a single chip.