JPH01215189A - Picture display device - Google Patents

Abstract

PURPOSE:To miniaturize a device by applying A/D conversion to a television signal, recording it to an audio magnetic tape by compression and synthesizing the television signal of required information quantity for liquid crystal display from the data reproduced from the magnetic tape at reproduction to apply picture display. CONSTITUTION:A television signal is subjected to A/D conversion and the luminance signal Y of the digital television signal subjected to A/D conversion and color difference signals R-Y, B-Y are processed separately as parameter to store it on a DAT(digital audio tape recorder) tape 23. Then based on the parameter reproduced from the DAT tape at reproduction, the digital luminance signal and the digital color difference signal are synthesized and displayed digitally on the display means 29 such as a liquid crystal display panel. The received television signal and the reproduced/synthesized television signal are selected and switched by a switch means 31 and displayed on the picture display means 29. Thus, miniaturization is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image display device that compresses a television signal and records it on an audio magnetic tape, and also plays the compressed television signal and displays it on a liquid crystal display panel or the like. .

[Prior Art] In recent years, liquid crystal televisions have become popular. Since this liquid crystal television can be miniaturized, it is often portable and viewed on the way to work or while traveling. However, in places such as trains and mountainous areas, the radio wave conditions are poor and the tuner cannot receive the signal well.

Therefore, there is a desire to be equipped with a VTR so that TV images can be recorded and played back, so that people can watch the VTR on trains and other places.

[Question 8 to be solved] However, since the VTR has a large mechanism and there is a limit to miniaturization, there is a problem that it is not suitable for combination with a liquid crystal television set for portable use.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an image display device that can be miniaturized by using an audio cassette magnetic tape.

[Means for solving the problem] In other words, we focused on the fact that because LCD televisions sample television signals and perform digital display, the amount of image information is less than that of analog television signals. In addition to compressing the data of the digital television signal and recording it on audio magnetic tape,
During playback, rather than returning to the original analog television signal, the digital television signal is synthesized with the amount of information required for the liquid crystal display and displayed on the liquid crystal display.
It is characterized by being able to be miniaturized.

In addition, by parameterizing the luminance signal and color difference signal separately during data compression, the luminance signal can be compressed with a sufficient amount of information, and the color difference signal, for which the human eye has low sensitivity, can be compressed with a large amount of information. It is designed to be compressed.

Furthermore, regarding the luminance signal, a parameter representing the contour (
The reproducibility is improved by expressing the contour parameters (contour parameters) as contour patterns and parameters representing gradation, and the color difference signal is expressed only by parameters representing gradation to increase the compression rate.

Furthermore, at the time of synthesis, a synthesized signal corresponding to the parameters is stored in the ROM, and the synthesized signal can be obtained by accessing the ROM with the reproduced parameters.

Furthermore, by using a DAT tape as the magnetic tape, it is possible to make the amount of information recordable on the tape, the amount of information necessary for liquid crystal display, and the amount of compressible information approximately equal.

Furthermore, means is provided for switching and displaying the received television signal and the reproduced television signal, and among the received television signals, the signal before parameterization is selected for the luminance signal, and the signal before parameterization is selected for the color difference signal. By selecting the converted signal, the number of signal lines of the switching means is reduced while preventing image deterioration.

Furthermore, for the color difference signal, which requires less information than the luminance signal, the circuit size is reduced by sharing the circuit by processing the RY signal and the BY signal alternately in a time-sharing manner. It is.

[Operation] In the image display device configured as described above, a television signal is A/D converted, and the luminance signal and color difference signal of the A/D converted digital television signal are separately parameterized. At the time of reproduction, a digital luminance signal and a digital color difference signal are combined based on the parameters reproduced from the DAT tape and digitally displayed on a display means such as a liquid crystal display panel. Further, the television signal reproduced and combined with the received television f-word is selectively switched by the switching means and displayed on the image display means.

[Embodiment of the Invention] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. First, the overall circuit configuration will be explained with reference to FIG. In the figure, reference numeral 11 denotes a television tuner, which selects the radio waves of a designated channel from among the TV radio waves received by the antenna 10, converts it into an intermediate frequency signal, and outputs it to the linear circuit 12. This linear circuit 12 amplifies the intermediate frequency signal sent from the tuner 11, performs video detection to extract the video signal, and further uses an internal chroma circuit to generate a Y signal (luminance signal), RY signal, B- Separate the Y signal and convert the Y signal to A/
In the D conversion circuit 13, the RY signal and the BY signal are inputted to the A/D conversion circuit 15 via the multiplexer 14.

The A/D conversion circuit 15 alternately converts the RY signal and BY signal provided via the multiplexer 14 into 6-bit digital data in a time-division manner, and outputs the digital data from the A/D conversion circuit 13. It is input to the data compression circuit 16 together with the 6-bit data for the Y signal. This data compression circuit 16 compresses one screen by 4X, for example, as will be described in detail later.
The compressed data is divided into a plurality of blocks each consisting of four dots, and gradation parameters are created for each block, and the compressed data is output to the recording circuit 17. On the other hand, the linear circuit 12 separates and amplifies the audio signal from the intermediate frequency signal and outputs it to the A/D conversion circuit 18 and the switching circuit 19. The A/D conversion circuit 18 converts the audio signal from the linear circuit 12 into 10-bit digital data and outputs it to the audio compression circuit 21. The audio compression circuit 21 compresses 10-bit input audio data into 8-bit data and outputs it to the recording circuit 17. This recording circuit I7 receives the compressed image data from the data compression circuit 16 and the audio compression circuit 21.
Compressed audio data is written onto a magnetic tape 23 by a magnetic head section 22 consisting of two heads for both recording and reproduction.

As this magnetic tape 23, for example, a DAT tape is used. The data recorded on the magnetic tape 23 is read out by the magnetic head section 22, and the data recorded on the magnetic tape 23 is read out by the reproduction circuit 24.
is man-powered. As the recording circuit 17 and the reproducing circuit 24, for example, those for DAT are used, and the DAT system is also used for all signal processing such as error correction, interleaving, modulation, demodulation, and deinterleaving. Although the servo system is not shown, it also has the same configuration as the DAT. However, the tape format does not have to be the same as DAT.

The reproduction circuit 24 reproduces image data and 8-bit audio data from the data read by the magnetic head unit 22, outputs the image data to the data synthesis circuit 25, and outputs the audio data to the audio expansion circuit 26. do. The data synthesis circuit 25 synthesizes the Y signal, the RY signal, and the BY signal using the image data from the reproduction circuit 24, as will be described in detail later, and outputs the synthesized signal to the signal conversion circuit 27. This signal conversion circuit 27 converts R,
G and B color signals are created and output to the liquid crystal drive circuit 28 to drive the liquid crystal display panel 29 for display. Further, the audio expansion circuit 26 expands the 8-bit data from the reproduction circuit 24 into 10-bit data, and outputs the data to the D/A conversion circuit 80.
The signal is converted into an analog signal and output to the switching circuit 19. This switching circuit 19 switches between the linear circuit 12 or the D/A circuit based on the control signal from the control & timing circuit 31.
The audio signal from the conversion circuit 30 is selected to drive the speaker 32. Further, the control and timing circuit 31 provides a control signal or a timing signal to each circuit section in FIG.

Next, the basic operation of the above-mentioned overall circuit will be explained. First, the television signal received by tuner ■1 is DA
Without recording on the T tape 23, the liquid crystal display panel 29 is displayed as is.
We will explain the operation when displaying on . When displaying the television signal as it is on the liquid crystal display panel 29, the control & timing circuit 31 sends a switching command to the data synthesis circuit 25 to select the image signal from the data compression circuit 16, and also A switching command is sent to the circuit 19 to select the audio signal from the linear circuit 12. When a television signal of a designated channel is received by the tuner 11 in this state, this television signal is converted into an intermediate frequency signal and then sent to the linear circuit 12. This linear circuit 12 amplifies the intermediate frequency signal input from the tuner 11, performs video detection and extracts an image signal, and then converts the image signal into a Y signal using an internal chroma circuit.

The signal is separated into a RY signal and a BY signal, and the Y signal is output to the A/D conversion circuit 13, and the RY signal and the BY signal are output to the multiplexer 14. The multiplexer 14 time-divisionally extracts the RY signal and the BY signal from the linear circuit 12 and outputs them to the A/D conversion circuit 15 . The A/D conversion circuits 13 and 15 each convert the input signal into 6-bit digital data and output it to the data compression circuit 1B. This data compression circuit 16 is an A/D
The Y signal given from the conversion circuit 13 is output as is to the data synthesis circuit 25, and the R-Y and B-Y color difference signals are converted into 8-bit gradation parameters σn-Y+σB-Y, as will be described in detail later. The converted data is output to the data synthesis circuit 25. The data synthesis circuit 25 outputs the Y signal as it is to the signal conversion circuit 27, and also outputs the color difference signal R-Y signal of the amount of information necessary for display on the liquid crystal display panel 29 from the parameters σ□-Y and σB-Y. -Y signals are synthesized and output to the signal conversion circuit 27. This signal conversion circuit 27 converts the Y signal, R-Y signal, and B-Y signal into R.
, G, and B color signals are generated, output to the liquid crystal drive circuit 28, and displayed on the liquid crystal display panel 29. On the other hand, the audio signal output from the linear circuit 12 is sent to the speaker 32 via the switching circuit 19 and output as audio.

Next, the operation of recording and reproducing the television signal received by the tuner 11 on the DAT tape 23 will be described. TV signal on magnetic tape 23
In the case of recording, the control & timing circuit 31 sends a switching command to the data synthesis circuit 25 to select the image signal from the reproduction circuit 24, and also sends a switching command to the switching circuit 19 to select the image signal from the D/A conversion circuit. A switching command is sent to select the audio signal from 30. Hereinafter, the configuration of one screen of the liquid crystal display panel 29 will be explained as shown in FIG.
The following explanation assumes that there are 92 dots x 264 dots, and each dot is expressed with 6 bits. When recording the image signals received by the tuner 11 and the linear circuit 12 on the magnetic tape 23, the data compression circuit 1B records the Y signal and color difference signal (RY signal) for one screen.

B-Y signal) is divided into blocks and compressed in units of blocks. When dividing the Y signal into blocks, the Y signal is divided into line blocks of IXN dots, for example, 1×8 dots, as shown in FIG.
The color difference signal is divided into blocks in units of MXL dots, for example, 4×4 dots, as shown in FIG.

When dividing the above Y signal into lines, as shown in Fig. 3, the Y signal is sampled at a constant cycle and
, and construct one line block. When one line block is composed of 8 dots in this way, the Y signal becomes 192,833 blocks on one screen.

In addition, when dividing the RY signal and B-Y signal into blocks, as shown in FIG. 4, four lines of color difference signals are sampled, respectively, and
24 l x 312 x 34- x 41'
Find X44 and construct one block. When one block is composed of 16 dots in this way, R-Y, B-
The Y color difference signal consists of 48×66 blocks on one screen. In this case, the color difference signal is time-divided by the multiplexer 14 and the A/D conversion circuit 15, and the R-Y
The signal and the BY signal are taken out alternately to form block data. For this reason, the amount of information of the color difference signal is halved compared to the Y signal, but there is no visual problem because such a high resolution cannot be obtained due to the characteristics of the liquid crystal display panel.

Then, when compressing the image signal, a contour pattern and gradation parameters are created from the Y signal, and the R-Y signal and B-Y
Gradation parameters are created from each signal. below,
1) Contour pattern creation and 2) Gradation parameter creation during signal compression will be explained in detail.

(2) Creation of contour pattern (from Y signal) 1) Calculate the maximum deviation δ1 in each line block using the following equation (1).

δ1 = Max (l xL*t xl-l) −(
1) That is, the difference between Xl and xi is determined for each line block for the Y signal shown in FIG. 6, and the maximum value of the difference is set as the maximum deviation δ1 of that line block.

11) Create ternary data from the Y signal.

The ternary data y for the Y signal is "1" due to the relationship between xi and δ as shown in the following equation (2).

Set to either rOJ or r-IJ.

...(2) That is, as shown in FIG. 7, if the signal difference between a certain dot xi and the previous dot X i-11 is within ±δ1/8, it is "0", and from δ1/8. If larger, “1”, δ1/
If it is smaller than 8, set the value of y to "-1". In addition,
The value of "8" in the above formula is an experimental value, and is not limited to this.

Through the above processing, the value of y for each dot is determined from the image data of one screen as shown in FIG.
Record in 3.

(2) Creation of gradation parameters (from Y signal) I) Calculate the maximum extreme value deviation δ2 using the following equation (3).

δ2−Max (l Xp −XI 1)=−(3
)-Peak That is, the maximum value of the difference between the initial value XI and the peak point (xp: local maximum value or local minimum value) is determined, and this is set as δ2. Figure 9 shows an example of the Y signal. In this example, t-X2 + x41 x (, is the peak point and x6 is the maximum extreme value deviation. As described above, for each line block The initial value x1 and the maximum extreme value deviation δ2 are calculated and recorded on the magnetic tape 23 for each block as shown in FIG.

■ Create gradation parameters for color difference signals (From R-Y signal, B-Y signal) l) Calculate the average value σ using the following equation (4).

Since the color difference signal block is a 4×4 block as shown in FIG. 4, the above equation (4) becomes as follows. This σ is composed of 4 bits above the decimal point and 2 bits below the decimal point, and is recorded on the magnetic tape 23 as a gradation parameter.

The display data is compressed to approximately ⅓ by the compression processing of the data compression circuit 16. That is, the data compression circuit 16
The amount of information of the Y signal, RY signal, and B-Y signal input to the Y signal: 192 x 204 x 8 bits - 304, 128 bits
t/frame R-Y signal + B-Y signal: 192 X284 X8 bit -304,128b
it/frame, and the total is 608.256-608 KblL/frame. Note that a frame in this case is a 1/30 (second) screen, and the amount of data is one field. One frame of a television signal is two screens of 1/60+1/60, but in this example, it is 1/30 (second).
Since one screen is one frame, the amount of information is halved.

On the other hand, the amount of information of the Y signal and color difference signal output from the data compression circuit 16 is as follows: RY signal: Therefore, the amount of information per frame output from the data compression circuit 16- is 192 x 284 x 4 days 202.752 - 203 K
blt/frame.

In addition, the information amount of yl is set to 1.5 bits because y+1
It takes 2 bits to represent an individual, but the combination of 8 bits lined up to make 16blL is 13b
It can be expressed as (38-6561≦2'
3-8192). Therefore, r13-1.
Considering 5X8+IJ, the information amount of yI is approximately 1.5blt
That's what I thought. Comparing the information amount of the input/output data of the data compression circuit 6 as described above, it becomes 203/608', l/3, and the image data in the data compression circuit 16 is reduced to 1/3.
It is compressed to 3. This compressed data is then transferred to the recording circuit 1.
7 is recorded on the magnetic tape 23.

The magnetic tape 23 is based on the DAT tape standard, but the recording format is not based on the DAT standard, and is, for example, 1800 rpm.

The rate is 7.5 frames/second. The storage capacity of a DAT tape is approximately 2109 Mbit/sec, but in this embodiment, the storage capacity is 1.
88 M/sec is used as the data area (data area excluding the parity area).

The image data written on the magnetic tape 23 is 192
X264 X3.75 203 Kbit / frame 203 K 87.5 frame - 1,523 Mbit
/second.

On the other hand, when audio data is sampled at 20/7fH, the sampling frequency is 4
It becomes 4.95KHz. In this case, since the L and R magnetic heads are alternately switched, 1/2 sampling data is given to each head. Also, since the audio compressed data is 8 bits, the recorded data is 44.95 KHz x 8 bits - 359,6 Kbi.
t/sec - 360/sec.

Therefore, the total of image data and audio data is 1.523 + 0.36-1.8Hζ1.88Mbi
t/sec. In this example, the bit rate is limited to recording 7.5 frames/second on a DAT tape, but in the case of a liquid crystal display panel, 3 bits of data for one pixel is sufficient, so 15 frames/second is possible. can be recorded.

Next, a description will be given of the processing for reproducing an image signal compressed and recorded on a recording medium such as a magnetic tape as described above, that is, (1) reproducing a Y-fold signal and (2) reproducing a color difference signal.

First, the case of reproducing the Y signal will be explained.

When reproducing a Y signal, among the signals read from the recording medium, the initial value Xi of the gradation parameter of the line block to be reproduced, the maximum extreme value deviation δ2° ternary data y,
The initial value xl' of the next line block is used. 11th
The initial value x1 of the block to be reproduced as shown in the figure
Since the initial values X and ' of the next block are determined, the intermediate point is determined using the maximum extreme value deviation δ2 and the ternary data y. The process for finding this intermediate point will be described below.

1) When y -11111111 (1 line block), ternary data y of 1 line block is all “1”
In this case, as shown in Figure 12, simply divide the space between xl and x1' into 8 equal parts and calculate the midpoint value X! using the following formula. seek.

By the way, when y-all “-1#”, you can do the same thing, and when y” are all “0”, Xi “”X
It should be I.

ji) ro to Y, 1. -IJ is mixed When the ternary data y contains the values rO, 1, -IJ, Pmax (maximum value ), Pa1n (minimum value), Ci (upward transition point) or Ci
The value Ci of (downward transition point) and the value of Z (not moving up or down) are determined by the following equation.

Pmax-Xt+62 (maximum value) pH1n-Xt-δ2 (minimum value) Zi=Zi-+ (does not go up or down) The above Ct shows the formula for finding the values of Ci and Ci by linear interpolation, and n : Number of consecutive Ci (or Ci) (if Zi is included in the middle, the number excluding Zi) i: 1, 2.3.・
..., the possible values for n co are x>, PIlln (1 o'clock), Pmax (1 o'clock),
Possible values for C1141 are xl', Pa1n (1 o'clock), Pn+ax(
1 o'clock).

In Figure 13 above, the y value of one line block is Y: X
An example is shown in which the intermediate code Yi is reproduced from the contour pattern in the case of l+l l -1101+l Xt'. In this example, in the formula for Ci for determining the value of C↓ above, Co"pHaX Cnil = P l1in. Therefore, the values of C and Z of the intermediate code are Ci (
1) = Pa + ax + (Pugin - Pmax)
Bow/4 Ci(2), -P wax + (P l1lin
-Pll1ax )・2/4 Ci(3) =Pa+ax + (Pln -Pmax
) φ3/4 Z-Ci (3). Note that FIG. 13 above only shows the rising and falling states of the data, and the amount of rise and fall is xl l
It changes variously depending on xi' + δ2.

Next, reproduction of color difference signals, that is, decoding processing from gradation parameters will be explained. The reproduction of this color difference signal is performed in the first
As shown in FIG. 4, this is basically done by assigning tone parameters σ and σ' to each pixel within the block. In this case, σ is the gradation parameter for the RY signal,
σ' is a tone parameter for the BY signal. Since the gradation parameters σ and σ' are given in 8 bits as described above, this code accesses the ROM that stores the gradation pattern, as will be described in detail later, and obtains 6 bits x 16 block information. It has gained. The above ROM contains
A plurality of tables corresponding to gradation parameters are prepared in advance, and the address of the table is specified by inputting 7 bits, and block information of 6 bits x 16 is read out. Note that one bit of the above 8-bit input is +
There is a sign bit indicating /-, so the remaining 7 bits are used for RO.
M is specified, and the read table data is used as + or - data depending on the 1-bit sign bit. As described above, the Y signal (luminance signal) for the line block and the color difference signal (RY signal, BY signal) for the 4×4 block are reproduced.

Next, a data compression circuit 16 compresses the received image data.
Details of the data synthesis circuit 25 that decodes image data from the data reproduced by the reproduction circuit 24 will be explained.

First, the data compression circuit 16 will be explained with reference to FIGS. 15 to 19. The data compression circuit 1B includes a luminance signal compression circuit 41 and a color difference signal compression circuit 42, as schematically shown in FIG. The luminance signal compression circuit 41 includes a contour pattern extraction section 43 that extracts ternary data y representing a contour pattern from the 6-bit Y signal supplied from the A/D conversion circuit 13, and a contour pattern extraction section 43 that extracts ternary data y representing a contour pattern, It consists of a gradation parameter extraction section 44 that extracts the initial value Xi and the maximum extreme value deviation δ2, the details of which will be described later.

Further, the color difference signal compression circuit 42 receives a 6-bit color difference signal (R=
8-bit gradation parameters σR-Y and σ[1-Y are extracted for each block from the Y signal and BY signal). Further, the Y signal input to the luminance signal compression circuit 41 and the gradation parameter σR-Y*σtoY output from the color difference signal compression circuit 42 are sent to the data synthesis circuit 25.

FIG. 16 shows details of the luminance signal compression circuit 41. As shown in the figure, the Y signal (digital data of 6 bits per dot) in the image signal to be recorded is input to the shift register 411, and is also input to the ignition deviation calculating section 412 and the maximum extreme value deviation. The data is input to a shift data calculation section 414 made up of a calculation section 413. Then, the ignition deviation calculation unit 412 calculates the maximum deviation δl in each line block by performing the calculation shown in the above equation (1), and together with the data held in the shift register 411, the ternary code conversion unit 415 calculates the maximum deviation δl in each line block. to use human power. This ternary code converting unit 415 performs fA calculation shown in the above equation (2) using the data xi from the shift register 411 and the maximum deviation δ1 from the ignition deviation calculation unit 412, and calculates the ternary code y. seek. In this case, 3
From the value code conversion unit 415, three types of 2-bit data ro
11. rooJ and rllJ are output, and indicate ternary data y where "01" is "1", "00" is "0", and "11" is "-1".

Further, as explained in FIG. 9, the maximum extreme value deviation calculating section 413 calculates the maximum extreme value deviation δ2 from the input data using the above equation (3), and calculates the maximum extreme value deviation δ2 from the input data together with the initial value x1 as a gradation parameter of the Y signal. Output as .

Next, details of the color difference signal compression circuit 42 shown in FIG. 15 will be explained with reference to FIG. 17. In the same figure, 421
is an adder circuit, and time-divided 6-bit color difference signals R-Y and B-Y are alternately applied to one input terminal A of the adder circuit. In addition, the other input terminal B of the adder circuit 421 has
The 9-bit compressed data stored in the RY block memory 422 and the BY block memory 423 is stored in the selector 4.
24, 425.

426. The adder circuit 421 is
The re-input data to input terminals A and B are added, and the addition output (9 bits) is input to the selector 427, and the R
It is input to a latch circuit 428 and a B latch circuit 429.

The selector 427 selects the time-divided RY signal,
Switching is controlled by a switching signal R/100 synchronized with the input cycle of the B-Y signal, and the data from the adder circuit 421 is
Block memory 422 or B-Y block memory 4
23 selectively. The block memory 422
, 423 has a capacity of 9 bits x 66 blocks, and receives the read clock R from the control & timing circuit 31.
Read/write is controlled by D and write enable clock WE. Then, the block memory 422
, 423 is temporarily latched in an internally provided buffer, and is alternately taken out via a selector 424 which is switched by a switching signal R/B.
It is sent to selector 425. Further, the switching signal R/100 is input to an AND circuit 4210 and also to an AND circuit 4212 via an inverter 4211. The AND circuits 4210 and 4212 are further inputted with the timing signal φAL which is output for each line, as well as the clock pulse φ4. The clock φR output from the AND circuit 421O is applied to the R latch circuit 428, and the clock φB output from the AND circuit 42I2 is applied to the B latch circuit 429 as latch clocks. R latch circuit 428. The B latch circuit 429 latches the RY signal and BY signal in the input data using the latch clock φR5φB, and outputs them to the selector 4213. This selector 4213
is the R latch circuit 428. The color difference signals from the B latch circuit 429 are alternately selected by the switching signal R/100 and output to the selector 425. Clock φa is applied to this selector 425 as a select signal. This clock φ
a is an AND circuit 4 that combines the clock φAL given to each line and a signal that becomes significant at the timing when lines other than line 1 of each tile block (4 x 4 dots) are selected.
214 and is created. The selector 425 selects data from the selector 424 when the clock φa is at a high level, and selects data from the selector 4213 when the clock φa is at a low level.
The selected data is output to the selector 426.

In addition, a "0" signal is input to the selector 426, and a clock φb is applied as a select signal. The clock φb is created by inputting the clock φ1B and a signal that becomes significant at the selection timing of line 1 of each tile type block to the AND circuit 4215. The selector 426 is set to “0” when the clock φb is at a high level.
``signal is selected, and when it is at a low level, the data from the selector 425 is selected and output to the adder circuit 421.The adder circuit 421 outputs the average value of the color difference signal for each block in 9 bits. The upper 6 bits indicate the integer part, and the lower 3 bits indicate the decimal part.

The 9-bit data output from the adder circuit 421 has its upper 8 bits (6 bits in the integer part and 2 bits in the decimal part) as the gradation parameter σY.

It is taken out as σB-Y and sent to the recording circuit 17.

The operation of the color difference signal compression circuit 42 configured as described above will be explained below with reference to the timing chart of FIG. 20. FIG. 20(a) shows a clock common to the system, and φ1 to φ4 are clock pulses that count the time of one pixel, of which φ1. φ3. φ4 is used. The timing of the clock pulse φ2 is set apart in consideration of the delay time of the adder circuit 421 and the like. In addition, φLB is a clock output for each head of a line block, and φTB is a tile-type block (4×4
This is a clock that is output for each beginning of a dot. This clock φTB is output with a time width of two pixels for every four pixels and every four lines in both the horizontal and vertical directions. φAL is output line by line at the same timing as φTB. 20th
Figures (b) to (d) show locks necessary for the operation of the color difference signal compression circuit 42 in Figure 17;
The common clock in Figure 7 (C) is 1°5.9
．． The clock for every 4 lines is 2 in (d) of the same figure.
．． 3, 4. 6, 7, 8. . . . indicates a clock on a line that is not at the beginning.

First, 1, 5, 9. The operation when compressing the color difference data of the lines . In the first line of each block, φTB input to the AND circuit 4215
Both the signal and the signal indicating line 1 become high level,
The clock φb output from the AND circuit 4215 becomes high level and is input to the selector 42B. Therefore, the selector 42B selects the "01 signal and inputs it to the input terminal B of the adder circuit 421. Therefore, the signal "01" is now inputted to the input terminal A of the adder circuit 421 in a time-sharing manner as shown in FIG. 20(a). The color difference signals of R-Y and B-Y are rRl,
B2. R3, B4. ...'', the adder circuit 421 sequentially outputs <R1+0> and <82 10> color difference signals while the clock φb is at a high level. Furthermore, while the clock φTB is at a high level, the clock φAL is also at a low level, and the latch clocks φR2φB are sequentially outputted from the AND circuits 4210 and 4212 in synchronization with the switching signal R/B and the clock pulse φ4. . Therefore, the color difference signal <R1+O> output from the adder circuit 421 is latched by the R latch circuit 428 in synchronization with the latch clock φR, and the color difference signal <B
l+0> is latched by the B latch circuit 429 in synchronization with the latch clock φB. The data latched by the R latch circuit 428 and the B latch circuit 429 as described above is alternately selected by the selector 4213 according to the level of the switching signal R/100 and sent to the selector 425. In FIG. 20, the output data of the adder circuit 421 is indicated by "<>" because there is a time delay in the output of the adder circuit 421, and the data is almost fixed around "<". It means to shift backwards to around the "〉" mark. Therefore, it is best to take in this output data at φ4 or at the next pixel time φ1, and in this embodiment, φ4 is used.

When line 1 is designated, the selector 425 is switched to the selector 4213 side because the clock φa is held at a low level, and the latched data R1, R latch circuit 428 and B latch circuit 429,
B2 is output to selector 42B.

In this state, when the clock φTB falls to a low level, the clock φb output from the AND circuit 4214 goes low.
level, and the selector 42B switches to the selector 425 side. Therefore, at the timing when the switching signal R/100 is at a high level, the latch data R1 of the R latch circuit 428 is transferred to the B of the adder circuit 421 via the selector 42B.
The signal is input to the terminal and added to the color difference signal R3 input to the A terminal. Then, this addition result rR1+R3J is written into the RY block memory 422 by the write enable clock WE. Next, when the switching signal R/100 falls to low level, the latch data R2 of the B latch circuit 429 is selected by the selector 4213, and the latch data R2 of the B latch circuit 429 is selected by the selector 4213.
5, 428 to the B terminal of the adder circuit 421, and is added to the color difference signal B4 input to the A terminal.

Then, this addition result rB2 +B4J is added to the BY block memory 423 by the write enable clock WE.
written to.

Thereafter, similar operations are performed, and the RY signal and BY signal sent from the A/D conversion circuit 15 in a time-division manner are added two pixels each for each signal, and the RY block memory 422. Written to B-Y block memory 423.

Then, when the process of line 1 is completed and line 2 is reached, the process operation is executed according to the timing chart shown in FIG. 20(d). At the timing of line 2, clock φAL is applied via AND circuit 4214 as clock φa for switching selector 425, and the level is inverted every two line blocks. Therefore, the selector 425 synchronizes with the clock φa and selects the selectors 424, 424,
4213 are selected alternately and output to the selector 42B.

This selector 42B is switched and controlled by the clock φb, but on line 2, the gate of the AND circuit 4215 is closed and the clock φb is held at a low level, so it is switched to the selector 425 side. Therefore, when line 2 is entered, the clock φa becomes high level and the switching signal R/B becomes high level. B of the adder circuit 421 via selectors 425 and 428.
input to the terminal. At this time, since the color difference signal R1 is given to the A terminal of the adder circuit 421, the adder circuit 421
1, the color difference signal R1 and the R-Y block memory 422
The read data R from is added. This adder circuit 4
The addition output of 21 is latched by the R latch circuit 428 in synchronization with the clock φR. Then, when the switching signal R/B switches to low level, the color difference signal B read out from the BY block memory 423 is taken out via the selector 424, and further via the selectors 425 and 428 to the B terminal of the adder circuit 421. is input. At this time, the adder circuit 42
Since the color difference signal B2 is applied to the A terminal of 1, the color difference signal B2 and the color difference signal B read from the BY block memory 423 are added in the adder circuit 421. The addition output of the adder circuit 421 is latched by the B latch circuit 429 in synchronization with the clock φB.

Thereafter, when the clock φa falls to a low level, the selector 425 is switched to the selector 4213 side. Therefore, first, when the switching signal R/100 is at a high level, the latch data of the R latch circuit 428 is selected by the selector 4213 and inputted to the B terminal of the adder circuit 421 via the selectors 425 and 428. At this time, adder circuit 4
Since the color difference signal R3 is given to the A terminal of 21, the color difference signal R3 and the R latch circuit 4 are supplied to the adder circuit 421.
The color difference signal R read from 28 is added. The addition output of this adder circuit 421 is the write enable clock W.
E is written into the RY block memory 422. Next, when the switching signal R/B falls to a low level, the data B latched in the B latch circuit 429 is transferred to the selector 4.
213 and input to the B terminal of the adder circuit 421 via selectors 425 and 428. At this time, since the color difference signal B4 is given to the A terminal of the adder circuit 421, the color difference signal B4 and B
Color difference signal B read from latch circuit 429 is added. The addition output of the adder circuit 421 is written into the BY block memory 423 by the write enable clock WE.

Thereafter, in the same manner, the R-Y block memory 422°B-Y
The color difference signals R-Y and B-Y sent from the A/D conversion circuit 15 are sequentially added to the data held in the block memory 423. Further, similar processing is performed for lines 3 and 4 of each block, and the upper eight bits of the data output from the adder circuit 421- during the processing of line 4 are sent to the recording circuit 17 and the data synthesis circuit 25.

Next, the details of the shift data calculation section 414 and the ternary code conversion section 415 in FIG. 16 are shown in FIGS. 18 and 19.
This will be explained using figures.

FIG. 18 shows details of the shift data calculation section 414. In the figure, 51 is a latch circuit that latches the 6-bit Y signal sent from the A/D conversion circuit 13 in synchronization with the clock pulse φl, and inputs it to the input terminal A of the subtraction circuit 52 and the latch circuit 53. . This latch circuit 53
clock φI.

φLB is applied as a latch clock via an AND circuit 54. The data latched by the latch circuit 53 is input to the input terminal B of the subtraction circuit 52, and is also input to the recording circuit 17 as the initial value X1 of each line block.
sent to. The subtraction circuit 52 performs subtraction of IA-Bl on the input data of the input terminals A and B, and outputs the subtraction result to the latch circuit 55:;. The data latched by the latch circuit 55 is taken out as the maximum deviation δ1, and is further taken out as the maximum extreme value deviation δ2 via the latch circuit 5B.

Further, the data latched by the latch circuit 51 is input to the input terminal A of the comparison circuit 57, and is also input to the input terminal B of the comparison circuit 57 via the latch circuit 58. The latch circuit 58 is supplied with the clock φl and the comparison output signal of rA>BJ from the comparator circuit 57 as a latch clock via an AND circuit 59. The above comparison circuit 5
7 is input terminal A, Bl: r for input data.
A comparison is made between A<BJ and rA>BJ, and the output signal in the case of "A>BJ is inputted to the latch circuit 55 as a latch clock and also inputted to the AND circuit 59.81, and rA
A comparison output signal in the case of <BJ is input to the AND circuit 62. In addition, the clock φl is input to the AND circuit θl, 62, and its output signal is sent to the flip-flops 83 and 84.
It is input to the clock terminal CK of. Further, the flip-flop 63 is always given an 11" signal to its input terminal IN, and the output signal is the input terminal ■Nl of the flip-flop 64,
:Returned. The output signal of the flip-flop 64 is the clock φ3. It is input to the AND circuit 85 together with φLB, and the output signal of this AND circuit B5 is input to the reset terminal R of the flip-flop 83.84. Further, the output signal of the flip-flop 84 is input to the AND circuit 6B together with the clock φ3, and the output signal of the AND circuit 6B is sent to the latch circuit 5B as a latch clock.

In the above configuration, the latch circuit 51 has a
As shown in a>, data X, to X8 sent from the A/D conversion circuit 13 in units of line blocks are sequentially input. The latch circuit 51 sequentially latches the data of X, to x8 in synchronization with the clock φ1, and the subtracter circuit 52 .
Latch circuit 53. Comparison circuit 57. It is output to the latch circuit 58. Since the latch circuit 53 is given a latch clock via the AND circuit 54 at the timing of the beginning of each line block, it latches only the data of Xl output from the latch circuit 51. Then, the subtraction circuit 52 extracts the data X1 latched by the latch circuit 5B and the data X2 . X3. . . , performs a subtraction operation of lA−Bl, and outputs the subtraction result to the latch circuit 55. On the other hand, the comparison circuit 57 outputs data x1 sequentially output from the latch circuit 51.
．． x2r . That is, when the first data x1 is output from the latch circuit 51, since no data is latched in the latch circuit 58, "A>B" of the comparison circuit 57
The output of J becomes "1", a latch pulse is output from the AND circuit 59, and data x1 is latched into the latch circuit 58. Therefore, after that, the data x1 latched by the latch circuit 58 and the next data output from the latch circuit 51 are sequentially compared, and if data larger than data x1 is output, the comparison circuit 57 outputs "A>BJ". The output signal of the comparator circuit 57 becomes "1", and the data xi is latched in the latch circuit 58. In this way, the comparator circuit 57's rA>BJ
Each time a "1" signal is output from the output terminal of the latch circuit 58 (IQ clutch circuit) is updated, but at the same time, the output data of the subtraction circuit 52 is latched into the latch circuit 55 by the output signal of the comparison circuit 57. , the maximum deviation δl is latched in the latch circuit 55 when the processing for one line block is completed.

On the other hand, “1” is output from the A>B output terminal of the comparator circuit 57.
When the signal is output, the gate of the AND circuit 61 is opened, and the clock φ1 is input to the clock terminal CK of the flip-flop B3. As a result, a "1" signal is read into the flip-flop 63.

That is, when the data sent later becomes larger than the data latched in the latch circuit 58, the "1#" signal is latched in the flip-flop 63. When the human input signal becomes smaller than the latch data, a "1" signal is output from the A<B output terminal of the comparison circuit 57, and the gate of the AND circuit 82 is opened.As a result, the clock φl is transferred to the clock terminal CK of the flip-flop G4. The “1° signal inputted to the flip-flop 63 and held in the flip-flop 63 is read into the flip-flop B4. That is, when the input signal xi forms a certain extreme value, a "1" signal is shifted to the flip-flop B4, which opens the gate of the AND circuit 66 and sends the clock φ3 to the latch circuit 5G. Therefore, the maximum deviation held in the latch circuit 55 at this time is latched in the latch circuit 56 in synchronization with the clock φ3. As described above, each time an extreme value of input data is detected, the maximum deviation held in the latch circuit 55 is transferred to the latch circuit 56. As described above, the deviation data for the line block data x1 to x8 is obtained, and the initial value x1 held in the latch circuit 53 is
is sent to the ternary code converter 415, and the data held in the latch circuit 55 is changed to the maximum deviation δ1. The data held in the latch circuit 56 is sent to the recording circuit 17 as the maximum extreme value deviation δ2.

The ternary code conversion section 415 is configured as shown in FIG. 19. In the figure, 71 is a latch circuit to which the Y signal sent from the shift register 411 of FIG. 16 is input. The latch circuit 71 latches the input Y signal in synchronization with the clock φ1, and inputs it to the input terminal A of the addition circuit 73 and subtraction circuit 74 via the latch circuit 72. Further, the maximum deviation δ1 sent from the latch circuit 55 in FIG. In this case, the latch circuit 75 performs "δ1/8" processing for the maximum deviation δ1 by latching its upper three bits in synchronization with the clock φl. The addition output of the addition circuit 73 is input to the input terminal B of the comparison circuit 7B.
The subtraction output of the subtraction circuit 74 is input to the input terminal of the comparison circuit 77. In addition, the latch circuit 7 is connected to the input terminal A of the comparison circuit 7B and the input terminal C of the comparison circuit 77.
Data latched to 1 is input.

Comparison circuit 7B compares data input to input terminals A and B, outputs "1" when rA>BJ, outputs "0" when "A≦B", and inputs it to latch circuit 78. . Also,
The comparison circuit 77 compares the data input to the input terminal C1D, outputs "1" when rC>DJ, outputs "0" when "C≧D", and inputs the data to the latch circuit 78. This latch circuit 78 latches the comparison outputs of the comparison circuits 78 and 77 using the clock φ1, and latches data r01J, r
00J.

The data of "10" is output as 31 direct data y.

In this case, in the ternary data y, "01" is "1".

"00" corresponds to rob, and rlOJ corresponds to "-1".

The ternary code conversion unit 415 configured as described above performs the arithmetic processing shown in equation (2) above and outputs ternary data y of a 2-bit code. That is, shift register 4
When the Y signal is sent from 11, the data x1+X2+ .
1, the latch circuit 721 is shifted. Therefore, when the dot xi in the latch circuit 71 is latched now, the latch circuit 72 latches the dot xi-+ one dot before it. On the other hand, the latch circuit 75 latches δ1/8, and the adder circuit 73 latches rxL−t+(δl/8).
", and the subtraction circuit 74 performs the calculation "xi→-(δ1/8)J.

Now, if the signal difference between a certain dot xi and the previous dot xi→ is greater than +δ1/8, the output of the comparison circuit 7B becomes "1", the output of the comparison circuit 77 becomes "0", and the latch circuit 78 , data of ro 1 (+1) J is latched. Further, when the signal difference between a certain dot Xi and the previous dot dot 1 is smaller than -δ1/8, the output of the comparison circuit 7B becomes "0", the output of the comparison circuit 77 becomes "1", and the latch circuit 7B The data of rlO(-1)J is latched. Then, the signal difference between a certain dot xi and the previous dot x i-+ is smaller than +δ1/8, and -δ1
If it is larger than /8, both the outputs of comparison circuits 78 and 77 become "0", and the latch circuit 78 receives "00 (±0)".
data is latched. The 2-bit data latched by the latch circuit 7B as described above is sent to the recording circuit 17 in FIG. 1 as ternary data y.

Next, regarding the data synthesis circuit 25 that performs decoding processing based on the data compressed by the data compression circuit 16 in FIG. 1 or the data reproduced by the reproduction circuit 24,
The details will be explained with reference to FIGS. 21 to 24.

As shown in FIG. 21, the data synthesis circuit 25 includes a luminance signal synthesis circuit 81. It consists of a switching circuit 829 and a color difference signal synthesis circuit 83. The luminance signal synthesis circuit 8■ includes a reproduction circuit 2.
The ternary data y reproduced from the magnetic tape 23 by 4,
Initial value Xl of a certain line block.

Initial value x1' of next line block, maximum extreme value deviation δ2
is input. The luminance signal synthesis circuit 81 decodes the 6-bit Y signal from the input data, as will be described in detail later, and generates the gradation parameter σ reproduced by the reproduction circuit 24.
RY+ is input to the switching circuit 82 together with σB-Y.

The switching circuit 82 also receives a Y signal and a gradation parameter σR- from the data compression circuit 16 whose details are shown in FIG.
Y+σB−Y is given.

The switching circuit 82 selects and outputs the compressed data given from the data compression circuit te or the reproduction circuit 24 according to a control command from the control & timing circuit 3I.

The Y signal output from the switching circuit 82 is sent as is to the signal conversion circuit 27, and the gradation parameter σR−Y*σtoY is input to the color difference signal synthesis circuit 83. This color difference signal synthesis circuit 83 has a gradation parameter σR, as will be described in detail later.
-Y+ σB-Y decodes the R-Y and B-Y color difference signals and outputs them to the signal conversion circuit 27.

FIG. 22 shows details of the luminance signal synthesis circuit 81. The ternary data y sent from the reproduction circuit 24 is sent to the buffer 91, the initial value x1 of a certain line block is sent to the calculation section 93 via the buffer 92, and the initial value x1' of the next line block is sent directly to the calculation section 93. , the maximum extreme value deviation δ2 are input to the calculation unit 93 via the buffer 94. The Y signal written to the buffer 91 is transferred to the intermediate code creation section 9
5 in serial, and in parallel to determination section 96. The determination unit 9B uses the buffer 91
The ternary data y read into is all '12' or all '
-1m or all "0" is detected and outputted to the arithmetic unit 93.

The intermediate code creation unit 95 generates a signal from the ternary data y held in the buffer 91 to determine whether the maximum value P laX, the minimum value Pa1n, the upward elapsed point Ct, the downward elapsed point C↓, or Intermediate code Yi indicating 2
is created and output to the calculation section 93. For example, p wax is ill, Pln is 110. C↑ is 011.

C↓ is 010. Z creates a 3-bit code such as 000. The arithmetic unit 93 is equipped with a linear interpolation unit 97, which calculates Xi based on the outputs of the intermediate code generation unit 95 and determination unit 96.

In the above configuration, when the determining unit 98 determines that the ternary data y of one line block held in the buffer 91 is all "1" or all "-1",
As shown in FIG. 12, the calculation unit 93 calculates Xl and x, /
The intermediate point xi is found by simply dividing the distance between 2 and 2 into 8 equal parts and using the above equation (6). Further, when the determining unit 96 determines that the ternary data y is all "0", the calculating unit 93 calculates the intermediate point as xi ■ xl . When rO, 1, -IJ are mixed in the ternary data y held in the buffer 91, the outputs of the intermediate code creation section 95 and the judgment section 9B, as well as the reproduced data x1. From x1' and δ2, the maximum value Pmax and the minimum value Pa1n are determined as explained in FIG.
, upward transition point C↑, downward transition point C
↓, calculate the intermediate code Yi of 21 without going up or down. In this case, the linear interpolation unit 97 performs linear interpolation between C↑ and C↓ when C↑ or C↓ continues to obtain CTi.

Further, the color difference signal synthesis circuit 83 in FIG. 21 is as follows:
It is constructed as shown in FIG. In the same figure, 100
is a selector into which the 8-bit tone parameters σR-Y*σB-Y output from the switching circuit 82 are input.

The selector 100 performs a switching operation according to the switching signal R/B, and the ROM101.
The address of the ROM 102 is specified by the gradation parameter σB-Y. In this case, the selector 100 accesses the ROMs 101 and 102 using 7 bits of the 8-bit data excluding the sign bit (1 bit), and adds the sign bit as is to the output bits of the ROMs 10I and 102. In the ROM10I (102), a plurality of tables corresponding to gradation parameters are prepared in advance as shown in FIG. block information is read. And this RO
The 7-bit RY signal, B
- Decoded as a Y signal. ROMl01 as above
, 102, by adding a sign bit to the output of
Since the pattern read from ROM101, 102 can be inverted according to the sign, ROM10I, 102
The pattern stored in the memory can achieve its purpose with 1/2 of the required pattern.

As described above, the data synthesis circuit 25 synthesizes the Y signal, the RY signal, and the BY signal from the reproduced data, and sends them to the signal conversion circuit 27. This signal conversion circuit 27 creates R, G, and B color signals from the Y signal, RY signal, and BY signal from the data synthesis circuit 25, and displays them on the liquid crystal display panel 29 via the liquid crystal drive circuit 28. Drive. On the other hand, the audio signal reproduced by the reproduction circuit 24 is expanded into 10-bit audio data by the audio expansion circuit 2B.
/A conversion circuit 30 converts the signal into an analog signal. This analog signal is then sent to the speaker 32 via the switching circuit 19 and output as audio.

[Effects of the Invention] As detailed above, according to the present invention, a television signal is A/D converted in an image display device, and the A/D converted television signal is compressed to produce an audio magnetic tape. At the same time, during reproduction, a television signal having the amount of information required for a liquid crystal display is synthesized from the data reproduced from the magnetic tape and an image is displayed. Therefore, the apparatus can be significantly miniaturized.

Furthermore, since the luminance signal and color difference signal are separately parameterized during data compression, the luminance signal can be compressed with a sufficient amount of information, and the color difference signal can be significantly compressed.

Furthermore, the reproducibility can be improved by expressing luminance signals using parameters representing contours and parameters representing gradation, and the compression rate can be increased by expressing color difference signals only using parameters representing gradation. .

Furthermore, by using DAT' tape as the magnetic tape, the amount of information that can be recorded on the tape, the amount of information required for liquid crystal display, and the amount of information that can be compressed can be made almost equal, making it possible to put it into practical use. It is very effective in doing so.

In addition, means is provided for switching and displaying the received television signal and the reproduced television signal, and among the received television signals, the signal before parameterization is selected for the luminance signal, and the signal before parameterization is selected for the color difference signal. Since the converted signal is selected, image deterioration can be prevented and the number of signal lines of the switching means can be reduced.

Furthermore, for the color difference signal, which requires less information than the luminance signal, the R-Y signal and the B-Y signal are processed alternately in a time-sharing manner, so the circuit can be shared.
The circuit scale can be reduced.

[Brief explanation of the drawing]

The drawings show one embodiment of the present invention. Fig. 1 is a block diagram showing the overall circuit configuration, Fig. 2 is a diagram showing an example of the structure of one screen, and Fig. 3 is a line block in which the Y signal is divided. FIG. 4 is a diagram showing the color difference signal divided into blocks, and FIG. 5 is the R-Y signal and B-Y signal in each block.
FIG. 6 is a diagram showing the time division state of signals, FIG. 6 is a diagram for explaining the contour pattern creation operation, FIGS. 7 and 8 are diagrams for explaining the ternary data creation operation, and FIGS. 10th
The figure is a diagram for explaining the gradation parameter creation operation.
1, 12, and 13 are diagrams for explaining the reproduction operation of the luminance signal, FIG. 14 is a diagram for explaining the reproduction operation of the color difference signal, and FIG. 15 is a diagram showing details of the data compression circuit. A block diagram, FIG. 16 is a block diagram showing details of the luminance signal compression circuit, FIG. 17 is a block diagram showing details of the color difference signal compression circuit, FIG. 18 is a circuit diagram showing details of the shift data calculation section, FIG. 19 is a block diagram showing details of the ternary code conversion section, FIG. 20 is a timing chart for explaining the operation of the color difference signal compression circuit, and FIG. 21 is a block diagram showing details of the data synthesis circuit. FIG. 22 is a block diagram showing details of the luminance signal synthesis circuit, FIG. 23 is a block diagram showing the configuration of the color difference signal synthesis circuit, and FIG. 24 is a block diagram showing the configuration of the color difference signal synthesis circuit.
It is a figure showing an example of table composition of OM. 14... Multiplexer, 1B... Data compression circuit, 17... Recording circuit, 22... Magnetic head section, 24
...Reproduction circuit, 25...Data synthesis circuit, 2B...
・Audio expansion circuit, 27...Signal conversion circuit, 3i...
Control & timing circuit, 41... Brightness signal compression circuit,
411...Shift register, 412...Several person deviation calculation unit, 41'3...Maximum extreme value deviation calculation unit, 414...
・Shift data calculation unit, 415... Ternary code conversion unit, 4
2... Color difference signal compression circuit, 421... Adder circuit,
422...RY block memory, 423...B-
Y block memory, 424, 428, 427, 4
213... Selector, 43... Contour pattern extraction unit, 44... Gradation parameter extraction unit, 52... Subtraction circuit, 57... Comparison circuit, 73... Addition circuit, 74...
...Subtraction circuit, 78.77...Comparison circuit, 91.92
．． 94... Buffer, 93... Arithmetic unit, 95...
Intermediate code creation section, 9B... Judgment section, 97... Linear interpolation section. Applicant's agent Patent attorney Takehiko Suzue Figure 2 Figure 3 Figure 41 Figure 5 Figure 6 Figure 7 Figure 8 Figure 10 Figure 12 1+1 x'
Figure 13 Figure 14 Theta, pressure rice 1 end slow 16 Figure 15 LQ > Shi height 1? Sword [Dy[81st 22nd 1.
J Color difference sale 18 eight problems 83 Figure 23 OM Figure 24i3

Claims (8)

[Claims] (1) a television signal supply means; a means for A/D converting the television signal supplied by the means; and a data compression means for compressing the television signal digitized by the A/D conversion means; A means for recording compressed data on an audio magnetic tape, a means for reproducing the data recorded on the magnetic tape, a data synthesis means for synthesizing a digital television signal from the reproduced data, and a synthesized digital television signal. 1. An image display device comprising: image display means for displaying an image based on a television signal. (2) The image display device according to claim 1, wherein the data compression means separately parameterizes the luminance signal and color difference signal of the television signal. (3) The image according to claim (2), wherein the data compression means parameterizes the luminance signal as a parameter representing an outline and a parameter representing a gradation, and parameterizes the color difference signal as a parameter representing a gradation. Display device. (4) The data compression means includes means for parameterizing the television signal, and the data synthesis means includes means for storing a synthesized signal corresponding to the parameters. Image display device. (5) The image display device according to claim 1, wherein the recording means and the reproducing means are recording and reproducing means of a DAT (digital audio tape recorder). (6) A switching means for switching between a signal supplied from the television signal supply means and a signal reproduced from the magnetic tape by the reproduction means and supplying the same to the image display means; Claim 1: Among the signals, a signal A/D converted by an A/D conversion means is selected for a luminance signal, and a signal compressed by a data compression means is selected for a color difference signal.
) image display device. (7) The A/D conversion means, the data compression means, and the data synthesis means process the RY signal and BY signal of the color difference signal alternately in a time-sharing manner. Image display device. (8) The image display device according to claim (1), wherein the image display means is a liquid crystal display means.