JPH0830509A - Data storage device - Google Patents

Abstract

PURPOSE:To share a picture memory by an MTSC system and a PAL system. CONSTITUTION:In the PAL system, a 7/8 conversion circuit 114 omits one lower bit from 8-bit luminance data to obtain 7 bits and successively fill 8 bits. In the NTSC system, the circuit 114 outputs the luminance data as they are. Each of 6/4 conversion circuits 116, 118 distributes 6-bit input data into 4-bit data independently of these systems. Outputs from the circuits 116, 118 are impressed to a selector 120 as 8-bit data obtained by arranging the outputs from the circuits 116, 118 respectively on the upper digits and the lower digits. The selector 120 supplies either one of the 8-bit data from the circuit 114 and the 8-bit data from the circuits 116, 118 to a memory 24a and supplies the other to a memory 24b. Data read out from the memories 24a, 24b are reversely converted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data storage device, and more particularly to a data storage device for storing data having different bit widths.

[0002]

2. Description of the Related Art This type of apparatus is used, for example, in a still video recording / reproducing apparatus for recording / reproducing still images.
With a still video recording / playback device, a 2 inch still
Using a video floppy as a recording medium, one track of 50 tracks and one field of video signal can be analog-recorded on one track.

Further, a structure in which an analog image signal is digitized, temporarily stored in an image memory, the image data read from the image memory is converted back into an analog signal, and reproduced and output is put into practical use.

[0004]

For example, it is assumed that a memory element whose access unit is 8 bits long is used as an image memory and a luminance signal is stored in 8 bits and a color signal is stored in 6 bits. In the case of the NTSC system, assuming that the actual video signal portion of the frame video signal is sampled at (53 μs / 1 horizontal line) × 485 lines, the required memory capacity is 4 Mbi.
t (4,194,304 bit) or less, 4M-D
A memory system can be constructed with one RAM or four 1M-DRAMs. However, in the PAL system, assuming that the actual video signal portion of the frame video signal is sampled at (52 μs / 1 horizontal line) × 565 lines, the required memory capacity is about 4,600,000 bits, which is 4
A memory system could not be constructed with one M-DRAM or four 1M-DRAMs.

An object of the present invention is to provide a data storage device which can be shared by the NTSC system and the PAL system.

Another object of the present invention is to provide a data storage device that efficiently stores data having a bit length that does not match the unit bit length of a memory device.

[0007]

A data storage device according to the present invention comprises a storage means for storing data, and a bit width of input data to be stored in the storage means that does not match the bit width of the storage means. First bit width conversion means for adapting the input data to the bit width of the storage means, and second for converting data read from the storage means in bit width units of the storage means into a predetermined bit width. And a bit width conversion means of.

[0008]

By the above means, data having a bit width that does not match the bit width of the storage means can be efficiently stored in the storage means without waste. As a result, the same memory system can be shared by data having different numbers of data, such as the NTSC system and the PAL system.

[0009]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows a schematic block diagram of an embodiment of the present invention applied to a still video recording / reproducing apparatus, in which a reproducing system and a recording system are shown together.

First, the operation of the recording system will be described. A video signal to be recorded is input to the external input terminal 10.
The Y / C separation circuit 12 separates the video signal input from the input terminal 10 into a signal Y + S (a luminance signal on which a synchronization signal is superimposed) and a signal C. The signals Y + S and C separated by the Y / C separation circuit 12 are A / D via a switch 14Y that selects one of the signals Y + S and a similar signal Y + S of the reproduced video signal.
It is applied to the converter 16Y and the sync separation circuit 18, and Y
The signal C separated by the / C separation circuit 12 is a switch 1 for selecting one of this signal and the similar signal C of the reproduced video signal.
It is applied to the A / D converter 16C and the black and white discrimination circuit 20 via 4C.

The A / D converters 16Y and 16C convert the signals Y + S and C from the switches 14Y and 14C into digital signals and apply them to a digital signal processing circuit (DSP) 22. A frame memory including a first memory 24a and a second memory 24b is connected to the DSP 22, and the memory 2
4a and 24b are used for freezing an external video signal or a reproduced video signal, and are also used for superimposing a character image or the like.

The sync separation circuit 18 separates the composite sync signal from the signal Y + S, further separates the horizontal sync signal HD and the vertical sync signal VD, and applies them to the video discrimination circuit 26 and the system control circuit 28. Video discrimination circuit 26
Determines from the signals HD and VD from the sync separation circuit 18 whether or not the signal to be processed is a video signal, and outputs the determination result to the system control circuit 28. The black and white discrimination circuit 20 discriminates whether the video signal is a black and white signal or a color signal from the chroma signal C from the switch 14C, and outputs the discrimination result to the system control circuit 28.

The system control circuit 28 includes a sync separation circuit 1
The DSP 22 is controlled in accordance with the signals HD, VD from the signal No. 8, the discrimination result of the video discrimination circuit 26, and the discrimination result of the monochrome discrimination circuit 20. As is well known, the DSP 22 can cause its various timing signals to follow an external synchronization signal (a composite synchronization signal separated from an external input video signal, a composite synchronization signal separated from a reproduced video signal, or a PG signal). it can. It is also possible to run by itself (free run). The system control circuit 28 uses the video signal discrimination circuit 2
According to the discrimination result of 6 and the discrimination result of the monochrome discrimination circuit 20,
When it is determined that the signal being processed is a color image signal, the DSP 22 is instructed to cause the external synchronization signal to follow the operation timing and freeze the image signal. The trigger for the freeze is given by the user operating a predetermined switch of the operation device 44, and in response to this, the system control circuit 28 applies a freeze start control signal to the DSP 22.

The DSP 22 independently controls the memories 24a and 24b, and freezes the data obtained by digitally processing the input image data to the memories 24a and 24b. The details of this operation will be described later. When the writing to the memories 24a and 24b is completed, the DSP 22 stops following the external synchronization signal and enters the free-running mode. In this self-propelled mode, DSP2
2 reads the stored data from the memories 24a and 24b at a predetermined speed and applies it to the D / A converters 32Y and 32C, respectively.

The signals digital-to-analog converted by the D / A converters 32Y and 32C are added by an adder 34 to be a video signal, and when selected by a switch 36, they are added via an adder 38 and a video output terminal 40. Output to the outside. The adder 38 has a character generator (C
The output of G) 42 is applied, and the CG 42 generates an image signal of a designated character according to the control signal of the system control circuit 28. The adder 38 superimposes a specified character or the like on the video signal to be output from the video output terminal 40.

The output of the CG 42 is also applied to the DSP 22, and the DSP 22 converts the image data supplied from the A / D converters 16Y and 16C into a character image from the CG 42 according to a control signal from the system control circuit 28. It is also possible to write the image data on which is superimposed in the memories 24a and 24b.

When the frozen images in the memories 24a and 24b are desired to be recorded on the still video floppy, the user presses the record button of the operation device 44. When the record button is pressed, the system control circuit 28 outputs a message indicating the start of the recording operation to the display device 46 such as a liquid crystal display device and / or the external video output. When the user acknowledges this and presses the confirmation button, the recording operation is started.

When the recording operation is started, the system control circuit 28 first drives the drive circuit 48 and the motor 50 to move the floppy disk 52 at a constant angular velocity during one vertical period of the video signal.
Rotate. The PG detection circuit 54 detects the rotation phase of the floppy and supplies the PG signal to the system control circuit 28. The system control circuit 28 also moves the recording / reproducing head to the track to be recorded.

The system control circuit 28 includes a floppy 52
When the rotation of is stable and recording on the floppy 52 is possible, the DSP 22 is instructed to start recording. In response to this, the DSP 22 generates a composite sync signal to be added to the Y output, following the PG signal so as to match the still video format. In addition, the digital color signals read from the memory 24a or the memory 24b are color-difference line-sequentialized and the RY signal and the BY signal are alternately output to the D / A converter 32C every other horizontal period.

The FM modulation circuit 58 includes a D / A converter 32Y.
The signal Y + S output from the DSK modulation circuit 62 is pre-emphasized and then FM-modulated. The ID signal output from the system control circuit 28 is DPSK modulated.
The adder 64 adds the outputs of the FM modulation circuits 58, 60 and 62 and applies the result to (the recording amplifier of) the recording / reproducing amplifier 56. As a result, the frozen images in the memories 24a and 24b are recorded in the floppy 52. In the case of frame recording, the head is moved to the adjacent track and recording is performed again.

Next, the operation during reproduction will be described. The system control circuit 28 first causes the drive circuit 48 and the motor 50 to rotate the floppy 52 once at a constant angular velocity during one vertical period of the video signal. The PG detection circuit 54 detects the rotation phase of the floppy and outputs the PG signal to the system control circuit 28.
Supply to. The system control circuit 28 also moves the recording / reproducing head to the recorded track of the image to be reproduced. When the rotation of the floppy 52 is stabilized, the reproducing amplifier of the recording / reproducing amplifier 56 is turned on and the reproducing signal is read from the floppy 52. The reproduction signal is separated by the filter 66 into an FM modulation luminance signal, an FM modulation line sequential color difference signal and a DPSK modulation ID signal. The FM-modulated luminance signal and the FM-modulated line-sequential color-difference signal, which have been separated, respectively
FM demodulation and de-emphasis are performed by the demodulation circuit 70 and applied to the switches 14Y and 14C. Further, the separated DPSK modulation ID signal is sent to the DPSK demodulation circuit 72.
And is applied to the system control circuit 28.

The reproduction output of the recording / reproducing amplifier 56 is also applied to the RF detecting circuit 74. The RF detection circuit 74 determines whether the track being reproduced has been recorded or not, and outputs the determination result to the system control circuit 28.

The outputs of the FM demodulation circuits 68 and 70 are applied to the DSP 22 via the switches 14Y and 14C and the A / D converters 16Y and 16C. In this case, the DSP 22 operates in synchronization with the sync signal included in the output of the A / D converter 16Y, and noise reduction processing, dropout compensation, and color difference line simultaneous output are performed on the outputs of the A / D converters 16Y and 16C. Then, the data is written into the memories 24a and 24b. When reproducing a frame-recorded image, the same operation is repeated for adjacent tracks, and the image data of the second field is also written in the memories 24a and 24b.

When the writing to the memories 24a and 24b is completed, the system control circuit 28 stops the rotation of the floppy 52, and the DSP 22 switches to the free-running mode.
Data stored in the memories 24a and 24b are repeatedly read at a predetermined rate. The image data read from the memories 24a and 24b becomes a video signal by the D / A converters 32Y and 32C and the adder 34, selected by the switch 36, and applied to the adder 38. The adder 38 superimposes the character image generated by the system control circuit 28 on the CG 42 on the reproduced image, and outputs the superimposed image to the output terminal 40.

Also, as a function at the time of reproduction, there is a multi-screen display function. For multi-screen display, DSP22
Is 1 / n of the reproduced image data in the horizontal method and in the vertical direction.
(N is an integer) and the memories 24a and 24b are sampled.
Write in. As a result, one screen is 1 / n vertically and horizontally
And is frozen in the memories 24a and 24b.
By repeating this process n times, n × n images are frozen in the memories 24a and 24b.

Next, the memories 24a, 2 by the DSP 22
The control and digital signal processing of 4b will be described in detail.
The memories 24a and 24b are composed of exactly the same memory device,
262,144 words x 4 bits, or 1
M-bit FIFO (First-In First-
Out) has a memory configuration in which two memories are connected in parallel. Therefore, the memories 24a and 24b are
It functions as a memory of 44 words × 8 bits, and the total memory capacity becomes 4 Mbits. The DSP 22 has a write enable signal WE, a read enable signal RE, a reset write signal RSTW, and a reset read signal RS.
TR controls writing and reading of the memories 24a and 24b.

FIG. 2 shows the data arrangement in the memories 24a and 24b when storing the frame video signal. The vertical direction indicates an address, and the address value decreases toward the top. The horizontal direction indicates the data bits, and the higher the bit, the higher the bits. In each memory 24a, 24b,
8-bit data is stored in one address.

In the memory 24a, the luminance data Yo of the odd field is written from the head address, and then the color difference data R-Ye and B-Ye of the even field are written in the lower and upper levels of the same address. In the memory 24b,
Color difference data R-Yo of odd field from the start address
B-Yo is written in the lower and upper bits of the same address, and then the even field luminance data Ye is written.

FIG. 3 shows the memory 2 in the DSP 22.
4 shows a schematic block diagram of a writing system for 4a and 24b. Note that the DSP 22 can be adapted to both the NTSC system and the PAL system with a change by setting the register and changing the clock frequency. Since such a configuration is well known, detailed description thereof will be omitted. A / D of Figure 1
The converters 16Y and 16C quantize the luminance signal into 8 bits and the line-sequential C signal into 6 bits. The sampling rate is 4 fsc (fsc is the color subcarrier frequency). The output of the A / D converter 16Y is input to the Y pre-processing circuit 110, and the output of the A / D converter 16C is input to the C pre-processing circuit 112 for pre-processing.

In the case of a floppy reproduced video signal, the Y preprocessing circuit 110 functions as a delay line of 1V (vertical synchronization period) to reduce noise, and 1H (horizontal synchronization period).
Function as a delay line for compensating for dropout and performing aperture correction. C preprocessing circuit 112
Functions as a 1H delay line, simultaneously synchronizes the color difference line sequential signals, and separately outputs the RY signal and the BY signal. The preprocessed signal has its high frequency removed by low-pass filtering, and then the data rate is thinned out from 4 fsc to fsc.

The 8-bit luminance data pre-processed by the Y pre-processing circuit 110 is applied to the 7/8 conversion circuit 114, and C
As for the color data pre-processed by the pre-processing circuit 112, 6-bit BY data is applied to the 6/4 conversion circuit 116 and 6-bit RY data is applied to the 6/4 conversion circuit 118. P
When the AL system video signal is frame-stored, the 7/8 conversion circuit 114 truncates the lower 1 bit of the 8-bit input data to 7 bits, and sequentially stuffs it into 8 bits according to the memory configuration. . That is, the 7/8 conversion circuit 1
The 14 converts the 7-bit data into 8-bit data by sequentially packing the 7-bit data into 8 bits. NTS
When the C format video signal is frame-stored, the 7/8 conversion circuit 114 outputs the 8-bit input data as it is. Further, the 6/4 conversion circuits 116 and 118 are NTSC.
Regardless of the system or the PAL system, 6-bit input data is re-divided into 4-bit data and output. The specific bit is not deleted. This will increase the data rate by a factor of 1.5. Conversion circuits 114, 116, 118
Details of will be described later.

The 8-bit data output from the 7/8 conversion circuit 114 is applied to the selector 120, and the 4-bit data of the 6/4 conversion circuits 116 and 118 is output from the 6/4 conversion circuit 116 (B- Y data) is applied to the selector 120 as 8-bit data in which the output (RY data) of the 6/4 conversion circuit 118 is placed in the upper order and the output (RY data) is placed in the lower order.
The selector 120 outputs one of these two 8-bit data to the memory 2 depending on the field timing.
4a and the other to the memory 24b. For example, the selector 120 writes the luminance data to the memory 24a and the color data to the memory 24b in the odd field so that the selector 120 writes the luminance data to the memory 24a and the color data to the memory 24a in the even field. Can be switched as described above. Of course, DSP22
Writing of the memories 24a and 24b is controlled by the control signals RSTW and WE.

FIG. 4 shows the memory 2 in the DSP 22.
4 shows a schematic block diagram of a reading system from 4a and 24b. The DSP 22 controls the reading of the memories 24a and 24b by the control signals RE and RSTR signals. The data read from the memories 24a and 24b is the selector 13
Applied to zero. The selector 130 is switched according to the content of the input data (luminance data or color data), supplies the luminance data to the 8/7 conversion circuit 132, and the upper 4 bits of the color data are 4/6 conversion circuit 134. Then, the lower 4 bits are supplied to the 4/6 conversion circuit 136.

The 8/7 conversion circuit 132 is the 7/8 conversion circuit 1
This is a circuit for performing the reverse processing of 14, and in the case of a PAL system video signal, 8-bit input data is rearranged into 7 bits and output, and in the case of the NTSC system, the input data is output as it is. Details of the 7/8 conversion circuit 114 will be described later.

The 4/6 conversion circuits 134 and 136 are circuits for performing the reverse processing of the 6/4 conversion circuits 116 and 118.
The bit input data is rearranged into 6 bits and output.
The data rate will again be fsc. Details of the 4/6 conversion circuits 134 and 136 will be described later.

In this way, the luminance data Y and the color data RY and BY are returned to the data structure before writing in the memories 24a and 24b, and the Y post-processing circuit 1 respectively.
38 and C and post-processed by the C post-processing circuit 140 and applied to the D / A converters 32Y and 32C.

FIG. 5 shows a circuit diagram of the 7/8 conversion circuit 114. IN0, IN6, ..., IN0 are bits in order from the upper bits of the input data (here, Y data), and OUT7, OUT6, ..., OUT0 are bits in order from the upper bits of the output data. . The clock frequency of the D flip-flop is 4 fsc. This 7/8 conversion circuit 114 controls the control signals BIT87, DSG, CQW.
(3) (Meaning of three of CQW2, CQW1, and CQW0). The signal DSG is L when the multi-screen freezes and is H otherwise. BIT87
Is L when a PAL video signal frame is stored, and is H otherwise.

CQW (3) is generated by the timing generation circuit shown in FIG. The timing generation circuit shown in FIG. 6 is composed of three 3-bit binary counters,
The clock frequency of the D flip-flop is 4 fsc, the signal DSG is normally H, the signals NBLKW, NBC
KRY and NBLKRC are signals that become H in the actual video portion of the video signal and become L in other portions (for example, the horizontal blanking period and the vertical blanking period). The system control circuit 28 uses the signals NBLKW and NBCKR.
The timing when Y and NBLKRC become H can be adjusted freely. If the signals NBLKW, NBCKRY, and NBLKRC are all L, the count value of each counter becomes 0. Signals NBLKW, NBCKRY, NBLKRC are all H
When the signal DSG is H, each counter counts up and changes in the range of 0 to 7, and when the signal DSG is L, it holds the count value.

Note that CQ (3) (specifically, CQW (3), CQRY (3), and CQRC which will be described later)
FIG. 7 shows a correspondence table of the count value of (3)) and the corresponding symbols.

The 7/8 conversion circuit 114 shown in FIG. 5 is basically composed of an output D flip-flop and a selector for selecting its input. Each of the 7/8 conversion circuits 114 corresponds to a decode value of CQW (3). The selector switches between the input INn and the input INn-1 delayed by one clock.
However, when the signal DSG is L, all D flip-flops hold the previous value.

A timing chart when the signal DSG is H and the signal BIT87 is L is shown in FIG. CQW (3)
Is a counter of 0 to 8, so the 7/8 conversion circuit 11
4 (FIG. 5) operates with 8 clocks as one basic unit. The count value of CQW (3) is coded according to the correspondence table shown in FIG. The symbol itself is shown in parentheses to indicate the value itself. Input data Dx is CQW
When (3) = x, it indicates that the data is input to the input IN (7). In FIG. 5, when the signal BIT87 is L, IN0 is not selected, so that the input data Dx is actually 7-bit data. In FIG. 8, {7x, 6x, 5x, 4x, 3x are arranged in order from the upper bits. , 2x, 1
x} (however, x = a to h).

In FIG. 5, OUT7 is L7 latched twice, and OUT0 is L1 latched once. Therefore, in FIG. 8, OUT7
Is IN7 delayed by 3 clocks, OUT0 is IN1
Is delayed by 2 clocks. OUT6 to OUT1
With respect to the above, each selector is switched according to the decode value of CQW (3), and becomes as shown in FIG. WEY is a write enable signal for the memory into which Y data is written, and is generated according to the decode value of CQW (3). Similarly to the Y data, the write enable signal WEY is switched by a selector (not shown) and applied to the memory 24a or the memory 24b. Signal WEY is CQ
When W (3) is a, it becomes L.

The clock of the memories 24a and 24b is 4fs.
c, the phase is 180 degrees out of phase with the DSP 22, and the delay of the selector 120 (FIG. 3) is so small that it can be ignored. Therefore, the table shown in FIG. 8 can be the memory map itself. Output data OU when signal WEY is L
T (8) a is not written in the memories 24a and 24b. However, 7f to 1f are written with CQW (3) = h, and 1g is written with CQW (3) = b.

As described above, the data of 7 bits × 8 words is converted into 8 bits × 7 words within 8 clocks and written in the memory 24a or 24b.

When the signal BIT87 is H, the input I
N0, IN7, ..., IN1 are output as they are.
That is, OUT (8) is {IN0, IN7, ..., IN
1}. At this time, the signal WEY always becomes H.

A circuit diagram of the 8/7 conversion circuit 132 is shown in FIG. The Y data read from the memories 24a and 24b are IN7, IN6, ...
Input to N0. Also, OUT7, OUT6, ...
OUT0 is each bit in order from the higher order of the output data after conversion. Clock frequency of D flip-flop is 4fs
c. This conversion circuit 118 has a control signal BIT8.
7, CQRY (3) (CQRY2, CQRY1, CQR
It is controlled by three meanings of Y0). BIT8
Similar to the case of FIG. 5, 7 is L when the frame storage data of the PAL system video signal is read, and H otherwise. CQRY (3) is also generated by the timing generation circuit shown in FIG.

The 8/7 conversion circuit shown in FIG. 9 is basically composed of an output D flip-flop and a selector for selecting its input, and each selector is selected according to the decoded value of CQRY (3). However, the input INn is switched between data latched by 4fsc inversion and data delayed by one clock.

Timing when signal BIT87 is L
The chart is shown in FIG. The notation is the same as in FIG. 8, and the input data Dx is as follows when CQRY (3) = x.
The data is input to the input IN (8).
Input data Dx = {7x, 6x, 5x, 4x, 3x, 2
x, 1x} (where x = a to h).

The delay of the selector 130 (FIG. 4) can be ignored, and the clocks of the memories 24a and 24b are 180 degrees out of phase with the DSP 22. Therefore, Dx is CQRY (3) =
It can be interpreted as read data from the memories 24a and 24b at the time of x. REY is a memory 24a, 24
This is a read enable signal for reading the Y data from b, and is generated according to the decoded value of CQRY (3). Similarly to the Y data, the read enable signal REY is also switched by the selector (not shown) and the memory 2
4a or 24b. Signal REY is CQRY
When (3) is a, it becomes L.

Since the memory clock is inverted,
When CQRY (3) = a, the memories 24a and 24b are not read and Dh is held. Therefore, data of 8 bits × 7 words is stored in the memories 24a, 2 within 8 clocks.
4b will be read.

As can be seen from FIG. 9, when the signal BIT87 is L, OUT0 is always L. That is, the output is 7-bit data. In FIG. 10, each bit value of OUT (8) is shown together with the time change. For example, CQRY
When (3) = b, the decode values of CQRY (3), which are the switching signals of the seven selectors, are all H, and Ln
-1 is selected. Therefore, OUT (8) c = {6h,
5h, 4h, 3h, 2h, 1h, 0h, L). When CQRY (3) = c, all the decoded values of CQRY (3) become L, and INn is selected. Therefore,
OUT (8) d = {7b, 6b, 5b, 4b, 3b, 2
b, 1b, L). At other times as well, it becomes as shown in FIG. In this way, data of 8 bits × 7 words is converted into 7 bits × 8 words.

When BIT87 is H, OUT (8) =
{L6, L5, L4, L3, L2, L1, L0, L7)
Becomes In 7/8 conversion before writing to memory, BIT8
When 7 is H, OUT (8) = {IN0, IN7, ...
., IN1}, so 8/7 after memory read
The output OUT (8) of the conversion is eventually {IN7, IN6,
..., IN1, IN0} (where INn is the input of the 7/8 conversion circuit 114), and 7 when BIT87 is H.
It can be seen that the / 8 conversion and the 8/7 conversion were performed correctly.

Further, when BIT87 is L, 7/8
Verify the transformation and its inverse. The verification result is shown in FIG. FIG. 11 shows CQRY (3) and 8/7 conversion circuit 132.
The output OUT (8) of FIG.
OUT of FIG. 8 is set to N (8) (memory read data).
(8) Created by substituting (memory write data). The output O of the 8/7 conversion circuit 132 in FIG.
In the table of UT (8), the subscript is the value of CQW (3), the input of the 7/8 conversion circuit 114 and the 8/7 conversion circuit 1
It is also a correspondence table of 32 outputs. Since the signals WEY and REY for CQW (3) and CQRY (3) are the same, regarding the time, the relationship between the memory write timing of the output of the 7/8 conversion circuit 114 and CQW (3), and the 8/7 conversion. The relationship between the memory read timing of the input of the circuit 132 and CQRY (3) may be associated.
In this way, the original series signal is restored by the 7/8 conversion and the 8/7 conversion.

FIG. 12 shows 6/4 conversion circuits 116 and 118.
3 is a detailed circuit diagram of FIG. IN5, IN4, ..., IN
0 is each bit in order from the high-order bit of C (BY or RY) data, and OUT3, OUT2, OUT1, O
UT0 is each bit of C data output. The clock frequency of the D flip-flop is 4 fsc. The 6/4 conversion circuit shown in FIG. 12 is controlled by control signals CQW (3) and DSG. The signal DSG is L as in the case of the multi-screen freeze, and H in the other cases, as before.

The basic operation of the 6/4 conversion circuit shown in FIG. 12 is the same as that of the 7/8 conversion circuit and 8/7 conversion circuit described above, and the input and the latch output are selected by the decode value of CQW (3). And output it. However, the data rate is fsc.

A timing chart when the signal DSG is H is shown in FIG. The notation is the same as in FIG.
The input IN (6) has a rate of fsc and CQW (3) is d.
Or it changes when h. Latches L1 and L0 are CQW
When (3) is d or h, the data is held. When CQW (3) is d, the selector selects {L
1, L0, In1, IN0}, otherwise,
Select {IN5, IN4, IN3, IN2} from the upper bits. As a result, the output as shown in FIG. 13 is obtained.

WEC is a write enable signal for the memory in which C data is written, and is generated according to the decode value of CQW (3). The write enable signal WEC is also the same as the write enable signal WEY.
It is switched by a selector (not shown) so that the C data is applied to the memory 24a or the memory 24b to which the C data is to be written. The signal WEC becomes H when CQW (3) is c, f or g.

The clock of the memories 24a and 24b is 4fs.
Since c is an inverted version of c, the output when CQW (3) is c, f, or g is the memory 24a or 24.
written to b. Therefore, the memory 24a or the memory 24b
From the upper bit to {B-Y5h, BY-h4h, B
-Y3h, BY-h2h, R-Y5h, R-Y4h, R-
Y3h, R-Y2h}, {B-Y1h, B-Y0h, B
-Y1d, B-Y0d, R-Y1h, R-Y0h, R-
Y1d, R-Y0d}, and {B-Y5d, B-Y4
d, BY3d, BY2d, RY5d, RY4
In the order of d, R-Y3d, R-Y2d}, data is written only 3 times within 8 clocks. As a result, the data of 6 bits × 2 words is converted into the data of 4 bits × 3 words.

FIG. 14 shows a circuit diagram of the 4/6 conversion circuits 134 and 136. The C data read from the memories 24a and 24b are IN3, IN2, I
Input to N1 and IN0. Also, OUT5, OUT4
.., OUT0 are each bit in order from the higher order of the converted C (RY or BY) output data. The clock frequency of the D flip-flop is 4 fsc. The conversion circuits 134 and 136 are controlled by the control signal CQRC (3). CQRC (3) is also generated by the timing generation circuit shown in FIG.

A timing chart of the 4/6 conversion circuit shown in FIG. 14 is shown in FIG. The notation is the same as before. The input data Dx is data read from the memory 24a or the memory 24b when CQRC (3) = x. However, as described above, the memories 24a, 24
Since b is an inverted clock, the phase changes with a delay of 180 degrees in the DSP 22. The REC stores the C data in the memory 24a.
Alternatively, it is a read enable signal for reading from the same 24b and is generated according to the decode value of CQRC (3). Similarly to the C data, the read enable signal REC is also the memory 24a or the memory 24a from which the C data should be read.
It is switched by a selector (not shown) so that it is applied to b.

Ln holds INn when CQRC (3) is d or h, and LLn holds INn when CQRC (3) is e. The upper 4-bit selector holds the value of Ln−2 when CQRC (3) is e. The lower 2 bits selector is CQR
When C (3) is a, LLn is held, and when CQRC (3) is e, INn is held.

As a result, the output OUT (6) is shown in FIG.
As shown in 5, the data of 4 bits x 3 words is 6
Converted to bits x 2 words.

When the 6/4 conversion and its inverse are verified, the result is as shown in FIG. FIG. 16 shows the output OUT (6) of the 4/6 conversion circuits 134 and 136 for CQRC (3).
Shows the table. FIG. 16 is created by substituting OUT (4) (memory write data) of FIG. 13 for IN (4) (memory read data) of FIG. Therefore, the output O of the 4/6 conversion circuits 134 and 136 in FIG.
In the table of UT (6), the subscript is the value of CQW (3), and it also serves as a correspondence table between the inputs of the 6/4 conversion circuits 116 and 118 and the outputs of the 4/6 conversion circuits 134 and 136. There is.

The correspondence between the memory read data and the memory write data is determined by the enable signals WEC and REC. That is, CQW (3) = c where the enable signal WEC becomes H corresponds to CQRC (3) = c where the enable signal REC becomes H, and CQW (3) = f is C.
Corresponds to QRC (3) = d and CQW (3) = g is CQR
The respective timings are associated so as to correspond to C (3) = g. In this way, 6/4 conversion and 4 /
By the 6 conversion, the original series signal is restored.

Next, the number of bits stored in the memory will be described.
By the 8/7 conversion and 6/4 conversion described above, PA
If one horizontal period of 52 μs × 565 lines is to be stored in the memory by controlling NBLKW in one frame of the L system video signal, the total amount of data is BIT.
When 87 is H, about 4,600,000 bit, BIT
When 87 is L, it becomes about 4,180,000 bits.
That is, when BIT87 is L, 4Mbit (4,1
94,304 bits). In the case of the NTSC system, the total data amount of 53 μs × 485 lines in one horizontal period is 4110,000 bits when BIT87 is H, which also fits in 4 Mbits.

In the case of multi-screen freeze, for example, n × n
In the multi-image of, the image data may be thinned to 1 / n,
In the 7/8 conversion circuit, 6/4 conversion circuit, and timing generation circuit, DSG can be set to H only once every n clocks. That is, in each case, if DSG is L, all D flip-flops retain the previous value,
Data can be thinned to 1 / n and written in the memories 24a and 24b. However, since the enable signals WEY and WEC generated by the decoded value of CQW (3) have a waveform extended n times as they are, D
SG is also decoded so that the enable signals WEY and WEC always become H only in one clock.

The system control circuit 28 receives the inputs of the timing generation circuit shown in FIG. 6, NBLKRY and NBLKRC.
The rising and falling edges of can be finely adjusted independently of the reproduction sync signal. That is, CQRY (3) and CQRC
(3) proceeds independently. As a result, the YC time difference generated by digital signal processing in the DSP 22 and the DSP 22
It is possible to absorb the YC time difference generated in the analog signal processing in the above in all modes.

In the above embodiment, the 7-bit data bus is converted into the 8-bit data bus and the inverse conversion is performed. However, in general, from the m-bit data bus to the n-bit data bus.
Obviously, it can be applied to the conversion to the bit data bus and vice versa.

In this embodiment, when the PAL video signal is frame-stored, by setting BIT 87 to L, Y data is converted to 7/8, and the number of words required to store the Y data in the memory is reduced to store the Y data in the memory. Store tightly in. As a result, it is possible to store the PAL video signal in a frame even with a 4 Mbit image scale.
A memory system that can be shared with the AL system can be realized.

Further, the C data can be read / written from / to the memory in the same unit as the Y data by performing the 6/4 conversion, so that the wasted unused memory space can be reduced.

The frame memory is divided into two identical blocks, Y data is written in one block, and C data is written in the other block, and this relationship is switched according to the field. Can be evenly distributed, and a 1 Mbi
A required memory capacity can be secured by using four t memories.

[0073]

As can be easily understood from the above description, according to the present invention, it is possible to efficiently store data having a bit length that does not match the unit bit length of the memory element, and to reduce the memory capacity. , Will be able to store more data.

Further, the PAL system frame image data can be stored in the NTSC system frame memory system, and a data storage device which can be shared by the NTSC system and the PAL system can be provided.

[Brief description of drawings]

FIG. 1 is a schematic block diagram of an embodiment of the present invention.

FIG. 2 is a data arrangement in memories 24a and 24b when a frame video signal is stored.

FIG. 3 is a schematic block diagram of a writing system for writing into memories 24a and 24b.

FIG. 4 is a schematic block diagram of a read system from the memories 24a and 24b.

5 is a circuit diagram of a 7/8 conversion circuit 114. FIG.

FIG. 6 is a circuit diagram of a timing generation circuit.

FIG. 7 is a correspondence table between CQ (3) and symbols.

FIG. 8 is a timing chart of 7/8 conversion.

9 is a circuit diagram of an 8/7 conversion circuit 132. FIG.

FIG. 10 is a timing diagram of 8/7 conversion.

FIG. 11 is a verification table of 7/8 conversion and its inverse conversion.

FIG. 12 is a circuit diagram of 6/4 conversion circuits 116 and 118.

FIG. 13 is a timing diagram of 6/4 conversion.

FIG. 14 is a circuit diagram of 4/6 conversion circuits 134 and 136.

FIG. 15 is a timing chart of 4/6 conversion.

FIG. 16 is a verification table of 6/4 conversion and its inverse conversion.

[Explanation of symbols]

 10: External Input Terminal 12: Y / C Separation Circuit 14Y, 14C: Switch 16Y, 16C: A / D Converter 18: Sync Separation Circuit 20: Monochrome Discrimination Circuit 22: Digital Signal Processing Circuit (DSP) 24a: Y Memory 24b : C memory 26: video discrimination circuit 28: system control circuit 32Y, 32C: D / A converter 34: adder 36: switch 38: adder 40: video output terminal 42: character generator (CG) 44: operating device 46: Display device 48: Drive circuit 50: Motor 52: Floppy 54: PG detection circuit 56: Recording / playback amplifier 58: FM modulation circuit 60: FM modulation circuit 62: DPSK modulation circuit 64: Adder 66: Filter 68: FM demodulation Circuit 70: FM demodulation circuit 72: DPSK demodulation circuit 74: RF detection circuit 110: Y preprocessing circuit 1 12: C pre-processing circuit 114: 7/8 conversion circuit 116, 118: 6/4 conversion circuit 120: selector 130: selector 132: 8/7 conversion circuit 134, 136: 4/6 conversion circuit 138: Y post-processing circuit 140: C post-processing circuit

Claims (1)

[Claims] 1. A storage means for storing data, and when the bit width of input data to be stored in the storage means does not match the bit width of the storage means, the input data is adapted to the bit width of the storage means. A first bit width conversion means, and a second bit width conversion means for converting the data read from the storage means in the bit width unit of the storage means into a predetermined bit width. Data storage device.