JPH0451789A - Video signal synthesizer for high vision vtr - Google Patents

Abstract

PURPOSE:To decrease the number of components and to realize complete overlap of video signals by using an A/D converter of a recording system having been provided to the synthesizer also for the A/D conversion of a video signal inputted externally. CONSTITUTION:An external input video signal is inputted from an input terminal 42 and fed to an A/D converter 44 for recording signal and external input signal used at recording but not used at reproduction via a changeover switch 43 turned to the position of synthesis in the synthesis mode, in which the signal is converted into a digital signal. In the synthesis mode, the external input video signal is fed to an input changeover section 71 via a changeover switch 45 closed and turned to the position of the synthesis in figure, and the signal is fed alternately to each shift register 57 of memory boards 47, 48 for each frame based on an input data switching signal. The shift register 67 converts the external serial input video signal from the input switching section 7a into a parallel signal and the signal after conversion is fed to a signal synthesis circuit 68.

Description

[Detailed Description of the Invention] [Industrial Field of Application] The present invention relates to high definition
The present invention relates to a signal synthesizing device for a VTR (VTR), and more specifically to a signal synthesizing device that synthesizes a high-definition video signal reproduced from a magnetic tape and a high-definition video signal input from an external source such as a television camera to form a composite image. It is something.

[Conventional technology]

A high-definition television system with significantly superior image and sound quality compared to conventional television systems has been developed, and is being put into practical use under the name Hi-Vision. The frequency band of a high-definition signal is five to six times that of the current NTSC signal, and in response to this, development of high-definition VTRs that enable high-density, wideband recording is underway. In order to record and reproduce broadband signals, a method has been adopted in which the bandwidth used by the tape head system of a VTR is widened and the signal is divided and recorded.

An example of a video signal processing section in a conventional high-definition VTR will be explained based on the block diagram of FIG. When recording a video signal, the video signal input through the input terminal 1 is converted to an A/D (analog/digital) converter 2.
The signal is converted into a digital signal and sent via the changeover switch 3 to the two memory boards 4 and 5 alternately, for example, every frame. And these memory boards 4 and 5
After performing shuffling, that is, processing to rearrange the time arrangement of video signal lines (scanning lines) within one frame, the signals are output from the memory boards 4 and 5 alternately, for example, every frame. After that, D/
A (digital/analog) converter 7 converts it into an analog signal, and the FM modulator 8 converts it into an analog signal.
The signal is M-modulated and recorded on a magnetic tape (not shown) by the magnetic head IO via the recording amplifier 9.

On the other hand, during reproduction, a video signal is reproduced from the magnetic tape by the magnetic head 10, amplified by the reproduction amplifier 11, further equalized by the equalizer 12, and then FM demodulated by the FM demodulator 13. Next, A/D comparator'-
A with TBC (time base collector) 14 with built-in time
After /D conversion and time axis error correction, the signals are sent alternately to the memory boards 4 and 5 via the changeover switch 3, where deshuffling, which is the opposite process to the above-mentioned shuffling, is performed. , the time arrangement of the lines of the video signal within one frame is restored. Subsequently, signals are alternately output from the memory boards 4 and 5 to the D/A converter 15 via the changeover switch 6, where they are converted into analog signals, and then sent via the output amplifier 16 and output terminal 17 to the TV, etc. Output to external device.

A more detailed configuration of the memory boards 4 and 5, which are shared during recording and playback, is shown in a block diagram in FIG. Each of the memory boards 4 and 5 includes an SPS (serial-parallel-serial) converter 18, a frame memory 19 (field memory may be used), and an address control circuit 20.

Line counter 22 in address control circuit 20
is the line number in one frame for address generation.
It is output to OM23 and ROM25 for synchronous addition control. The address generation ROM 23 calculates the starting address of the line based on the line number to the address counter 24.
supply to.

The initial value of the address counter 24 is set by this start address, and the address at which writing and reading are to be performed in the frame memory 19 is specified by the operation of the address counter 24. The synchronous addition control ROM 25 supplies a synchronous addition ROM control signal to the synchronous addition ROM 27 based on the above line number. The synchronization addition ROM27 is this synchronization addition R.
A specified synchronization signal is generated based on the OM control signal and the address supplied from the synchronization addition address counter 26.

Then, the frame memory 19 and the synchronization addition ROM 27 are switched by the RAM/ROM output enable signal, and the video signal and the synchronization signal are sequentially output to the SPS converter 18, thereby converting one line of video signal. Created. The SPS converter 18 converts the serial input signal into parallel and writes it into the frame memory 19, and the frame memory 19 and the synchronous addition ROM 27
The parallel signals read from the converter are converted into serial signals and output. As described above, shuffling or deshuffling is performed by once writing the video signal line by line into the frame memory 19 and reading out the predetermined portions in order.

Note that the SPS converter 18 in each memory board 4 and 5
Switching games 28a and 28b for inputting an input data switching signal and switching games 29a and 29b for inputting an output data switching signal are provided before and after the memory boards 4 and 5, respectively. Writing and reading are performed on the . That is, memory board 4
When a signal is written to the frame memory 19 of the memory board 5, the signal is read from the frame memory 19 of the memory board 5, and the signal is written to the frame memory 19 of the memory board 5.
When a signal is being written to frame memory 19 of memory board 4, the signal is read from frame memory 19 of memory board 4.

By the way, in the high-definition VTR as described above, as shown in FIG. It is conceivable to compose a composite image (2) by combining the image (2) based on a video signal (hereinafter referred to as a 2-playback video signal) reproduced from a magnetic tape 32 stored in a cassette of a high-definition VTR.

Fig. 8 shows a useless video synthesis circuit 30 that composes the composite image ■.
An example is shown below. This video synthesis circuit 30 is a D/A in FIG.
Since it is inserted between the converter 15 and the output amplifier 16, the analog playback video signal played from the magnetic tape 32 and output from the D/A converter 15 is sent to the analog switch 33 and the synchronous separation circuit 34. The synchronization separation circuit 34 separates the horizontal and vertical synchronization signals in the reproduced video signal. On the other hand, an external input video signal is input to the encoder 35. Also, encoder 35
The synchronization signal separated by the synchronization separation circuit 34 is input to the sync signal, the synthesis position is detected based on the presence or absence of an external input video signal, and the playback signal and the external input signal are switched by the analog switch 33 to output the output amplifier 16. A composite video signal is outputted through the video signal.

[Problem to be solved by the invention]

However, in the video synthesis circuit 30 described above, the synthesized video signal is generated by switching between the analog playback video signal and the analog external input video signal, so the circuit configuration of the encoder 35 and the like becomes complicated. Furthermore, since the same analog signals are combined, it is difficult to achieve complete superposition, resulting in a problem that the image quality of the combined image deteriorates.

[Means to solve the problem]

In order to solve the above-mentioned problems, a video signal synthesis device for a high-definition VTR according to the present invention converts an analog video signal into a digital video signal in order to record and reproduce one field of video signals by dividing them into a plurality of recording tracks. a shuffling circuit that converts the scan lines to a storage device such as a frame memory or a field memory, rearranges the time arrangement of the scanning lines and reads them from the storage device; and a deshuffling circuit that restores the rearranged time arrangement of the scanning lines and reads them from the storage device. In a video signal synthesis device for a high-definition VTR, the A/D converter is used both during recording and when synthesizing video signals, and converts an analog video signal input to the high-definition VTR into a digital video signal; A signal synthesis control circuit that generates and outputs sampling data from synthesis image data input externally and converted into a digital signal for synthesis with a reproduced image played on the high-definition VTR; and a signal synthesis control circuit. Input the above sampling data from , select the reproduced image data when the image data for synthesis and the data for sampling are equal, and select the image data for synthesis when the image data for synthesis and the data for sampling are not equal. The present invention is characterized in that it includes a signal synthesis circuit composed of, for example, a multiplexer and a digital comparator, which outputs the signal to the storage means.

[For production]

In the above configuration, an analog video signal input from an external device such as a high-definition television camera is converted into a digital video signal by an A/D converter in order to be combined with a reproduced image played on a high-definition VTR. . The signal synthesis control circuit generates sampling data in which each bit of the image element to be synthesized is inverted from the synthesis image data converted into a digital signal. The signal synthesis circuit inputs synthesis image data that has been input externally and converted into a digital signal, reproduced image data that has been reproduced and converted to a digital signal, and sampling data, and processes the synthesis image data and sampling data. Select the reproduced image data when they are equal, select the image data for synthesis when the image data for synthesis and the data for sampling are not equal,
Output to the storage means. The storage means is composed of, for example, a frame memory or a field memory, and stores, for each line (scanning line), composite data of reproduced image data and composite image data that are appropriately selected and output by the signal synthesis circuit.

The shuffling circuit and the deshuffling circuit rearrange the time arrangement of the composite data written in the storage means and sequentially read out the data.

As a result, one field of the combined video signal is divided into a plurality of recording tracks and recorded and reproduced.

According to the video signal synthesis device for a high-definition VTR according to the present invention, the A/D of the recording system originally provided in the device is
Since the converter is also used for A/D conversion of externally inputted video signals, it is possible to reduce the number of parts and is advantageous in terms of lowering costs. Also, since the video signal is converted into a digital signal and synthesized,
Complete superposition of video signals can be achieved.

〔Example〕

An embodiment of the present invention will be described below based on FIGS. 1 to 4.

As shown in FIG. 2, the recording system of the video signal processing unit in the high-definition VTR of this embodiment has an input input into which a video signal to be recorded on a magnetic tape 55 (hereinafter referred to as a recorded video signal) is input. It is equipped with a terminal 41 and an input terminal 42 into which a video signal from an external device such as a high-definition television camera (hereinafter referred to as an external input video signal) is input.The selector switch 43 is set to R in the figure during normal recording.
Switched to the EC side, the recorded video signal supplied from the input terminal 41 is sent to an A/D (analog/digital) converter 44 for recording signals and external input signals. Further, when combining the video signal reproduced from the magnetic tape 55 (hereinafter referred to as the reproduced video signal) and the external input video signal, the changeover switch 43 is switched to the combination side in the figure, and the input The external input video signal supplied from the terminal 42 is the same recording signal and external input signal A/D.
The signal is sent to a converter 44.

Furthermore, an A/D converter 44 for recording signals and external input signals
The video signals converted into digital signals are input to two memory boards 47 and 48 via changeover switches 45 and 46.

The output sections of the memory boards 47 and 48 are connected to a changeover switch 50 for switching between a recording system and a playback system.In the recording system after the changeover switch 50, a D/A (digital/analog )
A converter 51, an FM modulator 52 that performs FM modulation on the signal from the D/A converter 51, and a recording amplifier 53.
is connected, and the output of the recording amplifier 53 is connected to the magnetic head 54.
The information is recorded on the magnetic tape 55 by the following.

On the other hand, the reproduction system includes a reproduction amplifier 56 that amplifies the signal reproduced from the magnetic tape 55 by the magnetic head 54, an equalizer 57 that equalizes the amplified reproduction signal, and FM demodulates the equalized reproduction signal. FM demo simulator 58
and a TBC that has a built-in A/D converter for reproduced signals and performs A/D conversion of FM demodulated signals and correction of time axis errors.
(time base collector) 60. T.B.C.
The signal output from 60 is input to memory boards 47 and 48 via changeover switch 46.

Furthermore, in the reproduction system after the memory boards 47 and 48, a D/A converter 61 and an output amplifier 62 are connected, and the signal amplified by the output amplifier 62 is outputted to an external device such as a high-definition TV via an output terminal 63. It is now possible to do so.

Memory boards 47 and 48 shared during recording and playback
A more detailed configuration is shown in FIG.

The output of the changeover switch 46 is connected to the input changeover section 70. As a result, when the changeover switch 46 is switched to the PB side in the figure, the input switching unit 70 inputs the reproduced video signal to the SPS (serial-parallel-serial) converter 64 provided in each of the memory boards 47 and 48 and switches the input data. The signals are supplied alternately in frame units based on the signal. Further, when the changeover switch 46 is switched to the REC side in the figure, recording video signals are alternately supplied to each SPS converter 64 in frame units based on the input data switching signal.

On the other hand, the output of the changeover switch 45 is connected to the input switching section 71. As a result, when the changeover switch 45 is switched to the synthesis side in the figure, the input switching unit 71 frames the external input video signal to the shift register 67 provided in each of the memory boards 47 and 48 based on the input data switching signal. The units are supplied alternately.

The memory boards 47 and 48 each further include a frame memory 65 for subsequent iU and an address control circuit 66.
, a signal synthesis circuit 68 , and a signal synthesis control circuit 69 . The output of the address control circuit 66 is connected to the frame memory 65 and the SPS converter 64, and the output of the frame memory 65 is connected to the SPS converter 64. Further, the signal synthesis control circuit 69 and the shift register 6
The outputs of 7 are connected to a signal synthesis circuit 68, and the output of the signal synthesis circuit 68 is connected to a frame memory 65. Furthermore, the output of the SPS converter 64 is sent to the signal synthesis circuit 6.
8 and frame memory 65.

The frame memory 65 stores recorded/reproduced video signals recorded or reproduced on the magnetic tape 55 and supplied from the SPS converter 64 line by line. The above-mentioned SPS converter 64 performs serial-parallel conversion when the recording/playback video signal is written to the frame memory 65, and performs recording/reproducing video signals.
When reading out the reproduced video signal from the frame memory 65 and outputting it, parallel-to-serial conversion is performed in reverse. The address control circuit 66 includes an address counter, a synchronization addition ROM, etc., and supplies the frame memory 65 with a signal specifying a write or read address for each line of the recorded/reproduced video signal. The synchronization signal added to each line of the recording/playback video signal read from the frame memory 65 is SPS.
Output to converter 64. The shift register 67 described above converts the serial external input video signal input for synthesis via the input switching section 71 into a parallel external input video signal. The signal synthesis circuit 68 combines the parallel external input video signal supplied from the shift register 67 and the SPS converter 64.
The parallel reproduction video signal supplied from the frame memory 65 is switched and outputted to the frame memory 65. Signal synthesis control circuit 69
is based on the external input video signal by an external operation (e.g., front panel, system controller, etc.), as will be described in detail later, in order to compare with the external input video signal supplied from the shift register 67. Image data for sampling is specified. The control circuit 69 converts the sampling data into 8-bit data of the same format as one pixel, and outputs it to the signal synthesis circuit 68.

Further, each SPS converter 64 in the memory boards 47 and 48 is connected to an output switching section 72. Output switching section 7
2 performs a switching operation in units of frames based on an output data switching signal. That is, when a recorded video signal, a reproduced video signal, or an external input video signal signal for synthesis is written in the SPS converter 64 of either the memory board 47 or 48, the signal shown in FIG. The above signal is output to the changeover switch 50.

As shown in FIG. 3, the signal synthesis circuit 68 as a specific example includes a multiplexer 73 that extracts only necessary signals from a plurality of input signals, and a digital comparator 74 as a comparator. The digital comparator 74 is connected to the shift register 67 to input an external input video signal, and is also connected to the signal synthesis control circuit 69 to input sampling data to be described later. Then, when the external input video signal and the sampling data are equal, the digital comparator 74 outputs the signal from the multiplexer 7.
The multiplexer 73 is connected to the shift register 67 and inputs the external input video signal, and is also connected to the SPS converter 64 to output the reproduced video signal. The multiplexer 73 inputs the signal to the digital comparator 74.
When 'O' is input, the reproduced video signal from the SPS converter 64 is taken out, and when 'O' is input manually, the external input video signal from the shift register 67 is taken out and output to the frame memory 65. There is.

In the above configuration, first, the operation of the high-definition VTR during recording will be explained. During recording, the analog recording video signal input from the first input terminal 41 is
The signal is supplied to the recording signal/external input signal A/D converter 44 via the changeover switch 43 which has been switched to the EC side, and is converted into a digital signal. This digital recorded video signal is sent to the input switching unit 70 via the changeover switch 46 which is switched to the REC side in the figure. Note that at this time, the changeover switch 45 is in the off state. Based on the input data switching signal, the input switching section 70 supplies the digital recording video signal to each SPS converter 64 in the memory boards 47 and 48 alternately for each frame. Each SPS converter 64 converts the serial recording video signal into a parallel recording video signal, and stores it line by line at a predetermined address in the frame memory 65 designated based on the signal from the address control circuit 66.

When one frame of recorded video signal is stored in the frame memory 65, the recorded video signal stored from a predetermined address in the frame memory 65 designated based on a signal from the address control circuit 66 is sequentially sent to the SPS line by line. It is read out to converter 64. Every time reading of one line of recorded video signals is completed, a synchronization signal is supplied from a synchronization addition ROM (not shown) in the address control circuit 66 to the SPS converter 64, thereby adding a synchronization signal to one line of recorded video signals. is added. This recorded video signal is then converted into a serial signal and outputted to the changeover switch 50 in FIG. 2 via the output switching section 72. below,
Similar processing is repeated until reading of one frame of the recorded video signal is completed. As described above, shuffling is performed by once writing the recorded video signal line by line into the frame memory 65, and reading out predetermined portions in order.

Note that the input switching section 70 and the output switching section 72 are linked, so when input data is being written to one of the SPS converters 64, output data is being read from the other SPS converter 64. , recording video signals are alternately output from the respective 5-PS converters 64 for each frame.

During recording, the changeover switch 50 is connected to the REC side in FIG. FM
The modulated signal is recorded on a magnetic tape 55 by a magnetic head 54 via a recording amplifier 53.

On the other hand, during reproduction, the magnetic head 54 drives the magnetic tape 5.
The reproduced video signal reproduced from the FM demodulator 58 is amplified by a reproduction amplifier 56, equalized by an equalizer 57, and then FM demodulated by an FM demodulator 58. Continued, TBC60
After A/D conversion and time axis error correction are performed, the first
The signal is sent to the input switching section 70 shown in the figure. At this time, the changeover switch 45 is in the off state.

In the manual switching unit 70, the reproduced video signal is alternately sent to each SPS converter 64 of the memory boards 47 and 48 frame by frame, as in the case of recording described above, and is first transferred to a part of the frame memory 65 at a predetermined address. After being stored, the data is alternately output from each SPS converter 64 to the changeover switch 50 in FIG. 2 via the output switching section 72 every frame together with the synchronization signal from the address control circuit 66. This results in
Deshuffling is performed.

During playback, the selector switch 50 is connected to the PB side in FIG. and output to an external device such as a high-definition TV.

Next, an explanation will be given of the operation when combining the reproduced video signal reproduced from the magnetic tape 55 and the externally inputted video signal inputted from an external device such as a television camera.

At the time of synthesis, the reproduced video signal reproduced from the magnetic tape 55 by the magnetic head 54 is sent to the reproduction amplifier 5 in the same way as during reproduction.
The signals are alternately supplied frame by frame to the SPS converters 64 (FIG. 1) of the memory boards 47 and 48 via SPS converters 6 and the like, and are then supplied to the signal synthesis circuit 68.

On the other hand, an external input video signal is input from the input terminal 42,
At the time of synthesis, the signal is sent to the recording signal/external input signal A/D converter 44, which is not used during playback, via the changeover switch 43 connected to the synthesis side in FIG. converted into a signal. and,
At the time of composition, the external input video signal is sent to the input switching section 71 via the changeover switch 45 connected to the composition side in the figure and turned on, and the input data switching signal is sent to the input switching section 71 based on the above input data switching signal. Each shift register 6
7 and are sent alternately every frame. shift register 6
At 7, the external input video signal from the input switching section 71 is converted from serial to parallel, and the converted signal is supplied to the signal synthesis circuit 68.

Taking the luminance signal, that is, the Y signal, as an example, the frequency is 48.6 MHz.
Therefore, the number of pixels per line is 1440 out of 1125 scanning lines/frame.
Become an individual. Also, one pixel is converted to 8-bit data. When synthesizing video signals, the signal synthesis control circuit 6
9, as shown in FIG.
Output to. The digital comparator 74 similarly has 8
The external input video signal, which has been converted into bit data, and the extraction data are compared for each pixel in one line, and it is determined whether the external input video signal is extracted or not, and the multiplexer 73 is 1" or O".The multiplexer 73 outputs a digital comparator 74.
Selects the playback video signal when inputting “1” from “0”.
” is input, the external input video signal is selected. In this way, synthesis is performed pixel by pixel.

More specifically, as shown in FIG. 4, the external input video signal is an image 75 consisting of a composite image 75a (red) and a background 75b (blue), and the reproduced video signal is an image 76.
Suppose that Composite image 75a (red) and background 75b (
FOH1O
Assume that it can be written as F+((Here, the subscript H is 16
(represents a base number). To obtain the composite image 78, extract the background 75b (blue) from the image 75, and after extracting the background 75b (blue)
Just insert 6. Therefore, the signal synthesis control circuit 69 outputs the data OFM corresponding to the background 75b (blue) to the digital comparator 74 as sampling data.

On the other hand, in FIG.
and digital converter>' are supplied to the parator 74, and the image 76
is supplied to multiplexer 73. The digital comparator 74 receives the image data of the image 75 (ff17, FO
□ and OF
The image data of image 75 and sampling data OF are compared pixel by pixel.

When they are equal, that is, when the background 75b (blue) is detected, "1" is output to the multiplexer 3, and when the image data of the image 75 and the sampling data OFH are not equal, that is, the image for synthesis 75a (red), outputs 0° to the multiplexer 73. The multiplexer 73 selects whether the output of the digital comparator 74 is “
1, the image data of image 76 is taken out, and when the output of digital comparator 74 is "'0", image data of image 76 is extracted.
5, that is, data FO corresponding to the composite image 75a (red). In this way, the external input video signal or reproduced video signal taken out by the multiplexer 73 is sent to the frame memory 65 as a composite video signal in which each pixel is completely superimposed, and from the address control circuit 66. Each line is stored at a predetermined address in the frame memory 65 based on the signal.

Next, the composite video signal is sent from the frame memory 65 to the SPS converter 64, and a synchronization signal from the address control circuit 66 is added to this composite video signal line by line. Then, the composite video signal to which the synchronization signal has been added is outputted to the changeover switch 50 in FIG. 2 via the output switching section 72. Note that the output of the composite video signal from each SPS converter 64 of the memory boards 47 and 48 is performed alternately for each frame as in normal playback. Thereafter, the composite video signal is outputted from the output terminal 63 to the /S vision etc. via the D/A converter 61 etc., as in the case of normal playback, and a composite image 78 (shown in FIG. 4) is obtained.

Although the frame memory 65 is used in the above embodiment, a field memory may be used instead of the frame memory.

〔Effect of the invention〕

As described above, the video signal synthesis device for a high-definition VTR according to the present invention is used both during recording and when synthesizing video signals, and converts an analog video signal input to the high-definition VTR into a digital video signal. A/D
a signal synthesis control circuit that generates and outputs sampling data from synthesis image data that is input externally and is converted into a digital signal in order to synthesize the converter and a reproduced image that is played back on the high-definition VTR; The above sampling data is input from the synthesis control circuit, and reproduction image data is selected when the synthesis image data and sampling data are equal, and synthesis image data is selected when the synthesis image data and sampling data are not equal. The configuration includes a signal synthesis circuit that selects and outputs the selected signal to the storage means.

Therefore, since the recording A/D converter originally included in the device is used for A/D conversion of externally input video signals, the number of parts can be reduced and costs can be reduced. It is advantageous. Furthermore, since the reproduced video signal and the externally input video signal are both converted into digital signals and synthesized pixel by pixel, it is possible to obtain a completely superimposed composite signal. This has the effect of improving the image quality of the composite image.

[Brief explanation of the drawing]

1 to 4 show one embodiment of the present invention. FIG. 1 is a block diagram showing the configuration of main parts of a video signal processing section. FIG. 2 is a block diagram showing the configuration of the video signal processing section. FIG. 3 is a block diagram showing the configuration of the signal synthesis circuit. FIG. 4 is an explanatory diagram showing the image compositing procedure. 5 to 8 show conventional examples. FIG. 5 is a block diagram showing the configuration of the video signal processing section. FIG. 6 is a block diagram showing the configuration of the main parts of the video signal processing section. FIG. 7 is an explanatory diagram showing the image compositing procedure. FIG. 8 is a block diagram showing the configuration of the signal synthesis circuit. 44 is an A/D converter for recording signals and external human input signals; 6
5 is a frame memory (storage means), 68 is a signal synthesis circuit, and 69 is a signal synthesis control circuit. Patent Applicant: Sharp Co., Ltd.

Claims (1)

[Claims] In order to record and reproduce a video signal of one field by dividing it into a plurality of recording tracks, the analog video signal is converted into a digital video signal and written in a storage means, and the time arrangement of scanning lines is changed. In a video signal synthesis device for a high-definition VTR, which is equipped with a shuffling circuit that rearranges and reads out the scan lines from the storage means, and a deshuffling circuit that restores the time arrangement of the rearranged scanning lines and reads them out from the storage means, the video signal synthesis device for a high-definition VTR is equipped with the following: An A/D converter is also used to convert the analog video signal input to the high-definition VTR into a digital video signal, and an externally input digital A signal synthesis control circuit generates and outputs sampling data from the synthesis image data converted into a signal, and the above sampling data is input from the signal synthesis control circuit, and when the synthesis image data and the sampling data are equal. Select the reproduced image data, select the image data for synthesis when the image data for synthesis and the data for sampling are not equal,
A video signal synthesis device for a high-definition VTR, comprising a signal synthesis circuit for outputting to the storage means.