JPH01213007A - Mixer circuit - Google Patents

Abstract

PURPOSE:To improve the suppression of an unnecessary wave by inputting a UHF signal to a third FET source and inputting a VHF signal to a second FET gate. CONSTITUTION:A gate earth, a source input and the drain of a third FET 3 of a drain output type are connected to the gate of a first FET 1 out of the first FET 1 and a second FET 2 to constitute a buffer FET. A UHF signal is inputted to the source of the FET 3, and a VHF signal is inputted to the gate of the FET 2. Consequently, a UHF mixer circuit and a VHF mixer circuit are integrated in one body, a matching condition with a variable turning filter 18 inserted to the front stage of the FET 1 become well, and the suppression of the unnecessary wave of the filter 18 is improved.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a mixer circuit for signal frequency conversion used in satellite broadcast receivers, television tuners, etc.
This invention relates to a mixer circuit suitable for IC implementation.

[Conventional technology]

The mixer circuit in a conventional IC TV tuner is manufactured by IEE, Transaction on Consumer Electronics.

C.E. 32.4 (1986) pp. 723-732
Page (IEEE, Transactions on C
onsumer Electronics, Vol.
GE-32, k4 (1986) pp723-732
) as described in UHF mixer circuit.

VHF mixer circuit, Hyperband
nd) Mixer circuits are configured separately depending on the receiving frequency band, and each of the separate mixer circuits is selected by a switching circuit.

[Problem to be solved by the invention]

As mentioned above, in the existing proposed example, the UHF mixer circuit, VHF mixer circuit, and hyperband mixer circuit have separate configurations depending on the receiving frequency band, so the circuit size increases and However, there are problems in that the power consumption increases and the switching circuit for selecting separate mixer circuits depending on the receiving frequency band becomes complicated.

Furthermore, as described above, since the circuit scale becomes large, when the entire circuit is integrated into an IC, there is a problem that the amount of heat generated increases and the characteristics become unstable due to an increase in chip temperature.

Furthermore, an unnecessary wave suppression filter for suppressing unnecessary waves of the input UHF signal is generally inserted before the UHF mixer circuit, but in the previously proposed example described above, the UHF mixer circuit is This is the base input of the transistor, and as a result, the input impedance of the UHF mixer circuit is high.Therefore, there was a problem that the unnecessary wave suppression filter inserted could not achieve a sufficient degree of unnecessary wave suppression. .

As described above, there are several problems to be solved in the above-mentioned conventional techniques.

Therefore, it is an object of the present invention to solve the problems of the prior art, to integrate a UHF mixer circuit and a VHF mixer circuit (including a hyperband mixer circuit), to make it possible to integrate a UHF mixer circuit and a VHF mixer circuit (including a hyperband mixer circuit), and to improve the integration of UHF signal. An object of the present invention is to provide a balanced mixer circuit that can improve the degree of unnecessary wave suppression of an unnecessary wave suppression filter that suppresses unnecessary waves.

[Means to solve the problem]

In order to achieve the above object, the present invention includes, for example,
In a mixer circuit consisting of a double-balanced mixer, a buffer FET, and a constant current source, the first FET of the first FET and the second FET constituting the buffer FET is
Connect the drain of a third FET with a common gate, source input, and drain output type to the gate of T, input a UHF signal to the source of the third FET, and input a VHF signal (including hyperband signals). The signal was input to the gate of the second FET.

[Effect]

The double-balanced mixer has a UH'F signal and a VHF signal.
Since it is used for both signals (including hyperband signals), it is possible to substantially integrate the U) IF mixer circuit and the VHF mixer circuit (including the hyperband mixer circuit). Therefore, according to the present invention, the circuit scale can be reduced and the power consumption can be reduced, and a switching circuit (for example, connected to the drain of the third FET) for selecting mixer operation depending on the receiving frequency band. ) can be simplified.

In addition, since the circuit scale can be made smaller, when integrated into an IC, the amount of heat generated does not increase (as in the conventional case), and the characteristics do not become unstable due to an increase in chip temperature.
Suitable for IC implementation.

Furthermore, according to the present invention, since the input portion of the UHF signal is the source input of the third FET, the matching state with the unnecessary wave suppression filter inserted before the third FET is good. Therefore, the unnecessary wave suppression degree of this unnecessary wave suppression filter is greatly improved.

Further, the first FET and the second FET are buffer FEs.
As mentioned above, even if the UHF mixer circuit and VHF mixer circuit are integrated, the coupling between the UHF circuit and VHF circuit connected before the mixer circuit must be kept small (i.e. , it is possible to eliminate signal leakage between both circuits).

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

In FIG. 1, 1.2 are buffer FETs, 3
, 4, 5, 6, 7.9 are FETs, 8 is a switching FET, 10 is a UHF signal input terminal, 11 is a VH
F signal input terminal, 12 is a switching voltage input terminal, 13.14 is a local oscillation signal input terminal, 15.16 is an intermediate frequency signal output terminal, 17 is a bias voltage input terminal, 18° and 19 are variable respectively. Tuned filter, 20,2
1°22.24, 25, 26.27.30 are resistors, 23 is a capacitor, and 28 is an input terminal for current control voltage.

In this embodiment, as shown in FIG.
to configure a double-balanced mixer, connect the sources of FETs 4 and 5, and connect the buffer FET to the connected source.
Connect the drains of ETI, and also connect the sources of FETs 6 and 7, and connect the connected sources to the buffer FET.
The drain of FETI 2 is connected to the source of FETI 2, and a constant current source consisting of FET 9 is connected to the source of FETI 2. Also,
The gate of the buffer FETI is connected to the gate via a resistor 25, which is a so-called grounded gate type FET3.
A bias voltage is applied to the drain from the input terminal 17 via the resistor 21. Further, the gate of buffer FETI and the gate of buffer FET2 are connected by a resistor 20 having a high resistance value.
The same DC bias is applied to each.

Furthermore, a local oscillator (not shown) is connected between the input terminals 13 and 14, and a local oscillation signal is input thereto.

Now, the operation of this embodiment will be explained.

First, the operation when receiving a VHF signal (including hyperband signals) will be explained.

When receiving a VHF signal, the VHF signal is input to input terminal 11.
It is input to the gate of the buffer FET 2 via the variable tuning filter 19, and a High(
A high level switching voltage is applied, the switching FET 8 is turned on via the resistor 22, and the gate of the buffer FETI is grounded through the large capacitor 23.

When the VHF signal is input from the input terminal 11 to the gate of the buffer FET 2 via the variable tuning filter 19, the variable tuning filter 19, which is an unnecessary wave suppression filter,
Suppresses unnecessary signal waves (image signals, etc.).

Now, assuming that the gate voltage of the buffer FET2 is rising due to the input VHF signal, the current flowing through the buffer FET2 and FETs 6 and 7 increases due to this rise in gate voltage. However, the FET 9 constitutes a constant current source as described above, and the drain current flowing through the FET 9 is always a constant value. Therefore, buffer FET2
And the increase in the current flowing through FETs 6 and 7 is increased by the buffer F
This appears as a decrease in the current flowing through ET1 and FETs 4 and 5. In other words, VH is applied to the gate of buffer FET2.
When the F signal is input, buffer FET2 and FET6
, 7 flows in accordance with the VHF signal, while current in the opposite phase flows into the buffer FETI and FET 4.5. In this way, the VHF signal input as an unbalanced signal to the gate of the buffer FET2 is input as a balanced signal to the double-balanced mixer. By grounding the gate of FET2 with a large capacitor 23, the buffer FE is connected to the VHF signal.
Since the gate of TI has low impedance, better unbalanced-balanced conversion can be performed.

Next, the double-balanced mixer mixes the previously inputted local oscillation signal and the VHF signal inputted as a balanced signal, and outputs an intermediate frequency signal, which is a difference signal between the local oscillation signal and the VHF signal, to the output terminal 15. .

Output from 16.

The above is the operation when receiving a VHF signal.

Next, the operation when receiving a UHF signal will be explained.

When receiving a UHF signal, the UHF signal is input to input terminal 10.
The signal is input to the source of the FET 3 via the variable tuning filter 18, and a Loil (low) level switching voltage is applied to the input terminal 12 to turn off the switching FET 8 via the resistor 22.

When the UHF signal is input from the input terminal 10 to the source of the FET 3 via the variable tuning filter 18, the variable tuning filter 18, which is an unnecessary wave suppression filter, suppresses the unnecessary waves of the UHF signal.

Then, the UHF signal input to the source of FET3 is
It is output from the drain of FET3 and input to the gate of buffer FETI.

The subsequent operation is symmetrical to, but almost the same as, the operation when the VHF signal is received, so a description thereof will be omitted.

However, when receiving the UHF signal, the switching FET 8 is turned off as described above. This is because the variable tuning filter 19 always has a low impedance to the UHF signal, so the gate of the buffer FET 2 always has a low impedance to the VHF signal. This is because good unbalanced-balanced conversion can be performed even without grounding the gate of the buffer FET 2 with a large-capacity capacitor.

As described above, according to this embodiment, since the UHF mixer circuit and the VHF mixer circuit (including the hyperband mixer circuit) can be integrated, the circuit scale can be reduced.
Power consumption is also reduced, and a switching circuit (
Switching FET8. Resistance 22. The circuit consisting of the capacitor 23) can be simplified.

In addition, since the circuit scale can be reduced, when integrated into an IC, the amount of heat generated will increase and the characteristics will not become unstable due to an increase in chip temperature (therefore,
This can be said to be a configuration suitable for IC implementation.

Furthermore, according to this embodiment, the input portion of the UHF signal is the source input of the FET 3, and since the input impedance seen from the source of the FET 3 is low, the The matching state with the unnecessary wave suppression filter, that is, the variable tuning filter 18, becomes good, and therefore the degree of unnecessary wave suppression of this variable tuning filter 18 is greatly improved.

Also, when receiving a VHF signal, the buffer FE
The VHF signal input to T2 is blocked by the buffer FETI, so it leaks out from the input terminal 10,
The UHF circuit (not shown) connected to the input terminal 10 will not be adversely affected. Similarly, UH
When receiving the F signal, the UHF signal input to the buffer FETI is blocked by the buffer FET2, so it leaks out from the input terminal 11 and is connected to the VHF circuit (not shown) connected to the input terminal 11. ). That is, according to this embodiment, even if the UHF mixer circuit and the VHF mixer circuit (including the hyperband mixer circuit) are integrated as described above, the coupling between the UHF circuit and the VHF circuit can be reduced ( That is,
It is possible to eliminate signal leakage between both circuits).

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

This embodiment differs from the embodiment shown in FIG. 1 in that, as shown in FIG. 2, the source of the switching FET 8 is connected to the drain through a resistor 29 having a large resistance value.

In the embodiment shown in FIG. 1, the source of the switching FET 8 was floated in a direct current manner, but in this embodiment, by setting the source of the switching FET 8 to the same potential as the drain in a direct current manner, the switching FET 8 Switching characteristics can be improved. It should be noted that this embodiment has the same structure as the embodiment shown in FIG. 1 in other parts, so it is clear that the same characteristics and effects as the embodiment shown in FIG. 1 can be obtained.

FIG. 3 is a circuit diagram showing a third embodiment of the invention, and FIG. 4 is a circuit diagram showing a fourth embodiment of the invention.

In these embodiments, a diode (switching diode 31 in FIGS. 3 and 4) is used as a switching means instead of an FET (switching FET 8 in FIGS. 1 and 2).
), the switching circuit can be further simplified.

In the embodiment shown in FIG. 3, the cathode of a switching diode 31 is connected to the gate of the buffer FETI, and the anode is grounded by a capacitor 32 of large capacity. Then, a switching voltage is applied to the anode from the input terminal 12 via the resistor 22.

When receiving a UHF signal, a low-level switching voltage is applied to the input terminal 12 and the switching diode 31 is set to 0FFL, and when receiving a VHF signal, a high-level switching voltage is applied to the input terminal 12.
Turn on the switching diode 31.

On the other hand, in the embodiment shown in FIG. 4, the anode of a switching diode 31 is connected to the gate of the buffer FETI, and the cathode is grounded by a capacitor 32 of large capacity. and,
A switching voltage is applied to the cathode from the input terminal 12 via the resistor 22. When receiving a UHF signal, apply a high level switching voltage to the input terminal 12, and set the switching diode 31 to 0FFL, VH.
When receiving the F signal, a Loiv level switching voltage is applied to the input terminal 12 and the switching diode 31 is turned on.

The other operations of these embodiments are the same as those of the embodiment shown in FIG. 1, and it is therefore clear that similar characteristics and effects to those of the embodiment shown in FIG. 1 can be obtained in these embodiments as well.

FIG. 5 is a circuit diagram showing a fifth embodiment of the present invention.

In this embodiment, as shown in FIG. 5, FET4°5.6.
7 constitutes a double-balanced mixer, the sources of FETs 4 and 5 are connected together, and the buffer F is connected to the connected source.
Connect the drains of ETI and 36, and also connect the drains of FET6,
7 are connected together, and the drain of buffer FET2 is connected to the connected sources, and buffer FET1, 3 is connected.
A constant current source consisting of an FF and T9 is connected to the source of 6.2.

Further, the gate of the buffer FETI is connected to the drain of the FET3 whose gate is grounded, and a bias voltage from the input terminal 41 is applied to the drain by resistance division of the resistors 43 and 34.

Further, a resistor 44. is connected to the gate of the buffer FET3'6.
A bias voltage from an input terminal 42 is applied by resistor division of 35. Furthermore, the input terminal 37 is connected to the gate of the buffer FET2 by resistance division of the resistors 37 and 38.
, and its gate is grounded through a large capacitor 40 (in addition,
This grounding is to prevent unnecessary high frequency components from being induced in the gate of the buffer FET 2, and in some cases, it may not be necessary to ground for practical use. ).

Here, it is assumed that the gate widths of the buffers FETI and 2.36 are the same, and the bias voltages applied to the respective gates are also the same.

Now, the operation of this embodiment will be explained.

First, when receiving a UHF signal, the UHF signal is input from the input terminal 10 to the source of the FET 3 via the variable tuning filter 18, and the bias voltage input to the input terminal 41 is set to H4gh level, and the buffer FETI
is ONL, and the bias voltage input to the input terminal 42 is L.
OW level and turns off the buffer FET36.

On the other hand, when receiving a VHF signal, the VHF signal is sent from the input terminal 11 to the buffer FE via the variable tuning filter 19.
The bias voltage input to the gate of T36 and the input terminal 41 is set to Low level, the buffer F and ET1 are set to 0FFL, and the bias voltage input to the input terminal 42 is set to High level.
Turn on.

Through the operations described above, unbalanced-balanced signal conversion is performed in this embodiment as well, but the operating principle is the first
This is the same as described in the embodiment shown in the figure.

According to this embodiment, since the UHF mixer circuit and the VHF mixer circuit (including the hyperband mixer circuit) can be integrated, the circuit scale can be reduced, power consumption can be reduced, and the mixer operates depending on the receiving frequency band. The switching circuit for selecting can be simplified, and the DC bias of the mixer circuit does not change even if the switching operation is performed.

In addition, since the circuit scale can be reduced, when integrated into an IC, the amount of heat generated does not increase and the characteristics do not become unstable due to a rise in chip temperature, which is the case with conventional methods.
This can be said to be a configuration suitable for IC implementation.

Furthermore, according to this embodiment, since the input portion of the UHF signal is the source input of FET3, this FET
The matching state with the variable tuning filter 18 inserted before the filter 3 becomes good, and therefore the degree of unnecessary wave suppression of this variable tuning filter 18 is greatly improved.

FIG. 6 is a circuit diagram showing a sixth embodiment of the present invention.

As shown in FIG. 6, this embodiment is a modification of the embodiment shown in FIG.
5, 6.7 and buffer FETI.

2.36.45 and FET 3 with a gate ground plane. In addition, in Figure 6, 46°47.4
B, 49, 60, 61, 62.63 are resistances, respectively.

In this embodiment, first, when receiving UH and F signals,
The HF signal is input from the input terminal 10 to the source of the FET 3 via the variable tuning filter 18, and at the same time, the HF signal is input from the input terminal 4 to the source of the FET 3.
Set the bias voltage input to 1 to High level,
Buffer FET 1.45 is set to ONL, the bias voltage input to input terminal 42 is set to Low level, buffer FETs 2 and 36 are turned off, and the switching voltage input to input terminal 12 is set to Low level, switching FET 8 is set to ONL. Turn off.

On the other hand, when receiving a VHF signal, the VHF signal is sent from the input terminal 11 to the buffer FE via the variable tuning filter 19.
The bias voltage input to the gate of T2 and the input terminal 41 is set to Low level, and the buffer F
ETI, 45 is set to 0FFL, the bias voltage input to the input terminal 42 is set to High level, and the buffer FET2 is set to 0FFL.
, 36 are ONL, and the switching voltage input to the input terminal 12 is set to High level, so that the switching F
ET8 is turned ON, and the gate of the buffer FET 36 is grounded with a large capacity capacitor 23.

By the above-described operation, unbalanced-balanced signal conversion is performed also in this embodiment.

Further, resistors 60, 61, 62, and 63 are resistors for preventing distortion from occurring in the mixer circuit.

That is, resistors 60 and 61 have the same resistance value, and resistors 62 and 6
3 is set to the same resistance value. When the distortion generated for the UHF signal is larger than that for the VHF signal, the resistance value of the resistor 60.61 is selected to be larger than the resistance value of the resistor 62.63. , the resistance value of resistor 60.61 is selected to be smaller than the resistance value of resistor 62.63. In this way, good distortion characteristics can be obtained depending on the frequency band to be received, and the DC bias of the mixer circuit will not change even if a switching operation is performed to change the frequency band to be received. A mixer circuit is obtained.

It is clear that the characteristics and effects of this embodiment are similar to those of the embodiment of FIG. 5.

FIG. 7 is a circuit diagram showing a seventh embodiment of the present invention.

In this embodiment, as shown in FIG. 7, the gate of the buffer FET 1 is directly connected to the drain of FET 3, which is a grounded gate plane, and the drains of FET and T 50, which are grounded source planes. Furthermore, the gates of the buffers F and ET2 are grounded at high frequency with a large capacity capacitor 40. Additionally, in FIG. 7, 51, 52, and 53 are resistors, respectively.

In this embodiment, when receiving a UHF signal,
A signal is input from the input terminal 10 to the source of the FET 3 via the variable tuning filter 18, and the voltage input to the input terminal 41 is set to open or FE.
The voltage is set to turn on T3, and the bias voltage input to the input terminal 42 is set to low level, and the FET 50 is turned off.

When receiving a VHF signal, the VHF signal is input from the input terminal 11 to the gate of the FET 50 via the variable tuning filter 19, and the voltage input to the input terminals 41 and 42 causes the FET 3 to be set to 0FFL and the FET 50 Turn on.

Here, even if the drain currents of FET3 and FET50 are set to be the same and the switching operation is performed, the buffer FE
Make sure that the gate voltage of T1 does not change.

As described above, according to this embodiment, the UHF mixer circuit and the V
HF mixer circuit (including hyperband mixer circuit)
Since it can be integrated with the mixer, the circuit size can be reduced, power consumption can be reduced, and the switching circuit for selecting mixer operation depending on the frequency band to be received can be simplified. The DC bias of the mixer circuit does not change. Furthermore, since the circuit scale can be reduced, it can be said that the configuration is suitable for IC implementation.

Further, according to this embodiment, the input portion of the UHF signal is
Since it is the source input of T3, the matching state with the variable tuning filter 18 inserted in the previous stage of this FET 3 is good, and therefore, the unnecessary wave suppression degree of this variable tuning filter 18 is greatly improved.

FIG. 8 is a circuit diagram showing an eighth embodiment of the present invention.

In this embodiment, as shown in FIG. 8, FET 4°5.6.
7 constitutes a double-balanced mixer, and this double-balanced mixer is equipped with a buffer FETI.

It has a configuration in which 2 are connected. Additionally, in FIG. 8, 54, 55, 56, and 57 are resistors, respectively.

In this embodiment, i receiving the UHF signal is inputted from the input terminal 10 to the source of the buffer FETI via the variable tuning filter 18, and at the input terminal 4.
The voltage input to 1.42 turns the buffer FET1 ON and the buffer FET2 OFF. This results in
Among the FETs that make up the double-balanced mixer, FE
A single balanced mixer operation using T'4°5 is performed.

In addition, when receiving a VHF signal, the VHF signal input from the input terminal 11 of the VHF signal generator 1 to the gate of the buffer FET 2 via the variable tuning filter 19 is also input to the input terminal 4.
1.42, the buffer FETI is set to 0FFL and the buffer FET2 is turned on. This results in
Of the F'ETs that make up the double-balanced mixer, F
A single balanced mixer operation using ET6.7 is performed.

According to this embodiment, since the UHF mixer circuit and the VHF mixer circuit (including the hyperband mixer circuit) can be integrated, the circuit scale can be reduced, power consumption can be reduced, and the mixer operates depending on the receiving frequency band. The switching circuit for selecting can be simplified.

Further, according to this embodiment, since the input portion of the UHF signal is the source input of the buffer FETI, the variable tuning filter 18 inserted before the buffer FETI
Therefore, the degree of unnecessary wave suppression of this variable tuning filter 18 is greatly improved.

FIG. 9 is a circuit diagram showing a ninth embodiment of the present invention.

In this embodiment, a single-balanced mixer is configured with FETs 4 and 5, and a buffer FET is added to the single-balanced mixer.
It has a configuration in which ET1 is connected. In addition, 58 is a resistor, and 59.70 are switches.

In this embodiment, when receiving a UHF signal, the UHF signal is input from the input terminal 10 through the variable tuning filter 18 to the source of the buffer FETI, and the switch 5
Turn off (open) switch 9 and turn on switch 70 (short circuit)
do.

When receiving a VHF signal, the VHF signal is sent from the input terminal 11 to the buffer FE via the variable tuning filter 19.
It is input to the gate of TI, and the switch 59 is turned on.
(short circuit) and turn off the switch 70 (open).

According to this embodiment, since the tJHF mixer circuit and the VHF mixer circuit (including the hyperband mixer circuit) can be integrated, the circuit scale can be reduced, power consumption can be reduced, and the mixer circuit is suitable for IC implementation. is obtained.

In addition, since the input part of the UHF signal is the source input of the buffer FET 1, the matching state with the variable tuning filter 18 inserted before this FETI is good.
Therefore, the degree of unnecessary wave suppression of this variable tuning filter 18 is greatly improved.

[Effects of the Invention] As described above, according to the present invention, the UHF mixer circuit and the VHF mixer circuit (including the hyperband mixer circuit) can be integrated, so the circuit scale can be reduced and the consumption can be reduced. Power is also reduced, and the switching circuit for selecting mixer operation depending on the receiving frequency band can be simplified.

In addition, since the circuit scale can be reduced, when integrated into an IC, the amount of heat generated does not increase and the characteristics do not become unstable due to a rise in chip temperature, which is the case with conventional methods.
Suitable for IC implementation.

Furthermore, the input part of the UHF signal is the source input of the FET, and the input impedance seen from the source of this FET is low, so it is in a matching state with the unnecessary wave suppression filter inserted before the FET. becomes good, and therefore, the degree of unnecessary wave suppression of this unnecessary wave suppression filter is greatly improved.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing a first embodiment of the invention, Fig. 2 is a circuit diagram showing a second embodiment of the invention, and Fig. 3 is a circuit diagram showing a third embodiment of the invention. , FIG. 4 is a circuit diagram showing a fourth embodiment of the invention, FIG. 5 is a circuit diagram showing a fifth embodiment of the invention, and FIG. 6 is a circuit diagram showing a sixth embodiment of the invention. 7 is a circuit diagram showing a seventh embodiment of the invention, FIG. 8 is a circuit diagram showing an eighth embodiment of the invention, and FIG. 9 is a circuit diagram showing a ninth embodiment of the invention. This is a circuit diagram. Explanation of symbols 1.2... Buffer FET, 3 to 7, 9... FET
. 8... Switching FET, 18.19... Variable tuning filter, 31... Switching diode. Agent Patent Attorney Akio NamikiFigure 7Figure 9

Claims (1)

[Claims] 1. A mixer circuit for a receiver that receives a wideband signal consisting of a first band having a high frequency band and a second band having a low frequency band, the mixer circuit comprising a double-balanced mixer and a second band having a low frequency band. In the mixer circuit consisting of a buffer FET and a constant current source, a gate is connected to the gate of the first FET (1) of the first FET (1) and the second FET (2) constituting the buffer FET. The drain of a third FET (3) of ground, source input, drain output type is connected, the first band is input to the source of the third FET (3), and the second band is input to the source of the third FET (3). A mixer circuit characterized in that the input is input to the gate of FET (2). 2. In the mixer circuit according to claim 1, the double-balanced mixer includes fourth to seventh FETs (4 to 7).
The fourth FET (4) and the fifth FET
The sources of (5) are connected together to form a first terminal, the sources of the sixth FET (6) and seventh FET (7) are connected to form a second terminal, and the first terminal is The drain of the first FET (1) is connected to the second terminal, the drain of the second FET (2) is connected to the second terminal, and the first FET (1) and the second FET (2 ) are connected to form a third terminal, the constant current source is connected to the third terminal, a switching means is connected to the drain of the third FET (3), and the third terminal is connected to the third terminal. A bias voltage is supplied from the power supply to the drain of the FET (3) through the first resistor (21), and the gate of the first FET (1) and the second FET are connected to each other.
The gate of (2) is connected with a second resistor (20) having a relatively high resistance value to give the same DC bias, and the first band is connected to the source of the third FET (3). later inputted via a first variable tuned filter (18);
A mixer circuit characterized in that the second band is later input to the gate of the second FET (2) via a second variable tuning filter (19). 3. The mixer circuit according to claim 2, wherein the switching means has a drain connected to the third FET (3).
The source of the eighth FET (8) is grounded by a capacitor (23) having a relatively large capacity, and the source of the eighth FET (8) is connected to the drain of the eighth FET (8).
A mixer circuit characterized in that a switching voltage is applied to the gate of the ET (8) via a third resistor (22) having a relatively high resistance value. 4. The mixer circuit according to claim 3, wherein the eighth FET (8) is grounded by the capacitor (23).
The source of is connected to a fourth resistor (
29) is connected to the drain of the eighth FET (8). 5. The mixer circuit according to claim 2, wherein the switching means has a cathode connected to the third FET (3).
The anode of the diode (31) is grounded with a capacitor (32) having a relatively large capacity, and a switching voltage is applied to the anode. mixer circuit. 6. The mixer circuit according to claim 2, wherein the switching means connects its anode to the third FET (3).
It consists of a diode (31) connected to the drain of the diode (31), the cathode of the diode (31) is grounded by a capacitor (32) having a relatively large capacity, and a switching voltage is applied to the cathode. mixer circuit. 7. In the mixer circuit according to claim 1, the double-balanced mixer includes fourth to seventh FETs (4 to 7).
The fourth FET (4) and the fifth FET
The sources of (5) are connected together to form a first terminal, the sources of the sixth FET (6) and seventh FET (7) are connected to form a second terminal, and the first terminal is The drain of the first FET (1) and the drain of the second FET (36) are connected to the second terminal, and the eighth FET (36) is connected to the second terminal.
2), and connect the sources of the first FET (1), the second FET (36), and the eighth buffer FET (2) to form a third terminal. The constant current source is connected to the terminal, the gate of the eighth FET (2) is grounded at high frequency, and the first, second and eighth FETs
(1, 36, 2) are made equal in width, and the gate of the first FET (1) is connected to the first FET by resistor division.
The first band is changed by supplying a voltage of When receiving, turn on the first FET (1) and turn on the second FET (1).
FET (36) is turned off and when receiving the second band, the first FET (1) is turned off and the second FET (36) is turned off.
A mixer circuit characterized in that T(36) is turned on. 8. In the mixer circuit according to claim 1, the double-balanced mixer includes fourth to seventh FETs (4 to 7).
The fourth FET (4) and the fifth FET
The sources of (5) are connected together to form a first terminal, the sources of the sixth FET (6) and seventh FET (7) are connected to form a second terminal, and the first terminal is The drain of the first FET (1) is connected to the second terminal, and the drain of the eighth FET (2) is connected to the second terminal.
The sources of T(1) and the eighth FET (2) are connected to form a third terminal, the constant current source is connected to the third terminal, and the gate of the eighth FET (2) is connected to the third terminal. The second FET (1) is connected to the gate of the first FET (1) and grounded in terms of high frequency.
(50), and connect the drain of the second FET (50).
The source of the FET is grounded through the first resistor (51), and the drain of the third FET (3) is connected to the second resistor (5
3) supplies a bias voltage to the first FET (1).
A bias voltage is supplied from the gate of the eighth FET (2) to the gate of the eighth FET (2) through a third resistor (20) having a relatively high resistance value, and the first band is connected to the third FET (2).
A first variable tuning filter (18
), and the second band is input later through the second band
is later input to the gate of the FET (50) via the second variable tuning filter (19), and the gate of the third FET (3
) and the drain current of the second FET (50) are made equal, the first voltage is supplied to the source of the third FET (3), and the drain current of the second FET (50) is made equal to the drain current of the second FET (50). By supplying a second voltage to the gate and changing the first and second voltages, when receiving the first band, the third FET (3) is turned on and the second FET (3) is turned on. FE of
When T (50) is turned off and the second band is received, the third FET (3) is turned off and the second FET (50) is turned off and the second FET (50) is turned off.
0) is turned on. 9. In a mixer circuit for a receiver that receives a wideband signal consisting of a first band with a high frequency band and a second band with a low frequency band, the first to fourth FETs (4 to 7) A double-balanced mixer is configured, and the first FET (4) and the second FET (4)
The sources of the ET (5) are connected together to form a first terminal, the sources of the third FET (6) and the fourth FET (7) are connected to form a second terminal, and the sources of the third FET (6) and the fourth FET (7) are connected to form a second terminal. The drain of a fifth FET (1) as a buffer FET is connected to the terminal, and the sixth FET (1) as a buffer FET is connected to the second terminal.
The drain of ET (2) is connected, and the fifth FET (1
) is grounded via the first resistor (55), and the source of the sixth FET (2) is grounded via the second resistor (56), when receiving the first band. is the first
is input to the source of the fifth FET (1) via the first variable tuning filter (18), and the fifth FET
Turn on T(1) and turn off the sixth FET(2),
When receiving the second band, the second band is transmitted to the sixth FE through a second variable tuning filter (19).
A mixer circuit characterized in that an input signal is input to a gate of T(2) to turn off the fifth FET (1) and turn on the sixth FET (2). 10. In a mixer circuit for a receiver that receives a wideband signal consisting of a first band with a high frequency band and a second band with a low frequency band, the first FET (4) and the second FET ( 5) constitutes a single balanced mixer, and the first FET (4
) and the sources of the second FET (5) are connected to form the first terminal, the drain of the third FET (1) is connected to the first terminal, and the source of the third FET (1) is connected to the first terminal. Resist the source (5
8), the first band is input to the source of the third FET (1) via the first variable tuned filter (18), and the second band is input to the source of the third FET (1) via the first variable tuned filter (18). A mixer circuit characterized in that the input is input to the gate of the third FET (1) via a tuned filter (19).