JPH01212021A - Timing circuit and method of generating timing signal - Google Patents

Abstract

PURPOSE: To widen a timing range by providing a charging circuit which is charged with a pulse signal and generates a 1st electric signal and a reference voltage generator which generates a 2nd electric signal, and outputting a comparison electric signal in response to the 1st and 2nd electric signals. CONSTITUTION: A pulse signal generator generates and inputs a voltage signal with a constant duty ratio to the charging circuit 2; and the charging circuit 2 and reference voltage generator 3 generate voltage signals V1 and V2 respectively and a comparing device 4 compares those two voltage signals with each other and outputs one comparison signal. When the voltage V1 is larger than the V2 , the comparison signal V0 belongs to a 1st level and when the voltage V1 is smaller than the V2 , the comparison signal V0 belongs to a 2nd level. A restoring device 5 is used to discharge the charging circuit 2 after timing time and put it back to the starting state, i.e., the state before charging. Consequently, the timing time can be increased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to timing circuits and timing signal generation methods. More particularly, the present invention relates to analog timing circuits and timing signal generation methods.

[Prior Art and Issues to be Solved by the Invention J & Il Conventional analog timing circuits or delay circuits typically use a resistor R and a capacitor C as a timing element, and a resistor R and a capacitor C form an RC network, The capacitor is connected between a constant voltage and charged, and then the comparator compares the voltage that increases as the capacitor charges with a predetermined reference voltage, and outputs a high level or low level as a result of the comparison, and then connects the capacitor to a switching device. (e.g. thyristors, relays, etc.) or for other purposes. Since the capacitor voltage shows an exponential curve-like rise, the range where the curve is close to linear is narrow.

When the reference voltage is set within this range, the time at which the output of the comparator is turned over, the timing time, is very short (less than the charging time constant of this RC network). If the reference voltage is set outside this range,
The poor linearity of this voltage results in a decrease in timing accuracy. Normally, the way to extend the timing range provided by a timing circuit is to increase the values of the resistors and capacitors in the RC network, but using very large resistors and capacitors can reduce the accuracy of the resistor or capacitor values and reduce the timing accuracy. resulting in a decrease in Also, the larger the capacitor, the greater the electrical leakage. Therefore, if the charging current is small, the capacitor's leakage current reaches the same level as the charging current, rendering the circuit ineffective.

SUMMARY OF THE INVENTION An object of the present invention is to provide a new analog timing circuit or delay circuit to solve the above problems. It is also an object to provide an improved timing signal generation method.

Therefore, the main object of the present invention is to provide an analog timing circuit with a wide timing range.

Another object of the present invention is to provide an analog timing circuit with low requirements for timing elements.

These and other objects of the invention will become apparent from the brief description of the drawings.

[Means for Solving the Problems] A timing circuit of the present invention includes a pulse generator that generates a pulse signal, and a charging circuit that is connected to the pulse generator and is charged by the pulse signal and generates a first electric signal. , a reference voltage generator that generates a second electrical signal, and a comparison device, and is characterized in that it outputs a comparison electrical signal in response to the first electrical signal and the second electrical signal.

Further, the timing signal generation method of the present invention includes a method of generating a first electric signal by applying a pulse signal to an integrating circuit, and generating a timing signal by comparing the first electric signal and the second signal. It is characterized by

[Function] The timing circuit of the present invention is based on the principle of superposition in linear circuits (that is, the total response of a linear circuit is the sum of the respective input l responses), and is capable of forming an RC network with a conventionally used constant voltage. The constant charging is changed to charging the integrating circuit with a varying voltage, that is, charging the integrating circuit with a pulsed voltage having a constant duty ratio. In the timing circuit of the present invention, one pulse voltage generator outputs a voltage signal having a constant deniity ratio, charges this charging circuit in addition to one charging circuit, and outputs a first voltage signal that increases as charging progresses. the reference voltage generator outputs a second voltage signal, and the comparator outputs this second voltage signal.
Compares two voltage signals and outputs one comparison signal. On the other hand, another restoring device is provided to discharge the charging circuit and return to the initial state after the timing time is reached.

〔Example] The present invention will be explained below based on the drawings.

FIG. 1 is a block diagram of a timing circuit of the present invention, FIG. 2 is a timing circuit diagram of one embodiment of the present invention, FIG. 3 is a timing circuit diagram of another embodiment of the present invention, and FIGS. 4A and 4B.
Figures 4 and 4C show the potential VA, voltage v1, and voltage V at point A of the circuits shown in Figures 2 and 3, respectively. This is a graph showing.

Middle of the drawings - Reference numerals indicate the same or similar equipment or elements.

In FIG. 1, a pulse signal generator (1) generates a voltage signal with a constant duty ratio and inputs it to a charging circuit (2), and a charging circuit (2) and a reference voltage generator (3) each generate a voltage signal v1. and v2, and the comparator (4) compares these two voltage signals and outputs one comparison signal.If the voltage (1) is larger than v2 (that is, if the timing time has come), A) The comparison signal vo belongs to the first level, and if the voltage v1 is smaller than v2, then (
In other words, if the timing has not yet arrived)
, the comparison signal vo belongs to the second level. Comparison signal V. is used to control switches provided in other devices, such as thyristors, relays, etc. (not shown). After the repositioning device (5) reaches the timing time, the charging circuit (
2) is used to discharge the battery and return it to its initial state, that is, the state before charging.

FIG. 2 shows an embodiment of the timing circuit of the invention, which timing circuit has a pulse signal generator (1). The pulse signal generator (1) has two operational amplifiers LM+ and LM2, and the in-phase input terminal of the operational amplifier LM+ is grounded via a resistor R1 and connected to its own output terminal via a resistor R3. do. Operational amplifier LM+ and L
The anti-phase input terminals of M, are connected to each other, and the capacitor C1
is grounded via the variable resistor R2 and is connected to the variable resistor R via the resistor R2.
Both ends of the variable resistor R are connected to the cathode of the diode DI and the anode of the diode D2, respectively, and the other electrodes of the diodes D1 and D2 are connected to each other, and the output of the operational amplifier LM+ is connected to the moving end of the variable resistor R. connected to the end.

Resistor R connected in series between positive power supply +Vcc and ground
4, R5 constitutes a reference voltage generator (3), and outputs one constant voltage v2 to the operational amplifier LM2.
and the in-phase input terminal of the operational amplifier LM. The output terminal of operational amplifier LM2 is connected to the common mode input terminal of operational amplifier L)4+ via diode D3. The pulse signal generator (1) outputs a series of pulse voltage signals with a constant duty ratio at the output of the operational amplifier LM+. By adjusting the values of capacitor CI and resistor R2, the duty ratio of the pulse signal can be changed.

The charging circuit (2) is charged by the pulse voltage signal and generates a voltage signal V1, which is applied to the common mode input terminal of the operational amplifier LM3. Charging circuit (4) includes capacitor C2 and resistor R
6 and a diode D4. Diode D4 and resistor R6 are connected in series between the output of operational amplifier LM+ and the common mode input of operational amplifier LMs. One end of the capacitor C2 is grounded, and the other end is connected to the common-mode input terminal of the operational amplifier LM3. Due to the action of the diode D4 during the pulse interval, the charged capacitor C2 continues to hold its own voltage without being discharged.

The comparator (4) has an operational amplifier LM3, the output of which is connected to the load resistor R2. Operational amplifier LM3
compares voltage signals v1 and v2 applied to its in-phase and anti-phase input terminals, respectively, and outputs a comparison signal V at its output terminal. Output.

Here, the restoring device (9 is a sinimit circuit, which is used to discharge the capacitor C2 and return it to the initial state before charging after it is charged and reaches a certain voltage.The restoring device (5) is an operational amplifier. It has LM4 and L
The anti-phase input terminal of M4 is connected to the common-mode input terminal of operational amplifier LM3, and the common-mode input terminal of operational amplifier LM4 is connected to resistors R8 and R connected in series between the positive power supply +Vcc and ground.
It is connected to the connection point with 9. The common mode input terminals of operational amplifiers LM3 and LM4 are connected to diodes Ds,
They are interconnected through a switch Ks, a diode D6, and a resistor R7. When the switch 5 is turned on, if the voltage V+ of the capacitor C2 is greater than the output voltage V3 (the upper limit turnover voltage of the Schmitt circuit) (v3≧V2), the voltage across the resistors R8 and R9 forming the voltage divider becomes In the meantime, the capacitor C2 is discharged via the diode D5% switch 5 and the operational amplifier LM4, and the voltage v3 decreases. If the voltage v1 of the capacitor C2 is less than the reduced voltage Vs (lower limit turn-over voltage of the Schmitt circuit), the output of the operational amplifier LM4 falls to a high level and the discharge of the capacitor C2 ends.

FIG. 3 shows a variation of the embodiment of FIG. 2, which is similar to the circuit of FIG. 2, only that the RC integrator circuit of FIG. An integrator circuit is used, and a switch is used in place of the Schmitt circuit in FIG. The Miller integration circuit has an operational amplifier LM2, and the negative phase input terminal of the operational amplifier LMs is connected to the positive power supply +
A resistor R+o connected between Vcc and ground,
A voltage v4 derived from Rn is applied. The in-phase input terminal of the operational amplifier LMs is connected to the output terminal of the operational amplifier LH+ via a resistor RT2 and a diode D4 connected in the opposite direction, and further connected to the output terminal thereof via a capacitor C3. Diode D4 is capacitor C
3 is prevented from discharging during the charging pulse interval. The output terminal of the operational amplifier LMs is connected to the common mode input terminal of the operational amplifier LM3. The charging circuit (2) integrates the pulse voltage output from the pulse signal generator (1) and outputs a voltage v1 with good linearity, and the comparator (4) outputs the voltage v1 from the power supply Vc.
A comparison signal V is compared with a reference voltage V2 generated by an over-standard voltage generator (3) consisting of a variable resistor RI3 between C and ground.

get.

The restoring device (5) shown in FIG. 3 has a switch 6, which is connected in parallel with a capacitor C3. Turn on switch 6 and capacitor C3
can be discharged, reducing the output of the integrating circuit to zero and returning it to the state before charging.

FIGS. 4A, 4B, and 40 show the waveforms of the potential V at point A and the voltages V s Vl and O v2 in the circuits shown in FIGS. 2 and 3. Fig. 4A shows the voltage waveform at the output end of the pulse signal generator (1) in Figs. waveform voltage may also be used),
Under charging with this voltage, the charging circuit (2) outputs a stepwise voltage signal V+. Note that v2 is the output voltage of the reference voltage generator (3). If V2 > Vl, the output voltage V of the comparator (4). maintains a zero level, and at V2 = Vl, the voltage vo transitions to a high level. After a certain period of time, the repositioning device (5) discharges the capacitor, so the output voltage v1 of the charging circuit (2) decreases to zero, and the output voltage vo of the comparator (4) also transitions to zero accordingly. . This causes the entire timing circuit to enter the next timing period.

Delay time (i.e. timing time) of the entire circuit T
is expressed by the following formula.

T−nΔ1+ +−Δt2+Δt3 where m and n are the number of voltage pulses and pulse intervals within the timing time, respectively, and ga1”n sΔt1
and Δt2 are the pulse interval and pulse width, respectively, and the duty ratio of the pulse voltage is Δt1 and ″Δt2.

As can be seen from the above formula, the duty ratio K of the charging voltage vA is
Alternatively, the timing time T can be increased by increasing the value of Mar (this can be achieved by increasing the value of the reference voltage v2 when the pulse frequency is constant). In the above equation, -Δt2+Δt3 is the actual charging time of the charging circuit (the charging voltage vA is not zero only within this time). If the present invention uses the same timing elements as the conventional analog timing circuit, the timing time ratio of the timing circuit of the present invention can be doubled to the timing time of the conventional circuit. In addition, the linearity of the first voltage signal v1 in the present invention is good (see the embodiment in FIG. 3), and the linear range is wide, so the timing time can be increased by increasing the value of the second voltage signal v2. , and does not degrade timing accuracy unlike conventional timing circuits. In the embodiment shown in FIG. 2, a long time timing can be obtained depending on the duty ratio K of the charging voltage, so the timing accuracy is improved by setting the reference voltage v2 to be linear or within the linear range of the voltage of the capacitor C2. can be increased. In addition, the timing circuit of the present invention can obtain a relatively long timing time (several milliseconds to 10 milliseconds) by using only ordinary resistors and capacitors, thus reducing the requirements for timing elements such as resistors and capacitors. .

[Effects of the Invention] As explained above, the timing circuit and timing signal generation method of the present invention can increase the timing time even when using conventional timing elements, improve timing accuracy, and further improve the timing circuit and timing signal generation method of the present invention. This has the effect of reducing demands.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a timing circuit of the present invention, FIG. 2 is a timing circuit diagram of one embodiment of the present invention, FIG. 3 is a timing circuit diagram of another embodiment of the present invention, and FIGS. 4A and 4B.
4C shows the potential vA, voltage V1, and voltage V at point A of the circuit shown in FIGS. 2 and 3. It is a graph showing ′. (Main symbols in the drawing) (1): Pulse signal generator (2); Charging circuit (3): Reference voltage generator (4): Comparison device (5): Repositioning device Patent applicant Zhang Jihai Kaijo 1 Mi? Figure 1 1: Pulse signal generator 2: Charging circuit 3: Reference voltage generator 4: Comparator 5: Repositioning device

Claims (1)

[Scope of Claims] 1. A pulse generator that generates a pulse signal, a charging circuit that is connected to the pulse generator and is charged by the pulse signal and generates a first electric signal, and a reference that generates a second electric signal. A timing circuit comprising a voltage generator and a comparator, and outputting a comparison electrical signal in response to a first electrical signal and a second electrical signal. 2. The timing circuit of claim 1, further comprising a restoring device connected to the charging circuit and capable of discharging the charging circuit automatically or by manual control after a timing time has been reached. 3. The timing circuit according to claim 1, wherein the pulsed electrical signal has periodicity and a duty ratio thereof is adjustable, and further, the level of the first electrical signal is adjustable. 4. Claim 2, characterized in that the repositioning device is equipped with a Schmitt circuit or a manual control switch.
Timing circuit as described. 5. The timing circuit according to claim 1, wherein the charging circuit includes an RC integrating circuit or a Miller integrating circuit. 6. A method of generating a first electric signal by applying a pulse signal to an integrating circuit, and a method of generating a second electric signal of a predetermined level, and comparing the first electric signal and the second electric signal. A timing signal generation method characterized in that a timing signal is generated using a timing signal. 7. The pulse signal can be made periodic,
7. The timing signal generation method according to claim 6, further comprising a predetermined duty ratio.