CN1033431A - Improvement scheme of time delay circuit - Google Patents
Improvement scheme of time delay circuit Download PDFInfo
- Publication number
- CN1033431A CN1033431A CN 87108116 CN87108116A CN1033431A CN 1033431 A CN1033431 A CN 1033431A CN 87108116 CN87108116 CN 87108116 CN 87108116 A CN87108116 A CN 87108116A CN 1033431 A CN1033431 A CN 1033431A
- Authority
- CN
- China
- Prior art keywords
- circuit
- delay circuit
- scheme
- resistance
- delay
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
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Classifications
-
- G—PHYSICS
- G04—HOROLOGY
- G04F—TIME-INTERVAL MEASURING
- G04F1/00—Apparatus which can be set and started to measure-off predetermined or adjustably-fixed time intervals without driving mechanisms, e.g. egg timers
- G04F1/005—Apparatus which can be set and started to measure-off predetermined or adjustably-fixed time intervals without driving mechanisms, e.g. egg timers using electronic timing, e.g. counting means
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Pulse Circuits (AREA)
- Networks Using Active Elements (AREA)
Abstract
Improvement scheme of time delay circuit of the present invention relates to electronic technology field, and the input signal that invention has proposed to have now rc delay network in the analog delay circuit is changed into the scheme that changes the signal of telecommunication by the dc constant voltage signal of telecommunication.Thereby decide the situation of delay time before having changed by resistance-capacitance network.After this scheme is applied to analog delay circuit, reaching under same timing range (particularly very wide timing range) and the precision situation, circuit is easy to implement.Most of circuit devcies can be made in the same integrated circuit.Peripheral timing capacitor capacity and potentiometer resistance are all much smaller than the same generic request of prior art.Cost can reduce significantly.
Description
The present invention relates to electronic technology field.
In actual life, timing circuit has a wide range of applications.The various combination mode of electronic device.Can constitute multi-form and timing circuits characteristics.Conclusion is got up, and the realization of these combinations can be divided into two big classes; One class is the analog circuit method, and another kind of is the digital circuit method.
When the timing wide region that requires timing circuit adjustable (such as from somewhat by several hours, tens hours are adjustable continuously) time, the cost of existing above-mentioned two kinds of methods all will improve, even also be difficult to carry out after raising the cost.
Analog circuit will reach above-mentioned requirements, and general method is to strengthen resistance in the time delay network, the value of electric capacity.But, accomplish that wide region is adjustable then very difficult, cost improves.
Though digital circuit can reach above-mentioned requirements, cost will improve.And digital circuit will be equipped with record toward contact and show circuit or keyboard.
The present invention will overcome the above-mentioned deficiency of existing timing circuit, make the circuit that comes out according to the invention conceptual design in that to reach same wide region regularly adjustable continuously, under the constant prerequisite of precision, reduce circuit cost significantly, reduce requirement circuit element than existing implementation.
Linear superposition theorem in the application circuit basic theories of the present invention (overall response of linear circuit is the principle of each input response sum) is changed into the input of the variation signal of telecommunication with the constant signal of telecommunication input of being adopted (constant voltage charge) to the time-delay resistance-capacitance network in the past.The present invention adopts wherein: the continuously adjustable pulse input signal of duty ratio makes that the charging interval of electric capacity is not only depended on the time constant of resistance-capacitance network in the time delay network, and depends on the duty ratio of input signal under the constant situation of capacitance-resistance value.
Circuit according to the invention design can be implemented under the similarity condition, the regularly requirement of the unapproachable wide region of the delay circuit that prior art is made.Utilize existing industrial technology.Most of element in the new-type circuit can also be made integrated circuit.Electric capacity in the peripheral circuit and potentiometer all greatly reduce than capability value and the resistance that prior art requires.
Invention has realized the performance that prior art is difficult to realize under the prerequisite that reduces cost, have a wide range of applications.
Adopt exemplary embodiments that the principle of the invention makes integrated circuit (IC)-components as shown in drawings.Solid line is partly represented integrated circuit among the figure, and dotted portion is represented peripheral cell, and circuit theory is as follows:
Operational amplifier LM
1And LM
2And resistance R
1-R
5, R, capacitor C
1, diode D
1-D
3Deng the continuously adjustable pulse generator of common formation duty ratio.Control capacittance C
1And resistance R
2Value, can change pulse frequency.Regulate the value of resistance R.Can change duty ratio.
Operational amplifier LM
3And resistance R
6, R
7, capacitor C
2, diode D
4Deng the formation delay circuit.This partial circuit combines with foregoing circuit, can constitute the regularly continuous conditioned circuit of wide region.
K switch in resistance
5When closed, amplifier LM
4And resistance R
8-R
10Diode D
5, D
6Deng the formation Schmidt circuit.Whole delay circuit operation principle is as follows:
After the circuit energized, impulse circuit is with certain duty cycle pulse capacitor C in time delay network
2Charging.In capacitor C
2Voltage is lower than LM
3Comparative voltage before, amplifier LM
3Output low level, amplifier LM
4The output high level.In capacitor C
2Voltage surpasses LM
3Behind the comparative voltage, LM
3Output becomes high level by low level.Capacitor C
2Voltage continues to rise, when surpassing LM
4Comparative voltage (upper limit turnover voltage of Schmidt circuit) after, LM
4Output becomes low level by high level.At this moment, LM
4Comparative voltage step-down (the lower limit turnover voltage of Schmidt circuit), capacitor C
2By diode D
5And LM
4Capacitor C is worked as in discharge
2Voltage drops to and is lower than LM
3Behind the comparative voltage, LM
3Become low level by the output high level.Work as capacitor C
2Voltage drops to and is lower than LM
4During comparative voltage, LM
4Become high level by output low level, capacitor C
2Stop discharge, circuit enters a timing cycle
K switch in circuit
5When not closed, after circuit reaches regularly, LM
3Output keeps high level, until artificially with capacitor C
2The voltage zero clearing.
Operational amplifier in the circuit is the LM type.
Claims (1)
- Invention relates to electronic technology field.Existing rc delay network is by changing discharging and recharging of capacitance-resistance value Control Network electric capacity.Feature of the present invention is: the discharging and recharging of the input signal Control Network electric capacity by changing rc delay network.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 87108116 CN1010146B (en) | 1987-12-01 | 1987-12-01 | Improvement scheme of time delay circuit |
| JP63305008A JPH01212021A (en) | 1987-12-01 | 1988-11-30 | Timing circuit and method of generating timing signal |
| BE8801357A BE1002165A5 (en) | 1987-12-01 | 1988-12-01 | Clock circuit. |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 87108116 CN1010146B (en) | 1987-12-01 | 1987-12-01 | Improvement scheme of time delay circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1033431A true CN1033431A (en) | 1989-06-14 |
| CN1010146B CN1010146B (en) | 1990-10-24 |
Family
ID=4816368
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 87108116 Expired CN1010146B (en) | 1987-12-01 | 1987-12-01 | Improvement scheme of time delay circuit |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JPH01212021A (en) |
| CN (1) | CN1010146B (en) |
| BE (1) | BE1002165A5 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108199702A (en) * | 2018-03-02 | 2018-06-22 | 曙光信息产业(北京)有限公司 | Delay circuit |
-
1987
- 1987-12-01 CN CN 87108116 patent/CN1010146B/en not_active Expired
-
1988
- 1988-11-30 JP JP63305008A patent/JPH01212021A/en active Pending
- 1988-12-01 BE BE8801357A patent/BE1002165A5/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108199702A (en) * | 2018-03-02 | 2018-06-22 | 曙光信息产业(北京)有限公司 | Delay circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01212021A (en) | 1989-08-25 |
| BE1002165A5 (en) | 1990-08-28 |
| CN1010146B (en) | 1990-10-24 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C13 | Decision | ||
| GR02 | Examined patent application | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C19 | Lapse of patent right due to non-payment of the annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |