JPH01209737A - Semiconductor manufacturing apparatus - Google Patents

Semiconductor manufacturing apparatus

Info

Publication number
JPH01209737A
JPH01209737A JP63035637A JP3563788A JPH01209737A JP H01209737 A JPH01209737 A JP H01209737A JP 63035637 A JP63035637 A JP 63035637A JP 3563788 A JP3563788 A JP 3563788A JP H01209737 A JPH01209737 A JP H01209737A
Authority
JP
Japan
Prior art keywords
semiconductor wafer
heat treatment
processing
heat
time
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP63035637A
Other languages
Japanese (ja)
Other versions
JP2660285B2 (en
Inventor
Osamu Hirakawa
修 平河
Masami Akumoto
飽本 正己
Yoshio Kimura
義雄 木村
Mitsuru Ushijima
満 牛島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Electron Ltd
Tokyo Electron Kyushu Ltd
Original Assignee
Tokyo Electron Ltd
Tokyo Electron Kyushu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Electron Ltd, Tokyo Electron Kyushu Ltd filed Critical Tokyo Electron Ltd
Priority to JP3563788A priority Critical patent/JP2660285B2/en
Publication of JPH01209737A publication Critical patent/JPH01209737A/en
Application granted granted Critical
Publication of JP2660285B2 publication Critical patent/JP2660285B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)

Abstract

PURPOSE:To make it possible to perform processing characterized by high throughputs, by providing a conveying mechanism comprising a conveying part which conveys bodies under processing into a heat treating mechanism and a standby part which temporarily holds the bodies under processing. CONSTITUTION:Four juxtaposed hot plates 110, 111, 112 and 113 are provided in a heat-treating mechanism 115 and a semiconductor wafer 114 is heat-treated there. A conveying mechanism 118 comprising a conveying part 116 and a standby part 117 is provided in the vicinity of the heat treating mechanism 115. The conveying part 116 can be moved in the lateral direction X in parallel with the mechanism 115 and sucks and holds the semiconductor wafer 114. The standby part 117 has a mounting stage for temporarily holding the semiconductor wafer 114. Both the number of the hot plates (n) and an allowance time 122Tw are set and controlled with respect to a cycle time T. Thus said cycle time can be synchronized with the cycle times of processing mechanisms other than the heat-treating mechanism. The decrease in throughputs of the apparatus can be prevented by the heat-treating time of the heat-treating mechanism.

Description

【発明の詳細な説明】 〔発明の目的〕 (産業上の利用分野) 本発明は半導体製造装置に関する。[Detailed description of the invention] [Purpose of the invention] (Industrial application field) The present invention relates to semiconductor manufacturing equipment.

(従来の技術) 半導体製造装置において、半導体ウェハに回路パターン
を形成する工程中の一装置として、例えば、フォトレジ
スト塗布現像装置が用いられている。そして、このフォ
トレジスト塗布現像装置は、複数の処理機構例えば、半
導体ウェハ表面の洗浄機構、この洗浄に使用した純水な
どの水分を乾燥除去する疎水熱処理機構、半導体ウェハ
とフォトレジスト膜との密着性を向上するために行うH
MDS処理機構、半導体ウェハにフォトレジストを塗布
するフォトレジスト塗布機構、塗布されたフォトレジス
ト中に残存する溶剤を加熱蒸発させるプリベーク機構、
露光されたフォトレジストを現像する現像機構、現像に
よってパターン形成されたフォトレジストに残留する現
像液を蒸発除去し、半導体ウェハとフォトレジストとの
密着性を強化するためのボストベーク機構、フォトレジ
ストパターンの耐熱性を向上させるためのレジストキュ
ア機構などを備え、半導体ウェハを連続して処理する構
成のものである。
(Prior Art) In semiconductor manufacturing equipment, a photoresist coating and developing device, for example, is used as one device in the process of forming a circuit pattern on a semiconductor wafer. This photoresist coating and developing device has multiple processing mechanisms, such as a cleaning mechanism for the surface of the semiconductor wafer, a hydrophobic heat treatment mechanism for drying and removing water such as pure water used for this cleaning, and a mechanism for adhesion between the semiconductor wafer and the photoresist film. H done to improve sex
an MDS processing mechanism, a photoresist coating mechanism that applies photoresist to a semiconductor wafer, a pre-bake mechanism that heats and evaporates the solvent remaining in the applied photoresist;
A development mechanism that develops the exposed photoresist, a post-bake mechanism that evaporates and removes the developer remaining on the photoresist patterned by development and strengthens the adhesion between the semiconductor wafer and the photoresist, and a post-bake mechanism that develops the photoresist pattern. It is equipped with a resist curing mechanism to improve heat resistance and is configured to process semiconductor wafers continuously.

そして上記各機構間を例えばベルトを使用した搬送機構
で接続し、半導体ウェハを連続して処理するように構成
されている。
Each of the above-mentioned mechanisms is connected by a conveyance mechanism using a belt, for example, so that semiconductor wafers can be processed continuously.

しかし、近年VLSIの集積度が高まるにつれ、例えば
レジスト処理工程もより複雑となり、処理工程数および
処理工程の種類も増大している。
However, as the degree of integration of VLSIs has increased in recent years, for example, resist processing steps have become more complex, and the number and types of processing steps have also increased.

上記説明の装置では固定した連続処理は可能であるが、
この連続処理のプロセスの中に例えばレジスト多層塗布
や他の処理工程を追加したり、またはある処理工程を削
除するというようなことは不可能である。
Although fixed continuous processing is possible with the device described above,
It is impossible to add, for example, resist multilayer coating or other processing steps to this continuous processing process, or to delete certain processing steps.

」二足の事情により、処理工程の追加、削除、変更など
が可能で、複雑な処理工程に対応できるように1例えば
処理機構と搬送機構とを分離した構成の装置が要望され
ている。
Due to these two circumstances, there is a demand for an apparatus having a structure in which, for example, a processing mechanism and a transport mechanism are separated so that it is possible to add, delete, or change processing steps, and to cope with complex processing steps.

この装置例として、次に述べるようなものがある。An example of this device is as described below.

第4図(a)(b)に示すように、主搬送機構■の周囲
に、半導体ウェハ■のローダ−■、アンローダ−け)、
処理機WA■、処理機構B■、熱処理機構■などを配置
する。この熱処理機構■は例えば4個の熱板(8)■)
(10) (11)を垂直に多段配置し、この下位置に
移載用載置台(12)を配置する。また、この熱処理機
構ω近傍に副搬送機構A (13)、副搬送機構B (
14)を設ける。そして、ローダ−(3)から半導体ウ
ェハ■を取り出して主搬送機構■により例えば処理部A
(ハ)にセントし、半導体ウェハ■を処理する。この処
理が終ると主搬送機構(1)により上記半導体ウェハ(
2)を移載用載置台(12)にセットし1次にこの半導
体ウェハ■を副搬送機構A (13)で熱処理機構■の
熱板(8)→熱板(11)へと処理に応じて移す。そし
て、最上段の熱板(11)での熱処理が終了すると、半
導体ウェハ■を副搬送機構B(14)により搬送して移
載用載置台(12)にセットする。この移送用載置台(
12)上の半導体ウェハ■を主搬送機構α)で搬出して
アンローダ−(イ)に収納する。
As shown in FIGS. 4(a) and 4(b), around the main transfer mechanism
A processing machine WA■, a processing mechanism B■, a heat treatment mechanism ■, etc. are arranged. This heat treatment mechanism (■) consists of, for example, four heating plates (8) (■)
(10) (11) are vertically arranged in multiple stages, and a transfer mounting table (12) is arranged below this. Also, in the vicinity of this heat treatment mechanism ω, sub-transport mechanism A (13) and sub-transport mechanism B (
14). Then, the semiconductor wafer (■) is taken out from the loader (3) and moved to the processing section A by the main transport mechanism (■).
(c) and process the semiconductor wafer ■. When this process is finished, the main transport mechanism (1) transfers the semiconductor wafer (
2) is set on the transfer stage (12), and then the semiconductor wafer ■ is transferred by the sub-transfer mechanism A (13) from the hot plate (8) to the hot plate (11) of the heat treatment mechanism ■ according to the processing. and move it. When the heat treatment on the uppermost heating plate (11) is completed, the semiconductor wafer (2) is transported by the sub-transfer mechanism B (14) and set on the transfer stage (12). This transfer platform (
12) The upper semiconductor wafer (2) is carried out by the main transport mechanism (α) and stored in the unloader (A).

また、第5図に示すように、搬送機構(15)の移動経
路(16)に沿って、例えば手前側にローダ−(17)
、7’zo−ダー(18)、処理機t’il A (1
9)、処理機構B (20)を並設し、また向う側に熱
処理機構(21)として4個の熱板(22) (23)
 (24) (25)を並設する。そして、ローダ−(
17)から半導体ウェハ(26)を取り出して搬送機構
(15)で搬送して例えば処理機構A (19)にセッ
トして処理をする。この処理が終ると搬送機構(15)
により処理機構A (19)から半導体ウェハ(26)
を搬出し、熱板(22)上にセットして熱処理を開始す
る。続いて、別の半導体ウェハ(26)をローダ−(1
7)から取り出し、上記同様の動作にて熱板(23) 
(24) (25)にセットする。熱処理機構(21)
における熱処理が終ると搬送機構(15)により該当す
る上記熱板例えば熱板(22)から半導体ウェハ(26
)を搬出し、アンローダ−(18)に収納する。
Further, as shown in FIG. 5, a loader (17) is mounted on the front side along the movement path (16) of the transport mechanism (15).
, 7'zo-der (18), processor t'il A (1
9), treatment mechanism B (20) is installed in parallel, and four hot plates (22) (23) are installed as a heat treatment mechanism (21) on the opposite side.
(24) and (25) are installed in parallel. And the loader (
A semiconductor wafer (26) is taken out from 17), transported by a transport mechanism (15), and set in, for example, a processing mechanism A (19) for processing. When this process is finished, the transport mechanism (15)
Processing mechanism A (19) to semiconductor wafer (26)
is carried out, set on a hot plate (22), and heat treatment is started. Next, another semiconductor wafer (26) is loaded onto the loader (1).
7) and remove it from the hot plate (23) using the same operation as above.
(24) Set to (25). Heat treatment mechanism (21)
After the heat treatment is completed, the transfer mechanism (15) transfers the semiconductor wafer (26) from the corresponding hot plate, for example, the hot plate (22).
) is carried out and stored in the unloader (18).

(発明が解決しようとする課題) しかしながら、上記装置にはそれぞれ次に述べるような
問題点がある。
(Problems to be Solved by the Invention) However, each of the above devices has the following problems.

前者においては、副搬送機構が2個必要であり。In the former case, two sub-transport mechanisms are required.

また主搬送機構のサイクル時間と加熱処理時間との整合
をとるために上記副搬送機構の動作を制御することが必
要となる。例えば、主搬送機構が動作中であれば加熱処
理が終了した半導体ウェハを加熱処理機構から搬出でき
ず、結果として上記処理機構の熱板から熱板への半導体
ウェハの移載の際に待ち時間、すなわち熱処理を中断す
る時間が発生する。
Furthermore, it is necessary to control the operation of the sub-transport mechanism in order to match the cycle time of the main transport mechanism with the heat treatment time. For example, if the main transport mechanism is in operation, semiconductor wafers that have been heated cannot be removed from the heat treatment mechanism, resulting in a waiting time when transferring semiconductor wafers from one hot plate to another in the processing mechanism. In other words, it takes time to interrupt the heat treatment.

一方、後者においては、熱処理時間は使用されるレジス
トに応じて極めて精密に管理する必要があるために、熱
処理時間を管理すべく搬送機構を動作させようとすると
、装置のスループットが著しく低下する可能性がある。
On the other hand, in the latter case, the heat treatment time needs to be managed extremely precisely depending on the resist used, so if you try to operate the transport mechanism to manage the heat treatment time, the throughput of the device may drop significantly. There is sex.

すなわち、上記熱処理時間は熱板の個数を変更すること
によっである範囲内において調整可能であるが、熱板の
個数をnとした場合、装置のサイクル時間Tに対しnT
待時間限定される段階的な時間しか選択できず、その中
間の時間の制御は不可能である。
In other words, the above heat treatment time can be adjusted within a certain range by changing the number of hot plates, but if the number of hot plates is n, then nT
Only a limited waiting time can be selected in stages, and it is impossible to control the time in between.

したがって、装置のサイクル時間Tを変えることとなる
が、装置のサイクル時間Tは他の処理機構の処理時間に
も影響されるもので、装置のスループットは最も遅い処
理機構の処理時間に対し。
Therefore, the cycle time T of the device is changed, but the cycle time T of the device is also affected by the processing times of other processing mechanisms, and the throughput of the device is based on the processing time of the slowest processing mechanism.

それ以上の時間の熱処理サイクル時間に設定しなければ
ならない。
The heat treatment cycle time must be set to a longer time than that.

例えば、最も遅い処理機構の処理時間が51秒で熱処理
時間が150秒であれば、熱板を3個として50秒間で
は処理できず、この場合熱板を2個として75秒サイク
ルとせざるを得す、著しくスループットが低下する。
For example, if the processing time of the slowest processing mechanism is 51 seconds and the heat treatment time is 150 seconds, processing cannot be completed in 50 seconds using 3 hot plates, and in this case, it is necessary to use 2 hot plates and perform a 75 second cycle. However, throughput decreases significantly.

本発明は上述の従来事情に対処してなされたもので、ス
ループットの高い半導体製造装置を提供しようとするも
のである。
The present invention has been made in response to the above-mentioned conventional situation, and is intended to provide a semiconductor manufacturing apparatus with high throughput.

〔発明の構成〕[Structure of the invention]

(課題を解決するための手段) すなわち本発明は、複数の処理機構に被処理体を搬送し
て処理する半導体製造装置において、熱処理機構に被処
理体を搬送する搬送部および上記被処理体を一時的に待
機させる待機部からなる搬送機構を備えたことを特徴と
する。
(Means for Solving the Problems) That is, the present invention provides a semiconductor manufacturing apparatus that transports objects to be processed to a plurality of processing mechanisms for processing, which includes a transport unit that transports objects to be processed to a heat treatment mechanism, and a transport section that transports objects to be processed. The present invention is characterized in that it includes a transport mechanism that includes a standby section that temporarily stands by.

(作 用) 本発明半導体製造装置では、熱処理機構に被処理体を搬
送する搬送部および上記被処理体を一時的に待機させる
待機部からなる搬送機構を備えているので、この搬送機
構に生じる余裕時間を調整することにより、上記熱処理
機構の熱処理時間を変更することができる。
(Function) The semiconductor manufacturing apparatus of the present invention is equipped with a transport mechanism consisting of a transport section that transports the object to be processed to the heat treatment mechanism and a standby section that temporarily waits for the object to be processed. By adjusting the margin time, the heat treatment time of the heat treatment mechanism can be changed.

(実施例) 以下、本発明半導体製造装置を塗布現像装置に適用した
一実施例を図面を参照して説明する。
(Example) Hereinafter, an example in which the semiconductor manufacturing apparatus of the present invention is applied to a coating and developing apparatus will be described with reference to the drawings.

本体(101)の中央部付近には、被処理体例えば半導
体ウェハ(102)を吸着保持し伸縮自在に構成された
ピンセット(図示せず)を有し、横(X)方向の移動経
路(103)上を移動可能で且つ上記ピンセット(図示
せず)を回転(θ)可能に構成された主搬送機構(10
4)が設けられている。
Near the center of the main body (101), there are tweezers (not shown) that are configured to be extendable and retractable and hold an object to be processed, such as a semiconductor wafer (102), by suction, and are arranged along a movement path (103) in the lateral (X) direction. ) and is configured to be able to rotate (θ) the tweezers (not shown).
4) is provided.

次に、この主搬送機構(104)の移動経路(103)
の手前側には、複数の処理機構例えば処理前の半導体ウ
ェハ(102)を収納するローダ−機構(105)、処
理終了後の半導体ウェハ(106)を収納するアンロー
ダ−機構(107)、半導体ウェハ(102)上にフォ
トレジストを塗布する塗布機構(108) 、半導体ウ
ェハ(102)上の露光されたフォトレジストを現像す
る現像機構(109)が並置されている。そして、上記
主搬送機構(104)により半導体ウェハ(102)を
上記各機構に任意に搬送可能に構成されている。
Next, the movement path (103) of this main transport mechanism (104)
On the front side, there are a plurality of processing mechanisms, such as a loader mechanism (105) for storing semiconductor wafers (102) before processing, an unloader mechanism (107) for storing semiconductor wafers (106) after processing, and a semiconductor wafer. A coating mechanism (108) for coating photoresist on the semiconductor wafer (102) and a development mechanism (109) for developing the exposed photoresist on the semiconductor wafer (102) are juxtaposed. The main transport mechanism (104) is configured to transport the semiconductor wafer (102) to each of the mechanisms as desired.

一方、上記移動経路(103)の向う側には、例えば並
置された4個の熱板(110) (111) (112
) (113)を有し、半導体ウェハ(114)を載置
して加熱処理する熱処理機構(115)が配置されてい
る。そして、処理プロセスに応じて例えば、塗布された
フォトレジスト中に残存する溶剤を加熱蒸発させるプリ
ベーク処理、現像によってパターン形成されたフォトレ
ジストに残留する現像液を蒸発除去し半導体ウェハとフ
ォトレジストとの密着性を強化するためのポストベーク
処理に使用される。
On the other hand, on the other side of the movement path (103), there are, for example, four hot plates (110) (111) (112) arranged in parallel.
) (113), and a heat treatment mechanism (115) for placing and heat-treating a semiconductor wafer (114) is disposed. Then, depending on the processing process, for example, a pre-bake treatment is performed to heat and evaporate the solvent remaining in the applied photoresist, and a developer solution remaining in the patterned photoresist is removed by evaporation to remove the semiconductor wafer and the photoresist. Used in post-bake treatment to strengthen adhesion.

上記熱処理機構(115)の近傍には、この熱処理機構
(115)と並行する如く横(X)方向に移動可能で、
半導体ウェハ(114)を例えば吸着保持し伸縮自在に
構成されたピンセット(図示せず)を有した搬送部(1
16)および上記半導体ウェハ(114)を−時的に待
機させる載置台を有する待機部(117)からなる搬送
機構(118)が設けられている。そして、上記待機部
(117)と熱処理機構(115)間で任意に半導体ウ
ェハ(114)が搬送可能に構成されている。
In the vicinity of the heat treatment mechanism (115), there is a movable member that can move in the lateral (X) direction parallel to the heat treatment mechanism (115);
A transport section (1
16) and a waiting section (117) having a mounting table on which the semiconductor wafer (114) is temporarily placed on standby. The semiconductor wafer (114) can be arbitrarily transferred between the standby section (117) and the heat treatment mechanism (115).

また、上記待機部(117)を介して上記搬送機構(1
18)と主搬送機構(104)間で半導体ウェハ(11
4)の受は渡しが可能に構成されている。
Further, the transport mechanism (1
18) and the main transport mechanism (104).
4) The receiver is configured to allow handing over.

次に動作を説明する。先ず、主搬送機構(104)によ
り例えば現像処理すべき半導体ウェハ(102)をロー
ダ−機構(tOS)から搬出して、現像機構(109)
にセットし、現像処理を開始する。
Next, the operation will be explained. First, the main transport mechanism (104) carries out, for example, a semiconductor wafer (102) to be developed from the loader mechanism (tOS), and transfers it to the developing mechanism (109).
and start the development process.

現像機構(109)によって現像処理を終了した半導体
ウェハ(102)を主搬送機構(104)によって現像
機構(109)より搬出し、移動経路(103)上を左
方向に搬送し、上記半導体ウェハ(102)を搬送機構
(118)の待機部(117)に載置する。
The semiconductor wafer (102), which has been developed by the developing mechanism (109), is carried out from the developing mechanism (109) by the main conveying mechanism (104) and conveyed to the left on the moving path (103). 102) is placed on the standby section (117) of the transport mechanism (118).

そして、搬送機構(118)の搬送部(116)によっ
て待機部(117)に載置されている半導体ウェハ(1
02)を保持して搬送し、熱処理機構(ttS)の例え
ば熱板(113)にセットしてポストベーク処理を開始
する。
The semiconductor wafer (1) placed on the standby section (117) by the transfer section (116) of the transfer mechanism (118)
02) is held and transported, set on, for example, a hot plate (113) of a heat treatment mechanism (ttS), and post-bake processing is started.

一方、主搬送機構(104)で、次に現像処理すべき半
導体ウェハ(102)をローダ−機構(tOS)から搬
出し、現像機構(109)に搬送セットして現像処理を
開始する。
On the other hand, the main transport mechanism (104) carries out the semiconductor wafer (102) to be developed next from the loader mechanism (tOS), transports and sets it in the developing mechanism (109), and starts the development process.

次に、現像機構(109)によって現像処理を終了した
半導体ウェハ(102)を主搬送機構(104)によっ
て現像機構(109)より搬出し、移動経路(103)
上を左方向に搬送し、上記半導体ウェハ(102)を搬
送機構(118)の待機部(117)に載置する。そし
て、搬送機構(118)の搬送部(116)によって待
機部(117)に載置されている半導体ウェハ(102
)を保持して搬送し、熱処理機構(115)の例えば熱
板(112)にセットしてボストベーク処理を開始する
Next, the semiconductor wafer (102) which has been developed by the developing mechanism (109) is carried out from the developing mechanism (109) by the main transport mechanism (104), and is transferred to the moving path (103).
The semiconductor wafer (102) is then transported to the left and placed on the standby section (117) of the transport mechanism (118). The semiconductor wafer (102) placed on the standby section (117) by the transfer section (116) of the transfer mechanism (118)
) is held and conveyed, and set on, for example, a hot plate (112) of a heat treatment mechanism (115), and the boss bake process is started.

一方、主搬送機構(104)で、次に現像すべき半導体
ウェハ(102)をローダ−機構(105)から搬出し
、現像機構(109)に搬送セットして現像処理を開始
する。
On the other hand, the main transport mechanism (104) carries out the semiconductor wafer (102) to be developed next from the loader mechanism (105), transports and sets it in the developing mechanism (109), and starts the developing process.

上記動作を繰返し、熱処理機構(115)の熱板(11
1) (110)にも半導体ウェハ(102)をセット
してボストベーク処理を行う。
The above operation is repeated, and the hot plate (11) of the heat treatment mechanism (115) is
1) A semiconductor wafer (102) is also set in (110) and a boss bake process is performed.

そして、最初にボストベーク処理を開始した熱板(11
3)における所定時間の熱処理が終了すると、搬送部(
116)によって熱処理の終了した半導体ウェハ(11
4)を熱処理機構(115)から搬出して、待機部(1
17)に載置する。次に、主搬送機構(104)によっ
て、上記待機部(117)に載置されている上記半導体
ウェハ(114)を搬出し、アンローダ−機構(107
)に収納する。このあと、熱板(113)には、上記説
明した動作にしたがって現像処理の終了した半導体ウェ
ハ(ioz)をセットしてボストベーク処理を開始する
Then, the hot plate (11
When the heat treatment for the predetermined time in step 3) is completed, the transport section (
Semiconductor wafer (116) which has been heat-treated by
4) from the heat treatment mechanism (115) and put it in the standby section (1
17). Next, the main transport mechanism (104) carries out the semiconductor wafer (114) placed on the standby section (117), and the unloader mechanism (107)
). Thereafter, the semiconductor wafer (IOZ) that has been developed according to the above-described operation is set on the hot plate (113), and the post-bake process is started.

上記動作において、第2図に示すように主搬送機構(1
04)のサイクル時間(119)をTとした場合、次の
ようなサイクルにて処理を行う。
In the above operation, the main transport mechanism (1
If the cycle time (119) of 04) is T, processing is performed in the following cycle.

すなわち、主搬送機構(104)が待機部(117)に
載置されている熱処理の終了した熱板(113)からの
半導体ウェハ(114)を搬出し1次に熱処理すべき半
導体ウェハ(102)を上記待機部(117)に載置す
るまでの主搬送機構稼動時間(120)Ta経過後に、
搬送部(116)は上記半導体ウェハ(102)を保持
して搬送し搬入時間(121) Tbにて熱板(113
)に搬入セットする。
That is, the main transport mechanism (104) carries out the semiconductor wafer (114) from the heated plate (113) that has been subjected to heat treatment and is placed in the standby section (117), and transfers the semiconductor wafer (102) to the semiconductor wafer (102) to be subjected to the primary heat treatment. After the main transport mechanism operating time (120) Ta has elapsed until the main transport mechanism is placed on the standby section (117),
The transport section (116) holds and transports the semiconductor wafer (102), and transfers it to the hot plate (113) at a transport time (121) Tb.
) and set it up.

そして、搬送機構(118)の搬送部(116)は余裕
時間(122)Tv待機した後、熱板(112)から搬
出時間(123)Tcにて半導体ウェハ(114)を搬
出し、待機部(117)に載置する。このサイクルを熱
板(113)〜(110)において繰返す。
Then, the transport unit (116) of the transport mechanism (118) waits for a margin time (122) Tv, and then unloads the semiconductor wafer (114) from the hot plate (112) at an unloading time (123) Tc. 117). This cycle is repeated on hot plates (113) to (110).

ここで、上記熱板における実質熱処理時間(124)T
mは、熱板の数をn個とすると、Tm=nT−(T−T
b−T、v)=(n −1)T+(Tb+Tw)となり
、搬送部(116)の余裕時間(121) Tvを調整
することにより熱処理時間(124) T+aを制御す
ることが可能となる。
Here, the actual heat treatment time on the hot plate (124)T
m is Tm=nT-(T-T
b-T,v)=(n-1)T+(Tb+Tw), and by adjusting the margin time (121) Tv of the transport section (116), it becomes possible to control the heat treatment time (124) T+a.

上記余裕時間(121)Twは、主搬送機構(104)
のサイクル時間(119) Tより大きくなることはな
いが、上記主搬送稼動時間(120)Ta、搬入時間(
121)Tb、 Wi出待時間123)Tcを小さくす
ることにより。
The above margin time (121) Tw is the main transport mechanism (104)
Although the cycle time (119) of
121) Tb, Wi waiting time 123) By reducing Tc.

かなりの範囲にて調整可能となる。It can be adjusted within a considerable range.

したがって、上記サイクル時間(119) Tに対して
、熱板数nと余裕時間(122)Tw双方を設定制御す
ることにより、熱処理機構以外の処理機構のサイクル時
間との同期をとることが可能となり、熱処理機構の熱処
理時間により装置のスループットが低下するのを防ぐこ
とができる。
Therefore, by setting and controlling both the number of hot plates n and the margin time (122) Tw for the above cycle time (119) T, it becomes possible to synchronize with the cycle time of processing mechanisms other than the heat treatment mechanism. , it is possible to prevent the throughput of the apparatus from decreasing due to the heat treatment time of the heat treatment mechanism.

次に、本発明半導体製造装置の他の一実施例を図面を参
照して説明する。第3図(a)(b)において、先の実
施例と異なるところは、熱処理機構(215)の熱板(
210) (211) (212) (213)を垂直
方向に多段積みに構成し、且つ、同様な構成の熱処理機
構(315)を1個増やして2個設けたこと、搬送機構
(218)を上下動可能な2個の搬送部(216) (
316)および上記熱処理機構(215) (315)
の下方に配置した2個の待機部(217) (317)
で構成したこと、および塗布機構(tOa)、現像機構
(109)の左右にそれぞれローダ−機構(105)ア
ンローダ−機構(106)を配置した点である。
Next, another embodiment of the semiconductor manufacturing apparatus of the present invention will be described with reference to the drawings. In FIGS. 3(a) and 3(b), the difference from the previous embodiment is that the heating plate (
210) (211) (212) (213) are vertically stacked in multiple stages, and two heat treatment mechanisms (315) with the same configuration are added by one, and the transport mechanism (218) is vertically stacked. Two movable transport units (216) (
316) and the heat treatment mechanism (215) (315)
Two standby sections (217) (317) placed below the
and that a loader mechanism (105) and an unloader mechanism (106) are arranged on the left and right sides of the coating mechanism (tOa) and the developing mechanism (109), respectively.

なお、動作は先の実施例と同様であり、ここでは説明を
省略する。この実施例では、熱処理機構(215) (
315)の各熱板を垂直方向に多段積みに構成している
ので装置の床面積を低減できるほか、主搬送機構(10
4)と待機部(217) (317)の高さを同一にす
れば上記主搬送機構(104)の垂直方向への移動をな
くすこともできる。
Note that the operation is the same as in the previous embodiment, and the explanation will be omitted here. In this example, the heat treatment mechanism (215) (
The heating plates of the main transport mechanism (10
4) and the standby section (217) (317), it is possible to eliminate vertical movement of the main transport mechanism (104).

したがって、主搬送機構の構成が簡素となるほかに、垂
直方向の移動をなくすことにより上記主搬送機構の移動
速度を速くすることができるので、装置のスループット
を高くすることができる。
Therefore, in addition to simplifying the configuration of the main transport mechanism, the moving speed of the main transport mechanism can be increased by eliminating vertical movement, so that the throughput of the apparatus can be increased.

なお、上記実施例では、複数の処理機構とじて塗布機構
、現像機構、熱処理機構を配置したものについて説明し
たが、本発明はかかる実施例に限定されるものではなく
他の処理機構、例えば洗浄機構、疎水熱処理機構、HM
DS処理機構、レジストキュア機構など、実際のプロセ
スに対応して組合せ配置してもよい。
In the above embodiment, a coating mechanism, a developing mechanism, and a heat treatment mechanism are arranged as a plurality of processing mechanisms. However, the present invention is not limited to this embodiment, and other processing mechanisms, such as cleaning mechanism, hydrophobic heat treatment mechanism, HM
The DS processing mechanism, resist cure mechanism, etc. may be combined and arranged in accordance with the actual process.

また、上記実施例では、現像処理を行う場合について説
明したが、フォトレジスト塗布処理の場合には、塗布機
構(108)を使用し、熱処理機構(115)、(21
5)、 (315)をプリベーク処理として使用し、上
記説明と同様な動作で処理を行うことができる。
Further, in the above embodiment, the case where development processing is performed was explained, but in the case of photoresist coating processing, the coating mechanism (108) is used, and the heat treatment mechanism (115), (21
5) and (315) can be used as a pre-bake process, and the process can be performed in the same manner as described above.

〔発明の効果〕〔Effect of the invention〕

上述のように、本発明半導体製造装置によれば高スルー
プツトの処理が可能となる。
As described above, the semiconductor manufacturing apparatus of the present invention enables high throughput processing.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明半導体製造装置を塗布現像装置に適用し
た一実施例を示す構成図、第2図は第1図の動作説明図
、第3図は第1図の他の一実施例を示す構成図、第4図
および第5図は従来例を示す図である。 104・・・主搬送機構、 115、215.315・・・熱処理機構、116.2
16,316・・・搬送部。 117.217,317・・・待機部、118.218
・・・搬送機構。 特許出願人 東京エレクトロン株式会社テ ル 九 州
 株式会社 第3図
FIG. 1 is a configuration diagram showing an embodiment in which the semiconductor manufacturing apparatus of the present invention is applied to a coating and developing device, FIG. 2 is an explanatory diagram of the operation of FIG. 1, and FIG. The configuration diagrams shown in FIGS. 4 and 5 are diagrams showing conventional examples. 104... Main transport mechanism, 115, 215.315... Heat treatment mechanism, 116.2
16,316...Transportation section. 117.217,317...Standby section, 118.218
...transport mechanism. Patent applicant Tokyo Electron Ltd. Tel Kyushu Ltd. Figure 3

Claims (1)

【特許請求の範囲】[Claims]  複数の処理機構に被処理体を搬送して処理する半導体
製造装置において、熱処理機構へ被処理体を搬送する搬
送部、および上記被処理体を一時的に待機させる待機部
からなる搬送機構を備えたことを特徴とする半導体製造
装置。
A semiconductor manufacturing apparatus that transports objects to be processed to a plurality of processing mechanisms for processing, including a transport mechanism that includes a transport section that transports the objects to be processed to the heat treatment mechanism, and a standby section that temporarily waits for the objects to be processed. A semiconductor manufacturing device characterized by:
JP3563788A 1988-02-17 1988-02-17 Substrate processing apparatus and substrate processing method Expired - Lifetime JP2660285B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3563788A JP2660285B2 (en) 1988-02-17 1988-02-17 Substrate processing apparatus and substrate processing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3563788A JP2660285B2 (en) 1988-02-17 1988-02-17 Substrate processing apparatus and substrate processing method

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP8148571A Division JP2859849B2 (en) 1996-05-20 1996-05-20 Processing device and processing method

Publications (2)

Publication Number Publication Date
JPH01209737A true JPH01209737A (en) 1989-08-23
JP2660285B2 JP2660285B2 (en) 1997-10-08

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Country Status (1)

Country Link
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Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH021907A (en) * 1988-06-09 1990-01-08 Nec Kyushu Ltd In-line type semiconductor heat treatment device
JPH0338636U (en) * 1989-08-25 1991-04-15
JPH0631142U (en) * 1992-09-25 1994-04-22 大日本スクリーン製造株式会社 Substrate cleaning equipment
JPH06338555A (en) * 1992-12-21 1994-12-06 Dainippon Screen Mfg Co Ltd Board processing device
JPH07142355A (en) * 1993-11-19 1995-06-02 Sony Corp Method and apparatus for resist treatment
JPH07161632A (en) * 1993-07-16 1995-06-23 Semiconductor Syst Inc Heat treatment module for substrate coating / developing system
US5639301A (en) * 1994-06-17 1997-06-17 Dainippon Screen Mfg. Co., Ltd. Processing apparatus having parts for thermal and non-thermal treatment of substrates
US5826129A (en) * 1994-06-30 1998-10-20 Tokyo Electron Limited Substrate processing system
US6168667B1 (en) 1997-05-30 2001-01-02 Tokyo Electron Limited Resist-processing apparatus
JP2014120520A (en) * 2012-12-13 2014-06-30 Tokyo Electron Ltd Substrate processing device, substrate processing method and storage medium

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Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH021907A (en) * 1988-06-09 1990-01-08 Nec Kyushu Ltd In-line type semiconductor heat treatment device
JPH0338636U (en) * 1989-08-25 1991-04-15
JPH0631142U (en) * 1992-09-25 1994-04-22 大日本スクリーン製造株式会社 Substrate cleaning equipment
JPH06338555A (en) * 1992-12-21 1994-12-06 Dainippon Screen Mfg Co Ltd Board processing device
JP3042576B2 (en) * 1992-12-21 2000-05-15 大日本スクリーン製造株式会社 Substrate processing equipment
JPH07161632A (en) * 1993-07-16 1995-06-23 Semiconductor Syst Inc Heat treatment module for substrate coating / developing system
JPH07142355A (en) * 1993-11-19 1995-06-02 Sony Corp Method and apparatus for resist treatment
US5639301A (en) * 1994-06-17 1997-06-17 Dainippon Screen Mfg. Co., Ltd. Processing apparatus having parts for thermal and non-thermal treatment of substrates
US5826129A (en) * 1994-06-30 1998-10-20 Tokyo Electron Limited Substrate processing system
US6168667B1 (en) 1997-05-30 2001-01-02 Tokyo Electron Limited Resist-processing apparatus
JP2014120520A (en) * 2012-12-13 2014-06-30 Tokyo Electron Ltd Substrate processing device, substrate processing method and storage medium

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