JPH01206742A - Control path allocating system between multiplexing devices - Google Patents

Control path allocating system between multiplexing devices

Info

Publication number
JPH01206742A
JPH01206742A JP3088888A JP3088888A JPH01206742A JP H01206742 A JPH01206742 A JP H01206742A JP 3088888 A JP3088888 A JP 3088888A JP 3088888 A JP3088888 A JP 3088888A JP H01206742 A JPH01206742 A JP H01206742A
Authority
JP
Japan
Prior art keywords
control path
multiplexing
time slot
multiplexer
communication
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3088888A
Other languages
Japanese (ja)
Inventor
Kiyotaka Nishi
清隆 西
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP3088888A priority Critical patent/JPH01206742A/en
Publication of JPH01206742A publication Critical patent/JPH01206742A/en
Pending legal-status Critical Current

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  • Time-Division Multiplex Systems (AREA)

Abstract

PURPOSE:To use a remaining time slot for communication by allocating the time slot only to a high speed line, for which it is necessary to extend a control path, out of the plural high speed lines to be composed of plural multiplexing devices. CONSTITUTION:Multiplexing devices 1-4 are connected with transmission lines 6-9 as shown in the figure and high speed line terminals 101, 102-401 and 402 are provided in the multiplexing devices 1-4. A supervising device 5, which is in the same place as the multiplexing device 2, allocates the suitable time slot to the necessary multiplexing device intervals 2-1-3 and 2-4 by control paths 10, 11 and 12. Since it is not necessary to allocate the control path to the multiplexing device 3-4 interval, the time slot is used for communication. Thus, communication efficiency is improved and a service is improved.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は多重化装置間の制御パス割付方式に関し、特に
、多重化装置の高速回線が複数ある場合の制御パス割付
方式に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a control path allocation method between multiplexing devices, and particularly to a control path allocation method when a multiplexing device has a plurality of high-speed lines.

〔従来の技術〕[Conventional technology]

従来、この種の制御パス割付方式は、多重化装置の高速
回線が複数本実在した場合に、制御パスが必要な回線か
どうかという判定はせずにすべての回線に制御パスを割
り付けていた。
Conventionally, in this type of control path allocation method, when a multiplexer has multiple high-speed lines, a control path is allocated to all the lines without determining whether a control path is necessary.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来の制御パス割付方式は、前記のように高速回線が複
数ある多重化装置において、必要めない制御パスもタイ
ムスロットとして割り付は占有するので、伝送効率が低
下するという問題点がある。
The conventional control path allocation method has a problem in that, in a multiplexing device having a plurality of high-speed lines as described above, unnecessary control paths are also allocated as time slots, resulting in a reduction in transmission efficiency.

本発明は従来のもののこのような問題点を解決しようと
するもので、伝送効率が低下しない多重化装置間の制御
パス割付方式を提供するものである。
The present invention is an attempt to solve these problems of the conventional method, and provides a method for allocating control paths between multiplexing devices without reducing transmission efficiency.

〔課題を解決するだめの手段〕[Failure to solve the problem]

の高速回線の内制御パスを構成する必要のある高速回線
にはタイムスロットを割り付け、制御パスを構成する必
要のない高速回線にはタイムスロットを割り付けないこ
とを特徴とする特許パス割付方式が得られる。
The patented path allocation method is characterized in that time slots are allocated to high-speed lines that need to constitute a control path, and no time slots are allocated to high-speed lines that do not need to constitute a control path. It will be done.

〔実施例〕〔Example〕

次に9本発明について図面を参照して説明する。 Next, nine aspects of the present invention will be described with reference to the drawings.

第1図は本発明の一実施例の構成図を示す。FIG. 1 shows a configuration diagram of an embodiment of the present invention.

この図において、多重化装置1と多重化装置2は伝送路
6.多重化装置1と多重化装置3は伝送路7.多重化装
置3と多重化装置4は伝送路9、多重化装置2と多重化
装置4は伝送路8でそれぞれ接続されてネットワークが
構成されている。監視装置5は多重化装置2の設定場所
と同一場所に在り、多重化装置1への制御パス10゜多
重化装置3への制御パス11.多重化装置4への制御パ
ス12により監視パスを張っている。この場合、多重化
装置3と多重化装置4間の制御パスは張る必要がないの
で設けていない。
In this figure, multiplexer 1 and multiplexer 2 are connected to transmission line 6. The multiplexer 1 and the multiplexer 3 are connected to a transmission line 7. The multiplexing device 3 and the multiplexing device 4 are connected through a transmission path 9, and the multiplexing device 2 and the multiplexing device 4 are connected through a transmission path 8 to form a network. The monitoring device 5 is located at the same location where the multiplexer 2 is set up and has a control path 10° to the multiplexer 1 and a control path 11 to the multiplexer 3. A control path 12 to the multiplexing device 4 provides a monitoring path. In this case, a control path between the multiplexing device 3 and the multiplexing device 4 is not provided because it is not necessary to extend the control path.

各々の制御パスとしては通信速度2.4 kb/ sの
タイムスロットを各多重化装置ごとに割り付ける必要が
あり、多重化装置1は高速回線101と高速回線102
のそれぞれに制御パスとして通信速度2.4.kb/s
のタイムスロットを割りイ」け、多重化装置2は高速回
線201と高速回線202.多重化装置3は高速回線3
01.多重化装置4(l′i:高速回線401へそれぞ
れ制御パスとして通信速度2、4. kb/ sのタイ
ムスロットを割り付ける。
As each control path, it is necessary to allocate a time slot with a communication speed of 2.4 kb/s to each multiplexer, and the multiplexer 1 has a high-speed line 101 and a high-speed line 102.
Communication speed 2.4. kb/s
The multiplexer 2 allocates time slots for the high-speed line 201 and the high-speed line 202 . Multiplexer 3 is high-speed line 3
01. Multiplexer 4 (l'i: time slots with communication speeds of 2 and 4. kb/s are allocated as control paths to high-speed line 401, respectively.

ここで、多重化装置3の高速回線302と多重化装置4
の高速回線402には制御パスを必要とシナイので2通
信速度2.4.kb/sのタイムスロットを割り伺けな
い。従って、この間は、制御パス用としての通信速度2
.4kb/sのタイムスロットを通信用として使用する
ことができる。
Here, the high-speed line 302 of the multiplexer 3 and the multiplexer 4
Since the high-speed line 402 requires a control path, the communication speed is 2.4. I can't get a kb/s time slot. Therefore, during this period, the communication speed for the control path is 2.
.. A 4 kb/s time slot can be used for communication.

〔発明の効果〕〔Effect of the invention〕

以上説明したように2本発明は、一つの多重化装置の複
数の高速回線の内、制御パスを張る必要のない高速回線
には、制御パスのタイムスロットを割り付けないことに
より、そのタイムスロットを通信用として使用すること
ができるから2通常の通信データに対する伝送効率を高
め、ザービスの向上が得られる。
As explained above, in the present invention, among the plurality of high-speed lines of one multiplexing device, a time slot for a control path is not allocated to a high-speed line that does not require a control path. Since it can be used for communication, the transmission efficiency for normal communication data can be increased, and service can be improved.

以下余白Margin below

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の実施例の構成図である。図において、
  1,2,3.4は多重化装置、5は監視装置、6,
7,8.9は伝送路、 10.]、1,1.2は制御パ
ス、  1.01.、102.201.、202.30
1.、302.4.01.402は高速回線である。
FIG. 1 is a block diagram of an embodiment of the present invention. In the figure,
1, 2, 3.4 are multiplexing devices, 5 is a monitoring device, 6,
7, 8.9 are transmission lines, 10. ], 1, 1.2 is the control path, 1.01. , 102.201. , 202.30
1. , 302.4.01.402 is a high-speed line.

Claims (1)

【特許請求の範囲】[Claims] 1、複数の多重化装置で構成されるネットワークにおい
て、各多重化装置の複数の高速回線の内制御パスを構成
する必要のある高速回線にはタイムスロットを割り付け
、制御パスを構成する必要のない高速回線にはタイムス
ロットを割り付けないことを特徴とする制御パス割付方
式。
1. In a network composed of multiple multiplexers, time slots are assigned to the high-speed lines that need to configure a control path among the multiple high-speed lines of each multiplexer, so that there is no need to configure a control path. A control path allocation method characterized by not allocating time slots to high-speed lines.
JP3088888A 1988-02-15 1988-02-15 Control path allocating system between multiplexing devices Pending JPH01206742A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3088888A JPH01206742A (en) 1988-02-15 1988-02-15 Control path allocating system between multiplexing devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3088888A JPH01206742A (en) 1988-02-15 1988-02-15 Control path allocating system between multiplexing devices

Publications (1)

Publication Number Publication Date
JPH01206742A true JPH01206742A (en) 1989-08-18

Family

ID=12316266

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3088888A Pending JPH01206742A (en) 1988-02-15 1988-02-15 Control path allocating system between multiplexing devices

Country Status (1)

Country Link
JP (1) JPH01206742A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5834665A (en) * 1981-08-25 1983-03-01 Nec Corp Communication control system of loop transmission system
JPS58190142A (en) * 1982-04-30 1983-11-07 Hitachi Ltd Pulse code modulating terminal equipment

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5834665A (en) * 1981-08-25 1983-03-01 Nec Corp Communication control system of loop transmission system
JPS58190142A (en) * 1982-04-30 1983-11-07 Hitachi Ltd Pulse code modulating terminal equipment

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