JPH0120542B2 - - Google Patents

Description

[Detailed Description of the Invention] This invention relates to a read-only memory device, that is, a ROM (Read Only Memory) among semiconductor memory devices.
This relates to a structure (hereinafter simply referred to as a write method) for determining whether the stored content in is "1" or "0".

In typical ROMs up until now, when a potential is applied to the X and Y decoders, a potential is simultaneously applied to both the gate and drain terminals of a selected memory cell, and the contents of that memory cell are read out. A configuration in which the contents of "1" and "0" are determined in advance by whether or not the wiring from the decoder is connected to the drain of the insulated gate field effect transistor that constitutes the memory cell has been put into practical use. has been done. Therefore, the conventional ROM writing method is to create a perforation in a thick interlayer insulating film provided on the drain of a transistor and then wire the wiring. After that, a perforation pattern with the contents of the ROM according to the purpose was formed, and then a common aluminum wiring was formed to obtain a ROM storing the desired contents. This traditional writing method has different contents in a short process.
It had the advantage of being able to manufacture ROMs.

However, these memory cells are silicon gate
Conventional ROMs made of MOS field effect transistors, etc. had limitations in achieving finer patterns and higher element density. For example, if the distance between the drain hole and the gate polycrystalline silicon part used for the gate wiring becomes smaller than a certain distance, the electrode connected to the drain hole and the polycrystalline silicon part to be used as the gate electrode will come into contact with or come close to each other. This caused leakage current to occur and the formation of a steep step between the top of the polycrystalline silicon and the bottom of the perforation, which caused disconnection of the aluminum wiring, resulting in a reduction in manufacturing yield. Therefore, the gap between the gate polycrystalline silicon and the drain hole is designed to be at least about 2 μm, which poses a problem in increasing the density of the device.

In this invention, the memory cell has an insulated gate field effect transistor configuration, and the drain wiring is formed in the same layer as the gate wiring using the same material, so that it is possible to distinguish whether the memory content is "1" or "0". This is done by determining whether the drain diffusion layer is in direct contact with the drain wiring or whether an insulating film equivalent to a gate insulating film is interposed between the drain diffusion layer and the drain wiring. This is a read-only semiconductor memory device characterized by:

Here, the drain diffusion layer does not necessarily have to be limited to a region doped with impurities by a diffusion method. Naturally, it is also possible to use ion implantation technology or epitaxial growth technology. This is an attempt to clearly distinguish the term from drain wiring.

Fig. 1 shows a conventional structure, and Fig. 2 shows a schematic cross-sectional view of a structure according to the present invention, including a slight peripheral portion adjacent to a memory cell of a ROM made of a polycrystalline silicon gate field effect transistor. Shown in comparison. In FIG. 1, although the size of the drain hole 112 can be reduced as the pattern becomes finer, it is generally
7. Because the thickness of the interlayer insulating film near the upper edge (indicated by C in the figure) tends to be thinner than that on a smooth surface, the distance between the drain hole and the gate polycrystalline silicon is set to a certain distance. If they are brought closer than this, leakage current may occur or the dielectric strength between the layers may decrease. Furthermore, when the aluminum wiring 113 is formed on the interlayer insulating film 111, the distance between the bottom part 112 of the drain hole and the upper part C of the interlayer insulating film on the polycrystalline silicon sometimes forms a steep difference of 1.5 μm or more. Therefore, it can be easily inferred that the wire breakage is likely to occur in the D section of the figure. Further, in the same figure, the regions indicated as A and B indicate transistors in the "1" state as A, and transistors in the "0" state as B.

For these reasons, the drain hole must be designed to be at least 3 μm away from the gate region, and the writing method with the conventional structure was unsuitable for high density.

Next, the ROM writing method of the present invention will be explained using FIG. First, to write "1", remove the oxide film formed during gate oxidation on the silicon substrate in the drain region, and directly form a polycrystalline silicon layer 8 on top of it, so that it is in direct contact with the silicon substrate.
The writing of "0" is carried out as in 6B, leaving the above-mentioned oxide film on the drain intact and providing the same polycrystalline silicon layer 8. For example, in FIG. 2, the "1" state corresponds to the memory cell indicated by A, and the "0" state corresponds to the memory cell indicated by B.

Using this invention, the drain hole connected to the aluminum wiring 13 via the interlayer insulating film 11 is formed on the polycrystalline silicon 8 having approximately the same height as the gate polycrystalline silicon 7. Therefore, it is possible to eliminate leakage regions between the gate electrode and the drain wiring, regardless of the processing shape of the perforation. For the same reason, if the contacts in the peripheral circuits of the ROM are formed on polycrystalline silicon, the depth of all contact holes will be approximately the same as the thickness of the interlayer insulating film, making etching and other processing extremely easy. Even with miniaturization and higher density, the manufacturing process does not become particularly difficult and high yields can be ensured.

Furthermore, since the polycrystalline silicon wiring 8 on the drain can be formed using the same mask as the gate polycrystalline silicon wiring 8, the spacing between the gate and drain polycrystalline silicon wirings can be maintained at the designed dimension without relying on the alignment process, and can be formed using the same mask as the gate polycrystalline silicon wiring 8. There is no particular increase in the number of eye contact.

As described above, writing according to the present invention is determined by the process of removing the oxide film on the drain, so the subsequent manufacturing process is somewhat longer, but with the progress of high precision alignment technology and lithography technology, miniaturization and This far outweighs the advantages of being able to promote higher density of devices and to significantly improve manufacturing yields by reducing wiring steps. In particular, wafer direct exposure technology using electron beams, which has recently been adopted at the research stage as a means of miniaturization and large-scale integration, allows working
Since the mask manufacturing period is excluded, the length of some steps after writing is TAT ( Turn A rovnd T
ime) is not a decisive factor in making it longer.

Next, the writing method of the present invention will be described in detail with reference to examples using figures. FIG. 3 is a schematic cross-sectional view showing the manufacturing process of a polycrystalline silicon gate ROM in carrying out the present invention, and FIG. 2 is a finished view thereof.

A thin thermal oxide film 2 is formed on a silicon substrate 1 having p-type conductivity, and then a silicon nitride film 3 is deposited by the CVD method, and a region to be formed as a channel stopper region is formed by ordinary photolithography. Remove the silicon nitride film. Using the resist as a mask, boron is implanted in a dose sufficient to obtain the threshold voltage value of a predetermined field region by ion implantation to form a channel stopper region 4, and then selective oxidation is performed using the remaining silicon nitride film as a mask. If this is done, a field oxide film 5 having a thickness of about 0.8 μm can be obtained. This state is shown in Figure 3a. Next, the silicon nitride film 3 and the thin underlying silicon oxide film 2 are completely removed using a normal wet method, and a gate oxide film 6 of a predetermined thickness is formed again, and the drain region is formed according to the written content. When a part of the gate oxide film in the area to be formed is removed by photolithography using a writing mask and etching method, the result shown in FIG. 3B is obtained. Here, 6A is “1” with the gate oxide film removed.
The state 6B is for forming a "0" state in the future with the gate oxide film remaining. 5000Å immediately
A certain amount of polycrystalline silicon is deposited using the CVD method, and impurities such as phosphorus are diffused. Then, the polycrystalline silicon of the gate region 7 and the drain wiring 8 are separated using ordinary photolithography and etching techniques. After removing the resist, arsenic was added to ¹⁰ cm by ion implantation.
If the implantation is performed at a dose of about ^-2 , a source region 9 and a drain region 10 are formed, as shown in FIG. 3c. Here, 10A is a deep n-type drain diffusion layer diffused from polycrystalline silicon, and 10B is a drain diffusion layer formed only by ion implantation. Next, interlayer insulating film 1
1. A CVD oxide film or a PSG film is deposited. Contact holes 1 are created at the necessary locations for contact with aluminum using photolithography and etching techniques.
2, we obtain Figure 3d. Immediately, aluminum is deposited by vacuum evaporation and a wiring pattern is formed, resulting in the structure of the present invention shown in FIG. Compared to the conventional method shown in FIG. 1, there are fewer steps in the contact hole, making aluminum wiring easier.

If necessary, cover with a protective film and cut out the window of the bonding pad.

Although the above description did not mention any specific processing means, the effects of the invention are the same whether a normal wet method or a dry processing technique is used.

Above, an example in which the gate wiring and common drain wiring are made of polysilicon has been described in detail, but this is just an example, and other metals may also be used together.
Of course, it may be formed of a single metal such as.

[Brief explanation of drawings]

FIG. 1 is a schematic cross-sectional view showing the storage unit structure of a conventional ROM. Figure 2 shows the structure of the method of the present invention in comparison with the conventional method.
B is a memory unit indicating a "1" state in which the aluminum wiring is in contact with the drain of the address switch transistor, and B is a memory unit in a non-contact "0" state. Further, FIG. 3 is a schematic sectional view showing the manufacturing process of an embodiment according to the manufacturing order for explaining the present invention, and the finished state is shown in FIG. 2.
The numbers and symbols in the figure will be explained next. DESCRIPTION OF SYMBOLS 1... Silicon substrate, 2... Thin thermal oxide film, 3... Silicon nitride film, 4... Channel stopper region, 5
...Field oxide film, 6,106...Gate oxide film, 6A...Drain region that should be in the written "1" state, 6B...Drain region that should be in the unwritten "0" state, 7,107...Gate electrode 8. Polycrystalline silicon to be used as drain wiring, 9. Source region, 1
0...Drain region, 10A...Deep diffusion region, 10
B... Shallow diffusion region, 11, 111... Interlayer insulating film,
12, 112... Contact portion, 13, 113... Aluminum wiring.

Claims (1)

[Claims] 1 The memory cell has an insulated gate field effect transistor configuration, and the drain wiring is formed in the same layer as the gate wiring using the same material, and the drain diffusion layer is used to distinguish whether the memory content is "1" or "0". The method is characterized in that the determination is made by determining whether the drain wiring is in direct contact with the drain wiring or whether an insulating film equivalent to a gate insulating film is interposed between the drain diffusion layer and the drain wiring. A read-only semiconductor storage device.