JPH01202921A - Semiconductor logic circuit - Google Patents

Abstract

PURPOSE:To operate a transmission gate at a higher speed by providing a circuit comprising two MESFETs between an output of a 1st logic circuit and an input of a 2nd logic circuit. CONSTITUTION:A circuit comprising a 1st MESFET 14 and a 2nd MESFET 15 is provided between an output of the 1st logic circuit 11 and an input of the 2nd logic circuit 12. Since the node N12 is connected to a gate of a MESFET 18, the potential reaches a level only higher by nearly 0.6V than the level of the 2nd constant power supply V12. Since the node M1 1 is connected to the gate of the MESFET 14 and the transmission gate 15 only on the other hand, the potential is increased by the Schottky clamp voltage of the gate-source of the MESFET 14 than the node N12. Thus, the potential reaching a higher voltage by nearly 0.6V than the constant power supply V12 only is inputted to the transmission gate 13 while the level is increased to the potential level of nearly twice. Thus, the signal speed transmitted through the transmission gate 13 is much increased.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor logic circuit having a transmission gate 1 in a prefectural bond circuit using field effect transistors.

(Prior Art) Conventionally, in semiconductor logic circuits that use field effect transistors as transmission gates, the output of a first logic circuit is connected to the drain (or gate) of a transmission gate 1- and the input of a second logic circuit. A similar circuit configuration is often used.

As for this kind of technology, there is one shown in FIG. 12. FIG. 2 is a circuit diagram showing an example of the configuration of a conventional semiconductor logic circuit, which is used, for example, in a flip-flop circuit.

This semiconductor logic circuit is composed of a first logic port B1, a second logic circuit 2, and a transmission gate 3. 1st
Logic circuit 1 constitutes an inverter circuit, and is composed of a normally-off Schottky gate field effect transistor (
(hereinafter referred to as MESFET) 4 and a normally-on type MESFET 5 as an impedance element.

M) The gate of the MESFET 4 is connected to the first input terminal 11, and the train is connected to the gate I and the drain of the MESFET 5 to form a node N1.

Like the first logic circuit 1, the second logic circuit 2 is a normally-off type MES1? F, T6 and normally-on M1ΣSFE as an impedance element
'l'7, and the mutual connection is also to the first logic circuit 1.
It is similar to However, the drain of MESFET6 and M
The gate and source of ESFET7 are both connected to the first output terminal 01, and MFεS F E 'I' 6
The gate of is connected to the output of the first logic circuit 1, that is, the node N1.

The drains of the MESFE'r5゜7 of the first and second logic circuits 1 and 2 are both connected to the first constant potential power supply ■1,
The sources of ESFET'4.6 are both connected to the second constant potential power supply V.
Connected to 2.

The transmission gate 3 consists of a MESFE 'T', its drain is connected to the node N1, and its gate and source are connected to the second input terminal 2 and the second output terminal 02, respectively.

The operation of the semiconductor logic circuit configured as described above will be explained with reference to FIG. FIG. 3 is a time chart of the semiconductor logic circuit of FIG. 2, in which the horizontal axis represents time T, and the vertical axis represents the first input terminal 1, the node N1, and the first output terminal 01.
, the signal level of the second input terminal I2, and the second output terminal 02.

The signal input to the first input terminal 11 is inverted by the first logic circuit 1, which is an inverter circuit, and the signal is inverted by the first logic circuit 1, which is an inverter circuit.
At the first input terminal 1, a signal whose signal level is opposite to that at the first input terminal 1 appears. Also, the second logic circuit 2 sends a signal to the first output terminal 01 that is opposite to the signal at the node N1.
That is, the same signal as the first input terminal 11 is output.

Further, the signal at the node N1 is outputted to the second output terminal 02 by the transmission gate 3 only when the signal at the second input terminal 2 is at a high level. Here, the second input terminal ■
2 is at a low level, the impedance seen from the second output terminal 02 to the transmission gate 3 becomes high, and the output of the second output terminal 02 is not determined if this circuit remains as it is. However, when the semiconductor logic circuit shown in FIG. 2 is actually used, it is determined by the circuit connected to the second output terminal 02, and is not a problem here.

(Problem to be solved by the invention) However, in the semiconductor logic circuit with the above configuration,
There were the following problems.

While the second input terminal 2 is at a high level, that is, when the signal at the node N1 is output to the second output terminal 02, especially when the high level signal at the node N1 is output to the second output terminal 02, In order to increase the transmission speed, it is desirable that the high level signal at node N1 be at a higher voltage.

However, in the semiconductor logic circuit of FIG. 2 constructed using MESFETs, the potential of the node N1 does not become higher than the second constant potential power supply (2) by, for example, about 0.6 ■ or more. This is because the node N1 is the MESFE of the second logic circuit 2.
Since it is connected to the gate of T6, MESFE'l'
This is because the Schottky diode between the gate and source of No. 6 clamps the voltage at a position higher than the second constant potential power supply No. 2 by the Schottky diode's clamp voltage. This clamp voltage is applied to gallium arsenide (GaAs)
In the case of MESFET, it is about 0.6■.

In this way, the voltage of the high level signal at node N1 is
Since the voltage does not become higher than the clamp voltage of the Schottky diode of the S'FET 6, there was a problem in that the signal of the note N1 could not be transmitted through the transmission gate 3 at high speed.

The present invention provides a semiconductor logic circuit that solves the problem of the prior art, which is the need for speeding up signal propagation through a transmission gate.

(Means for Solving the Problems) In order to solve the above problems, the present invention provides a Schottky game.
1, a field effect transistor and an impedance element connected to the drain of the transistor, and a first transistor having the gate and the train of the transistor as input and output, respectively. a second logic circuit having the same configuration as the first logic circuit and whose input is connected to the output of the first logic circuit;
a first connected to the impedance element of the logic circuit of
a constant potential power source, and a second constant voltage source connected to the sources of the transistors 1 to 1 in the first and second logic circuits.
a transmission gate comprising a Schottky gate field effect transistor connected to the output of the first logic circuit; A circuit consisting of a first Schottky gate field effect transistor and a second Schottky gate I field effect transistor is provided between the input of the logic circuit, and the gate, train and source of the first transistor are respectively connected to the first Schottky gate field effect transistor. The output of the logic circuit 01f is connected to the input of the first constant potential power supply and the second logic circuit, and the drain and source are connected to the gate 1 of the second transistor, respectively. , the human power of the second logic circuit, and the second constant potential power supply.

(Function) According to the present invention, since the semiconductor logic circuit is configured as described above, the first and second MESFETs are provided between the output of the first logic circuit and the input of the second logic circuit. The circuit outputs a signal at the same logic level as the conventional one, and increases the high-level potential of the signal input to the transfer gates 1 to 1 by the Schottky clamp voltage between the gate and source of the first MESFET. do. This function speeds up the operation of the transmission game I. Therefore, the above problem can be solved.

(Embodiment) FIG. 1 is a circuit diagram showing an embodiment of a semiconductor logic circuit of the present invention.

This semiconductor logic circuit includes a first logic circuit 11, a second logic circuit 12, a transmission gate 13, and a first and second MESFET provided between the first and second logic circuits.
14 and 15.

The first logic circuit 11 is a normally-off type MESFET.
16 and a normally-on MESFET 17 as an impedance element, and these constitute an inverter circuit. The train of MESI"ET16 is connected to the gate and source of MESFET17,
First logical port rl! i! Node NI as output of Ill
One L is missing.

The gate of MEsFET16 is connected to the first input terminal Ill and forms the input of the first logic port B11.

The second logic circuit 12 constitutes an inverter circuit having the same configuration as the first logic circuit 11, and ME S F F, '1'.
18's drain and ME S f;'ET19's game I
~, the source is connected to the first output terminal 011. 1st. Each MES of the second logic circuit 11.12
The trains of FETs 17 and 19 are both connected to the first constant potential power supply Vll, and the sources of the MESFEs 16°18 of the first and second logic circuits 11.12 are both connected to the second constant potential power supply V12. There is.

A first MESFET 14 and a second MESFET are connected between the output of the first logic circuit 11 and the input of the second logic circuit 12.
A circuit consisting of FET 15 is provided. 1st ME
The source of SFET 14 and the drain of the second MESFE'l'' are connected together iL.

It is connected to the input of the second logic circuit 12, that is, to the gate 1- of the MESFE'1'18 via the node N12.

The gate and drain of the first MESFET 14 are connected to the node Nil and the first constant potential power supply Vll, respectively, and the gate and source of the second MESFET 15 are connected to the first input terminal Ill and the second constant potential power supply V1, respectively.
Connected to 2.

The transmission gate 13 consists of a MESFET whose gate is connected to the second input terminal 112 and whose source is connected to the second output terminal 012.

Further, the drain is connected to the output of the first logic circuit B11, that is, the node Nil.

The semiconductor logic circuit configured as described above connects the output of the first logic circuit 11 to the first . Second MESFET14,1
．． The signal is inputted to the second logic circuit 12 via the circuit composed of 5, and its operation is performed as follows.

Node N11 and node N12 operate at the same logic level as node N1 of FIGS. 2 and 3.

Here, the first. In the circuit configured with the second MESFET14.15, the gate l of the second MESFET'r15 is
~ is connected to the first logic circuit 1 by the first input terminal Ill.
Since the same input as 1 is given and the output of the first logic circuit 11, which is an inverter, is connected to the gate of the first MESFET 14, a signal of the same logic level as the node Nil is output to the node N12. .

At the potential level in this case, especially at a high level,
Since the node N12 is connected to the gate of the MESFET 18, its potential is 0.0.
It only increases by about 6V. On the other hand, node Ni
Since l is only connected to the gate of M13SFET 14 and transmission gate 15, its potential is equal to node N 1
．． 2%, the Schottky clamp voltage between the gate I and source of the IESFET 14 can be increased.

In this way, in this embodiment, it is possible to increase the high-level potential of the signals input to the transmission gates I to 13.

That is, it becomes possible to increase the potential, which was conventionally only about 0.6 V higher than the second constant potential power supply V12, to a potential level about twice that level and input it to the transmission gate 13. Thereby, the speed of the signal transmitted through the transmission gate 13 can be made higher.

Note that the present invention is not limited to the illustrated embodiment, and various modifications are possible. For example, the output of the first logic circuit 11 is connected to the drain of the transfer gate I.13, but instead of this, the output of the first logic circuit 11 and the drain of the transfer gate I.
It is also possible to connect gate No. 3. Further, although the MESFE'l' 17 and 19 are used as impedance elements, modifications such as using resistances instead of these are also possible.

(Effects of the Invention) As described in detail above, according to the present invention, a circuit consisting of the first and second MESFFs and T is connected between the output of the first logic circuit and the input of the second logic circuit. , it is possible to increase the high-level potential of the signal input to the transmission gate, and the transmission gate can be operated at higher speed.

Therefore, the present invention can be applied to a wide variety of circuits such as sequential circuits and flip-flop circuits in logic circuits, and high-speed semiconductor logic circuits can be constructed.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the semiconductor logic circuit of the present invention, FIG. 2 is a circuit diagram of a conventional semiconductor logic circuit in II, and FIG. This is a time chart. 11...First logic circuit, 12...Second logic circuit, 13...Transmission gate, 14...
...First ME S F E '1', 15...
...Second MESFE'l', 16-19...
- MESFET, Vll...first constant potential power supply, V12...second constant potential power supply.

Claims (1)

[Scope of Claims] A first logic circuit comprising a Schottky gate field effect transistor and an impedance element connected to the drain of the transistor, the gate and drain of the transistor serving as input and output, respectively; a second logic circuit having a similar configuration to the logic circuit and having an input connected to the output of the first logic circuit; and a second logic circuit having an input connected to the impedance element of the first and second logic circuits. a second constant potential power source connected to the sources of the transistors in the first and second logic circuits; and a Schottky gate field effect connected to the output of the first logic circuit. a transmission gate consisting of a transistor, a first Schottky gate field effect transistor and a second Schottky gate field effect transistor between the output of the first logic circuit and the input of the second logic circuit; A circuit consisting of a Schottky gate field effect transistor is provided, and the gate, drain, and source of the first transistor are connected to the output of the first logic circuit, the first constant potential power supply, and the second logic circuit, respectively. and the gate, drain, and source of the second transistor are connected to the input of the first logic circuit, the input of the second logic circuit, and the second constant potential power supply, respectively. Features of semiconductor logic circuits.