JPH01202041A - Data receiving circuit - Google Patents

Abstract

PURPOSE:To allow a synchronism detecting circuit to be requested with high processing speed by providing the title circuit with a 3rd selecting circuit for outputting a synchronizing signal from a 2nd synchronism detecting circuit when a synchronizing step-out signal is outputted from a 1st synchronism detecting circuit and outputting a synchronizing signal from the 1st synchronism detecting circuit when the synchronizing step-out signal is not outputted from a 1st synchronism detecting signal. CONSTITUTION:When the synchronizing step-out signal is not inputted from a synchronism detecting circuit 105, a selecting circuit 103 outputs data obtained from an output terminal (c) to a terminal (g). At the time of inputting the synchronizing step-out signal, the selecting circuit 103 selects data obtained from an output terminal (b) and outputs the data to the terminal (g). Since the synchronizing signal is outputted to an output terminal (e) when the synchronizing step-out signal is not inputted from the circuit 105, a selecting circuit 104 selects the signal and outputs the selected signal to an output terminal (h). Since the synchronizing signal is outputted from a synchronism detecting circuit 106 at the time of inputting the synchronizing step-out signal, the selecting circuit 104 selects the signal and outputs the selected signal to the output terminal (h). Consequently, the synchronism detecting circuits are driven at a half of ordinary processing speed to detect synchronism.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a circuit for receiving high-speed data, and more particularly to a data receiving circuit equipped with a frame synchronization signal detection circuit.

[Conventional technology]

In a circuit that receives data sent through a transmission path, as the data transmission speed increases, it becomes necessary to process the data at high speed, so the elements used in the circuit must also be capable of high-speed processing. .but,
Since high-speed data processing is performed without using such special elements, data can be processed in parallel.

That is, on the transmitting side, transmission data is divided into, for example, two parts and processed in parallel, and then the data is multiplexed and sent to the transmission path. Then, on the receiving side, the multiplexed data is separated and parallel processing is performed in the same way as on the transmitting side. As a result, the circuit portion that performs parallel processing can perform processing at half the data transmission speed of the transmission line.

The second example of transmission data when performing such parallel processing is
As shown in the figure. On the sending side, the data to be sent is A, and 82 data (Al, A2...., B1°B2....)
As shown in FIG. 2(a), each bit is transmitted alternately in a time-division manner. Then, on the receiving side, Fig. 2(b), (
C) As shown in A, the data is separated into 82 pieces. At this stage, the data rate is reduced by half, making data processing easier.

FIG. 3 shows a conventional data receiving circuit that performs such data separation and synchronization signal detection. Synchronization detection circuit 20
detects the frame synchronization signal of the transmission path frame from the signal inputted to the terminal i from the transmission path, outputs the detected synchronization signal from the terminal i, and supplies it to the separation circuit 10. The separation circuit 10 distinguishes and separates whether the multiplexed data input from the terminal i is A data or B data based on the synchronization signal given from the synchronization detection circuit 20, and the A data is sent to the terminal. From j, B data is output from terminal k.

[Problem to be solved by the invention]

A conventional data receiving circuit can detect a synchronization signal and separate multiplexed data from a transmission path with a simple circuit configuration as described above.

However, since the input data is processed at the same speed,
High processing speed is required for the synchronization detection circuit.

An object of the present invention is to eliminate such drawbacks and provide a data receiving circuit that can be constructed using a synchronization detection circuit that operates at half the processing speed of the conventional one.

(Means for Solving the Problems) The present invention provides a data receiving circuit that receives two types of data multiplexed in a time-division manner, in which the two types of data are separated into first and second data. A separation circuit that outputs from the first and second output terminals, and detects and outputs a synchronization signal of the first data included in the signal from the first output terminal of this separation circuit, and when this synchronization signal cannot be detected. a first synchronization detection circuit that outputs an out-of-synchronization signal; a second synchronization detection circuit that detects and outputs a synchronization signal of the first data included in the signal from the second output terminal of the separation circuit; When the first synchronization detection circuit outputs an out-of-sync signal, the data from the second output terminal of the separation circuit is output, and when the first synchronization detection circuit does not output an out-of-sync signal, the first output terminal of the separation circuit When the first selection circuit outputs the data from the output terminal of the separation circuit and the first synchronization detection circuit outputs the out-of-synchronization signal, the first selection circuit outputs the data from the first output terminal of the separation circuit, and the first synchronization detection circuit outputs the data from the first output terminal of the separation circuit. a second selection circuit that outputs data from the second output terminal of the separation circuit when the detection circuit does not output an out-of-sync signal; and a third selection circuit that outputs the synchronization signal from the synchronization detection circuit and outputs the synchronization signal from the first synchronization detection circuit when the first synchronization detection circuit does not output an out-of-synchronization signal. Features.

〔Example〕 Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a data receiving circuit according to the present invention. This circuit includes a separation circuit 101, a synchronization detection circuit 105
．． 106 and selection circuits 102 to 104.

The input of the separation circuit 101 is connected to the terminal a connected to the transmission line, and the output terminal of the separation circuit 101 is connected to the input of the synchronization detection circuit 105 and the - side of the selection circuits 102 and 103. One output terminal C is connected to the synchronization detection circuit 1
06 and the other input of the selection circuits 102 and 103.

The output terminal d of the synchronization detection circuit 105 is connected to the selection circuits 102 to 1.
04, and the output terminal e is connected to the control input of the selection circuit 10.
Connected to one input of 4. Further, the output of the synchronization detection circuit 106 is connected to the other input of the selection circuit 104.

The outputs of the selection circuits 102 to 104 are respectively connected to terminals f.

Connected to g and h.

Next, the operation will be explained. From terminal a, 82 pieces of data A as shown in FIG. 2(a) are input as serial data arranged alternately for each time loft. Of these data, a frame synchronization signal is assigned and inserted only to data A.

This data receiving circuit receives data A from the above-mentioned input data from the transmission line in the following manner.

B and synchronization signals are separated and connected to terminals f and g, respectively.

Output from h.

The separation circuit 101 switches the signal input from the terminal a every time slot, and outputs data A and B from the output terminals A and C, respectively.

At this time, the synchronization detection circuit 105 receives and receives the signal from the output terminal of the separation circuit 101, and detects the synchronization signal assigned to the data A included in this signal. The detected synchronization signal is output from the output terminal e, and when the synchronization signal cannot be detected, an out-of-synchronization signal is output from the output terminal d. On the other hand, the synchronization detection circuit 106 is connected to the separation circuit 101.
The synchronization signal assigned to data A is detected.

Then, when the selection circuit 102 does not receive the synchronization loss signal from the synchronization detection circuit 105, the selection circuit 102 selects the separation circuit 10.
Since data A is output to output terminal 1, data from output terminal 1 is selected and output to terminal f. On the other hand, when the out-of-synchronization signal is input, it means that data A has been output to output terminal C, so data from output terminal C is selected and output to terminal f.

Furthermore, when the out-of-sync signal is not input from the synchronization detection circuit 105, the selection circuit 103 selects the data from the output terminal C and outputs the data B to the output terminal C. Output to g. On the other hand, when the out-of-synchronization signal is input, it means that data B is being output to output terminal G, so data from output terminal G is selected and output to terminal g.

As a result, data A and B are output from terminals f and g, respectively, as shown in FIGS.

On the other hand, when the out-of-sync signal is not input from the synchronization detection circuit 105, the selection circuit 104 outputs a synchronization signal to the output terminal e, so it selects this signal and outputs it to the output terminal. When an out-of-synchronization signal is input, since a synchronization signal is output from the synchronization detection circuit 106, it is selected and outputted to the output terminal.

〔Effect of the invention〕

As explained above, the present invention provides time-division multiplexed two
The data receiving circuit that receives two types of data includes a separation circuit that separates the two types of data into first and second data and outputs them from the first and second output terminals; A first synchronization detection circuit that detects and outputs a synchronization signal of the first data included in the signal from the output terminal, and outputs an out-of-synchronization signal when this synchronization signal cannot be detected, and a second synchronization detection circuit of the separation circuit. A second device that detects and outputs the first data synchronization signal included in the signal from the output terminal of the device.
When the synchronization detection circuit and the first synchronization detection circuit output an out-of-sync signal, output the data from the second output terminal of the separation circuit, and when the first synchronization detection circuit does not output an out-of-sync signal. , a first selection circuit that outputs data from the first output terminal of the separation circuit, and a first synchronization detection circuit that outputs the data from the first output terminal of the separation circuit when the first synchronization detection circuit outputs an out-of-synchronization signal. and when the first synchronization detection circuit does not output the out-of-sync signal, the second selection circuit outputs the data from the second output terminal of the separation circuit, and the first synchronization detection circuit outputs the out-of-sync signal. A third selection that outputs the synchronization signal from the second synchronization detection circuit when outputting the synchronization detection circuit, and outputs the synchronization signal from the first synchronization detection circuit when the first synchronization detection circuit does not output an out-of-synchronization signal. It is equipped with a circuit.

Therefore, in the data receiving circuit of the present invention, the synchronization detection circuit can perform synchronization detection by operating at half the processing speed of the conventional one. As a result, the hardware configuration becomes easy and costs can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of a data receiving circuit according to the present invention, FIG. 2 is a timing chart explaining the operation of the embodiment of FIG. 1 and the conventional circuit, and FIG. 3 is a conventional data receiving circuit. FIG. 101...Separation circuits 102-104...Selection circuits 105, 106...Synchronization detection circuit Agent Patent attorney Yoshiyuki Iwasa Figure 1

Claims (1)

[Claims] (1) In a data receiving circuit that receives two types of data multiplexed in a time division manner, the two types of data are separated into first and second data and output from first and second output terminals. a separation circuit; a first circuit that detects and outputs a synchronization signal of first data included in a signal from a first output terminal of the separation circuit; and outputs an out-of-synchronization signal when the synchronization signal cannot be detected; a synchronization detection circuit; a second synchronization detection circuit that detects and outputs a synchronization signal of the first data included in the signal from the second output terminal of the separation circuit; , the data from the second output terminal of the separation circuit is output, and when the first synchronization detection circuit does not output an out-of-sync signal, the data from the first output terminal of the separation circuit is output. When the first selection circuit and the first synchronization detection circuit output an out-of-sync signal, output the data from the first output terminal of the separation circuit, and when the first synchronization detection circuit does not output an out-of-sync signal. , a second selection circuit that outputs data from a second output terminal of the separation circuit; and a second selection circuit that outputs a synchronization signal from the second synchronization detection circuit when the first synchronization detection circuit outputs an out-of-synchronization signal. , and a third selection circuit that outputs a synchronization signal from the first synchronization detection circuit when the first synchronization detection circuit does not output an out-of-synchronization signal.