JPH01201972A - Luminescent element driving circuit - Google Patents
Luminescent element driving circuitInfo
- Publication number
- JPH01201972A JPH01201972A JP63026063A JP2606388A JPH01201972A JP H01201972 A JPH01201972 A JP H01201972A JP 63026063 A JP63026063 A JP 63026063A JP 2606388 A JP2606388 A JP 2606388A JP H01201972 A JPH01201972 A JP H01201972A
- Authority
- JP
- Japan
- Prior art keywords
- fet
- light emitting
- emitting element
- modulation signal
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims abstract description 20
- 230000005669 field effect Effects 0.000 claims description 2
- 230000003287 optical effect Effects 0.000 description 18
- 230000008878 coupling Effects 0.000 description 8
- 238000010168 coupling process Methods 0.000 description 8
- 238000005859 coupling reaction Methods 0.000 description 8
- QZZYPHBVOQMBAT-JTQLQIEISA-N (2s)-2-amino-3-[4-(2-fluoroethoxy)phenyl]propanoic acid Chemical compound OC(=O)[C@@H](N)CC1=CC=C(OCCF)C=C1 QZZYPHBVOQMBAT-JTQLQIEISA-N 0.000 description 7
- 238000010586 diagram Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 7
- 238000004904 shortening Methods 0.000 description 5
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
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Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、ディジタル光通信における発光素子駆動回
路、特に光出力波形の立上がり、立下がり時間の短縮化
を行うことのできる発光素子駆動回路に関するものであ
る。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a light emitting element driving circuit in digital optical communication, and particularly to a light emitting element driving circuit that can shorten the rise and fall times of an optical output waveform. It is something.
（従来の技術）
第４図は、例えば昭和６２年電子情報通信学会創立７０
周年記念総合全国大会２３９７．’１２５Ｍ ｂ／ｓ伝
送用光送受信器Ｊ、１０−２７５頁に示されている従来
の発光素子駆動回路を示すもので、図中、（１）はノア
ゲート、（２）は第１のトランジスタ、（３）は第２の
トランジスタ、（４）は第３のトランジスタ、（５）は
第４のトランジスタ、（６）は第１の定電流源、（７）
は第２の定電流源、（８）は結合コンデンサ、（９）は
抵抗、（１０）は発光素子、（１１）は負電源である。(Prior art) Figure 4 shows, for example, the 70th anniversary of the founding of the Institute of Electronics, Information and Communication Engineers in 1988.
Anniversary Comprehensive National Convention 2397. '125M b/s Transmission Optical Transmitter/Receiver J, page 10-275 shows a conventional light emitting element drive circuit, in which (1) is a NOR gate, (2) is a first transistor, (3) is the second transistor, (4) is the third transistor, (5) is the fourth transistor, (6) is the first constant current source, (7)
is a second constant current source, (8) is a coupling capacitor, (9) is a resistor, (10) is a light emitting element, and (11) is a negative power supply.
第５図は、第４図に示された発光素子駆動回路の各部波
形図てあり、図中、（１２）は第１のトランジスタ（２
）のコレクタ電流波形、（１３）は総合コンデンサ（８
）を流れる電流波形、（１４）は発光素子（１０）の駆
動電流波形である。FIG. 5 is a waveform diagram of each part of the light emitting device drive circuit shown in FIG.
), (13) is the collector current waveform of the overall capacitor (8
), and (14) is the drive current waveform of the light emitting element (10).
従来の発光素子駆動回路は上記のように構成され、変調
信号はノアゲート（１）に人力され、正相・逆相の変調
信号に変換された後、第１のトランジスタ（２）、第３
のトランジスタ（４）およひ第２のトランジスタ（３）
、Ｍ４のトランジスタ（５）のベースに入力される。第
１のトランジスタ（２）、第２のトランジスタ（３）お
よび第１の定電流源（６）は電流切換回路を構成し、第
１のトランジスタ（２）のコレクタ電流波形（１２）か
得られる。A conventional light emitting element drive circuit is configured as described above, and a modulation signal is inputted to the NOR gate (1) and converted into a positive phase/reverse phase modulation signal, and then the first transistor (2), the third transistor
transistor (4) and second transistor (3)
, M4 is input to the base of the transistor (5). The first transistor (2), the second transistor (3), and the first constant current source (6) constitute a current switching circuit, and the collector current waveform (12) of the first transistor (2) can be obtained. .
また第３のトランジスタ（４）、第４のトランジスタ（
５）および第２の定電流源（７）は電流切換回路を構成
し、抵抗（９）と結合コンデンサ（８）との微分特性に
より、結合コンデンサ（８）を流れる電流波形（１３）
が得られる。さらに、発光素子（１ｏ）には、第１のト
ランジスタ（２）のコレクタ電流波形（１２）と結合コ
ンデンサ（８）を流れる電流波形（１３）との和とし、
て駆動電流波形（１４）か流れる。結合コンデンサ（８
）を流れる電流波形（１３）は、発光素子（１０）の光
出力の立上がり時に、定常状態より大きな電流を流すこ
とにより、立上がり時間を短縮し、光出力の立上がり時
に発光素子（１０）に電流を供給して発光素子（１０）
の蓄積電荷を吸収し、光出力の立上がり時間を短縮する
効果を有する。発光素子（１０）の光出力の立下がり時
にも、同様の理由により光出力の立下がり時間を短縮す
る効果を有している。In addition, the third transistor (4) and the fourth transistor (
5) and the second constant current source (7) constitute a current switching circuit, and the current waveform (13) flowing through the coupling capacitor (8) is determined by the differential characteristics of the resistor (9) and the coupling capacitor (8).
is obtained. Furthermore, in the light emitting element (1o), the sum of the collector current waveform (12) of the first transistor (2) and the current waveform (13) flowing through the coupling capacitor (8),
The drive current waveform (14) flows. Coupling capacitor (8
) The current waveform (13) flowing through the light emitting element (10) shortens the rise time by flowing a larger current than the steady state when the light output of the light emitting element (10) rises, and the current waveform (13) flows through the light emitting element (10) when the light output rises. Light emitting element (10) by supplying
It has the effect of absorbing the accumulated charge of , and shortening the rise time of optical output. Also when the light output of the light emitting element (10) falls, it has the effect of shortening the fall time of the light output for the same reason.
（発明か解決しようとする課題）
上記のような従来の発光素子駆動回路ては、抵抗（９）
と結合コンデンサ（８）との微分特性により発生する電
（嵐を光出力の立上がり時と立下がり時とにおいて加え
ることにより、光出力波形の立上がり時間、立下がり時
間の短縮化を行なっているが、抵抗（９）と結合コンデ
ンサ（８）との微分特性は、発光素子（１０）のインピ
ータンスが充分小さい場合にしか理想的な動作かできな
い。(Problem to be solved by the invention) In the conventional light emitting element drive circuit as described above, the resistor (9)
The rise time and fall time of the optical output waveform are shortened by adding the electric current (storm) generated by the differential characteristics of the optical output waveform and the coupling capacitor (8) at the rise and fall of the optical output. The differential characteristics of the resistor (9) and the coupling capacitor (8) allow ideal operation only when the impedance of the light emitting element (10) is sufficiently small.
ところが実際の光出力の立上がり時、立下がり時には、
発光素子（ｌＯ）のインピーダンスが大きいため、結合
コンデンサ（８）に流れる電流波形（１３）のピーク値
を充分大きくすることがてきず、光出力の立上がり、立
下がり時間の短縮効果が不充分であるという課題かあっ
た。However, when the actual optical output rises and falls,
Since the impedance of the light emitting element (lO) is large, it is not possible to sufficiently increase the peak value of the current waveform (13) flowing through the coupling capacitor (8), and the effect of shortening the rise and fall times of the optical output is insufficient. There was a certain issue.
この発明は、かかる課題を解決するためになされたもの
で、発光素子のインピータンスが大きい場合でも、光出
力の立上がり、立下がり時間を充分短縮することがてき
る発光素子駆動回路を得ることを目的とする。This invention was made to solve this problem, and aims to provide a light emitting element drive circuit that can sufficiently shorten the rise and fall times of optical output even when the impedance of the light emitting element is large. purpose.
この発明に係る発光素子駆動回路は、ゲートに変調信号
か人力される電界効果トランジスタ（以下ＦＥＴ）と、
このＦＥＴのドレインと発光素子のカソードとの間に接
続された抵抗・コンデンサの並列回路と、第１の端子が
発光素子のカソードと上記並列回路との間に接続される
とともに、第２の端子か上記発生素子のアノード電位以
上の任意の電位を有する電源に接続され、上記変調信号
又はその反転信号が制御信号として入力される３端子ス
イッチとを設けるようにしたものである。The light emitting device drive circuit according to the present invention includes a field effect transistor (hereinafter referred to as FET) whose gate receives a modulation signal manually;
A parallel circuit of a resistor/capacitor is connected between the drain of the FET and the cathode of the light emitting element, a first terminal is connected between the cathode of the light emitting element and the parallel circuit, and a second terminal is connected between the cathode of the light emitting element and the parallel circuit. and a three-terminal switch connected to a power supply having an arbitrary potential higher than the anode potential of the generating element, and into which the modulation signal or its inverted signal is input as a control signal.
（作用）
この発明においては、ＦＥＴのドレインと発光素子のカ
ソードとの間に接続される抵抗・コンデンサの並列回路
により、光出力の立上がり時に発光素子駆動電流にサグ
電流を発生させて光出力波形の立上がり時間を短縮し、
光出力の立下がり時には、制御信号により３端子スイッ
チの第１の端子と第２の端子との間を導通状態とし、発
光素子の蓄積電荷を放電させることにより光出力波形の
立下がり時間を短縮する。(Function) In this invention, a parallel circuit of a resistor and a capacitor connected between the drain of the FET and the cathode of the light emitting element generates a sag current in the light emitting element drive current at the rise of the optical output, thereby shaping the optical output waveform. Shorten the rise time of
When the optical output falls, the control signal brings the first and second terminals of the three-terminal switch into a conductive state and discharges the accumulated charge in the light emitting element, thereby shortening the falling time of the optical output waveform. do.
第１図はこの発明の一実施例を示すもので、図中、第４
図と同一符号は同−又は相当部分を示す。（１５）はＦ
ＥＴ 、（１６）は抵抗、（１７）はこの抵抗（１６）
とともに並列回路を構成するコンデンサ、（１８）は３
端子スイッチ、（１９）はこの３端子スイッチ（１８）
の第１の端子、（２０）は３端子スイッチ（１８）の第
２の端子、（２１）は上記ＦＥＴ （１５）のゲート入
力端子、（２２）は上記３端子スイッチ（１８）の制御
信号入力端子である。FIG. 1 shows an embodiment of the present invention.
The same reference numerals as in the figures indicate the same or corresponding parts. (15) is F
ET, (16) is the resistance, (17) is this resistance (16)
The capacitor that forms a parallel circuit with (18) is 3
Terminal switch, (19) is this 3-terminal switch (18)
(20) is the second terminal of the three-terminal switch (18), (21) is the gate input terminal of the FET (15), and (22) is the control signal of the three-terminal switch (18). This is an input terminal.
第２図は、第１図に示した発光素子駆動回路の各部波形
図であり、図中、（２３）は上記ゲート入力端子（２１
）に入力される変調信号、（２４）は上記ＦＥＴ（１５
）のソース電位、（２５）はＦＥＴ （１５）のドレイ
ン・ソース間抵抗値の波形、（２６）は上記制御信号入
力端子（２２）に制御信号として人力される反転変調信
号、（２７）は発光素子（１０）の駆動電流波形である
。FIG. 2 is a waveform diagram of each part of the light emitting element drive circuit shown in FIG. 1, in which (23) is the gate input terminal (21
), the modulation signal (24) is input to the FET (15
), (25) is the waveform of the drain-source resistance value of FET (15), (26) is the inverted modulation signal input as a control signal to the control signal input terminal (22), and (27) is the waveform of the drain-source resistance value of FET (15). It is a drive current waveform of a light emitting element (10).
上記のように構成された発光素子駆動回路において、変
調信号（２３）は、ＦＥＴ （１５）のゲート入力端子
（２１）に人力され、また反転変調信号（２６）は、制
御信号入力端子（２２）に人力される。変調信号（２３
）の高レベルｖＨと低レベルｖＬおよび負電源（１１）
から供給されるＦＥＴ （１５）のソース電位ｖｓは、
以下に示す関係式を満たす。In the light emitting element drive circuit configured as described above, the modulation signal (23) is input to the gate input terminal (21) of the FET (15), and the inverted modulation signal (26) is input to the control signal input terminal (22). ) is done manually. Modulation signal (23
) high level vH, low level vL and negative power supply (11)
The source potential vs of FET (15) supplied from
The relational expression shown below is satisfied.
ＶＬ＜ ＶＳ Ｖｔｈ
・＝ （１）ｖｌｌ＞ｖ、
・・・（２）但し、Ｖｔｈ：ＦＥＴ（１５）閾値
電圧上記（１）式、（２）式より、ＦＥＴ （１５）は
飽和スイッチング動作を行ない、ＦＥＴ （１５）のド
レイン・ソース間抵抗は変調信号（２３）が高レベルｖ
Ｈのときは数Ω、低レベルＶ、のときは数百Ωとなり、
第２図に示すようなＦＥＴ （Ｉｓ）のドレイン・ソー
ス間抵抗値の波形（２５）か得られる。ＦＥＴ （１５
）は多数キャリアデバイスであり、ドレイン・ソース間
抵抗のスイッチは急峻に行なわれる。VL< VS Vth
・= (1) vll>v,
...(2) However, Vth: FET (15) threshold voltage From the above equations (1) and (2), FET (15) performs saturation switching operation, and the drain-source resistance of FET (15) is The modulation signal (23) is at a high level v
When it is H, it is several ohms, and when it is low level V, it is several hundred ohms.
A waveform (25) of the drain-source resistance value of the FET (Is) as shown in FIG. 2 is obtained. FET (15
) is a majority carrier device, and the drain-source resistance switches rapidly.
３端子スイッチ（１８）は、反転変調信号（２６）か高
レベルのとき第１の端子（１９）と第２の端子（２０）
とが導通、反転変調信号（２６）が低レベルのとき第１
の端子（１９）と第２の端子（２０）とが遮断状態とな
るよう動作する。The three-terminal switch (18) switches between the first terminal (19) and the second terminal (20) when the inverted modulation signal (26) is at a high level.
is conductive, and when the inverted modulation signal (26) is at a low level, the first
The terminal (19) and the second terminal (20) are operated to be in a disconnected state.
変調信号（２３）が高レベルｖＨの期間Ｔ□、Ｔ３（第
２図参照）には、ＦＥＴ （１５）のドレイン・ソース
間抵抗は非常に小さくなり、ＦＥＴ （１５）のドレイ
ンにはソース電位Ｖ８が発生し、３端子スイッチ（１８
）は遮断状態であるので、抵抗（１６）とコンデンサ（
１７）と ゛の並列回路および発光素子（１０）に
のみ電流が流れる。抵抗（１６）とコンデンサ（１７）
との並列回路のインピータンスは、高域通過特性を有す
るので、発光素子（１０）の駆動電流波形（２７）の立
上がり時にはピーキングが発生し、発光素子（１０）の
光出力の立上がり時間を短縮する。During the period T□, T3 (see Figure 2) when the modulation signal (23) is at a high level vH, the drain-source resistance of the FET (15) becomes extremely small, and the drain of the FET (15) has a source potential. V8 is generated and the 3-terminal switch (18
) is in the cut-off state, so the resistor (16) and capacitor (
Current flows only through the parallel circuit of 17) and 2 and the light emitting element (10). Resistor (16) and capacitor (17)
Since the impedance of the parallel circuit with the light-emitting element (10) has a high-pass characteristic, peaking occurs at the rise of the drive current waveform (27) of the light-emitting element (10), shortening the rise time of the optical output of the light-emitting element (10). do.
変調信号（２３）か低しヘル覧の期間Ｔ２．Ｔ４ （
第２図参照）には、ＦＥＴ （１５）のドレイン・ソー
ス間抵抗は数百Ωとなり、３端子スイッチ（１８）は導
通状態となるため、抵抗（１６）とコンデンサ（１７）
との並列回路およびＦＥＴ （１５）のドレイン・ソー
ス間にはほとんど電流は漬れず、発光素子（１０）と３
端子スイッチ（１８）の経路を通じて発光素子（１０）
の蓄積電荷か放電される。発光素子（１０）の駆動電流
波形（２７）の立下がり時には、消光する側にサグ電流
が流れることになり、発光素子（１０）の光出力の立下
がり時間が短縮される。The modulation signal (23) is low during the period T2. T4 (
(see Figure 2), the resistance between the drain and source of the FET (15) is several hundred Ω, and the 3-terminal switch (18) is in a conductive state, so the resistor (16) and capacitor (17)
There is almost no current flowing between the parallel circuit between the light emitting element (10) and the drain and source of the FET (15).
Light emitting element (10) through the path of terminal switch (18)
The accumulated charge is discharged. When the driving current waveform (27) of the light emitting element (10) falls, a sag current flows to the side where light is extinguished, and the fall time of the optical output of the light emitting element (10) is shortened.
しかして、発光素子（１０）の立上がりは、抵抗（１６
）とコンデンサ（１７）との並列回路の高域通過特性に
より高速化され、また発光素子（１０）の立下がりは、
３端子スイッチ（１８）で発光素子（１０）の蓄積電荷
を放電することにより高速化される。Therefore, the rise of the light emitting element (10) is caused by the resistance (16
) and the capacitor (17) in parallel circuit, the speed is increased, and the falling edge of the light emitting element (10) is
The speed is increased by discharging the accumulated charge of the light emitting element (10) with the three-terminal switch (18).
また、従来の発光素子駆動回路で用いられていた電流切
換回路は、変調信号のパターンによらず常時発光素子駆
動電流のピーク値と同じ電流が消費されるが、この実施
例の発光素子駆動回路では、発光素子（１０）か発光状
態にあるときのみ電流か消費されるので、大幅な低消費
電力化が可能となる。In addition, the current switching circuit used in the conventional light emitting element drive circuit always consumes the same current as the peak value of the light emitting element drive current regardless of the modulation signal pattern, but the light emitting element drive circuit of this embodiment consumes the same current as the peak value of the light emitting element drive current. Since current is consumed only when the light emitting element (10) is in the light emitting state, it is possible to significantly reduce power consumption.
第３図はこの発明の他の実施例を示すものて、上記実施
例における３端子スイッチ（１８）をＦＥＴ（２８）で
構成するようにしたものである。すなわち、反転変調信
号（２６）が制御信号として入力される制御信号入力端
子（２２）には、ＦＥＴ （２８）のゲートか接続され
、また３端子スイッチ（１８）の第１の端子（１９）に
はＦＥＴ （２８）のソースが接続され、さらに３端子
スイッチ（１８）の第２の端子（２０）には、ＦＥＴ（
２８）のドレインが接続されている。FIG. 3 shows another embodiment of the present invention, in which the three-terminal switch (18) in the above embodiment is constructed with an FET (28). That is, the control signal input terminal (22) to which the inverted modulation signal (26) is input as a control signal is connected to the gate of the FET (28), and is also connected to the first terminal (19) of the three-terminal switch (18). The source of the FET (28) is connected to the FET (28), and the second terminal (20) of the three-terminal switch (18) is connected to the FET (28).
28) is connected to the drain.
以上の構成において、反転変調信号（２６）の高レベル
■°、、低しヘルｖ′、は、以下の関係式を満たす。In the above configuration, the high level ■°, and the low level v' of the inverted modulation signal (26) satisfy the following relational expression.
Ｖ’Ｈ＝ Ｏ（ＧＮＤレベル） ・・・（３
）Ｖｓ ｍｉｎ ｖ’、 ＞ Ｖｔｈ
−（４）但し、ＶＳｍｌｎ：発光素子（１０）の
カソード電位の最小値
ｖｔｈＦＥＴ（２８）ノ闇値電圧
上記（４）式は、発光素子（１０）の光出力オン時にＦ
ＥＴ （２８）がオフ状態にあり、発光素子（１０）の
駆動電流がすべて発光素子（１０）に流れるための条件
式ところで、ＧａＡｓ系、Ｉｎｐ系発光素子においては
、ＶＳｍｉ。は−１６〜−２，０（Ｖ）程度であり、反
転変調信号（２６）の振幅は２〜３（ｖ）程度必要とな
る。上記（３）式、（４）式より、ＦＥＴ （２８）は
飽和スイッチング動作を行ない、反転変調信号（２６）
が高レベルＶ′□のとき数Ω、低レベルｖ′、のとき数
百Ωとなり、はぼ理想的な３端子スイッチとして動作す
る。発光素子（１０）の光出力の立下がり時間は、発光
素子（１０）の接合容量ＣｔｌとＦＥＴ （２８）のオ
ン抵抗γＤＳＯＮとで決定され、オン抵抗γＤＳＯＮは
、上記のとおり数Ωてあり、充分高速化が可能となる。V'H = O (GND level) ... (3
)Vs min v', > Vth
-(4) However, VSmln: Minimum value of the cathode potential of the light emitting element (10) vthFET (28) dark value voltage The above equation (4) indicates that when the light output of the light emitting element (10) is on
ET (28) is in the off state and all the drive current of the light emitting element (10) flows to the light emitting element (10).By the way, in GaAs-based and Inp-based light emitting elements, VSmi. is approximately -16 to -2.0 (V), and the amplitude of the inverted modulation signal (26) is required to be approximately 2 to 3 (V). From equations (3) and (4) above, FET (28) performs saturation switching operation, and the inverted modulation signal (26)
When the voltage is at a high level V'□, it is several ohms, and when it is a low level v', it is several hundred ohms, and it operates as an ideal three-terminal switch. The fall time of the optical output of the light emitting element (10) is determined by the junction capacitance Ctl of the light emitting element (10) and the on-resistance γDSON of the FET (28), and the on-resistance γDSON is several Ω as described above. Sufficient speed-up is possible.
また、ＦＥＴとしてＧａＡｓＭＥＳＦＥＴを用いること
により、ＦＥＴのドレイン・ソース間抵抗値の波形（２
５）の立上がり、立下がり時間は３００ （Ｐ ５ｅｃ
）程度となり、ＩＧｂ／ｓ程度の変調か可能となり、高
速化にも適している。In addition, by using a GaAs MESFET as the FET, the waveform of the resistance value between the drain and source of the FET (2
5) rise and fall times are 300 (P 5ec
), which enables modulation of the order of IGb/s and is suitable for high-speed operation.
なお、上記両実施例では、３端子スイッチ（１８）の第
２の端子（２０）を発光素子（１０）のアノードと同電
位のＧＮＤレベルに接続する場合を示したが、発光素子
（ｌＯ）のアノード電位以上の任意の電位に接続しても
同様の効果が期待てきる。In both of the above embodiments, the second terminal (20) of the three-terminal switch (18) is connected to the GND level, which has the same potential as the anode of the light emitting element (10). A similar effect can be expected even if connected to any potential higher than the anode potential of .
また、上記両実施例では、制御信号として発光素子（１
０）の変調信号の反転信号を用いる３端子スイッチ（１
８）について示したが、変調信号と同相の信号を制御信
号として用いるタイプの３端子スイッチを用いても同様
の効果が得られる。In both of the above embodiments, the light emitting element (1
A three-terminal switch (1) that uses the inverted signal of the modulation signal of
Although 8) was shown above, the same effect can be obtained by using a three-terminal switch of the type that uses a signal in phase with the modulation signal as a control signal.
この発明は以上説明したとおり、ＦＥＴと、抵抗・コン
デンサの並列回路と、３端子スイッチとで駆動回路を構
成するようにしているので、発光素子のインピーダンス
が大きい場合でも、光出力の立上がり、立下がり時間を
充分短縮することができ、また大幅な低消費電力化を図
ることができる等の効果がある。As explained above, in this invention, the drive circuit is configured with an FET, a parallel circuit of a resistor/capacitor, and a three-terminal switch, so even if the impedance of the light emitting element is large, the rise and fall of the optical output There are effects such as the fall time can be sufficiently shortened and power consumption can be significantly reduced.
第１図はこの発明の一実施例に係る発光素子駆動回路を
示す回路図、第２図は第１図に示す回路の各部波形図、
第３図はこの発明の他の実施例を示す第１図相当図、第
４図は従来の発光素子駆動回路を示す回路図、第５図は
第４図に示す発光素子駆動回路の各部波形図である。
（１０）・・・発光素子、（１５）、（２８）・・・Ｆ
ＥＴ 、（１Ｂ）・・・抵抗、（１７）・・・コンデン
サ、（１８）・・・３端子スイッチ、（１９）・・・第
１の端子、（２０）・・・第２の端子、（２１）・・・
ゲート入力端子、（２２）・・・制御信号入力端子。
なお、各図中、同一符号は同−又は相当部分を示す。FIG. 1 is a circuit diagram showing a light emitting element driving circuit according to an embodiment of the present invention, FIG. 2 is a waveform diagram of each part of the circuit shown in FIG. 1,
3 is a diagram corresponding to FIG. 1 showing another embodiment of the present invention, FIG. 4 is a circuit diagram showing a conventional light emitting element driving circuit, and FIG. 5 is a waveform of each part of the light emitting element driving circuit shown in FIG. 4. It is a diagram. (10)...Light emitting element, (15), (28)...F
ET, (1B)...resistor, (17)...capacitor, (18)...3-terminal switch, (19)...first terminal, (20)...second terminal, (21)...
Gate input terminal, (22)...control signal input terminal. In each figure, the same reference numerals indicate the same or corresponding parts.
Claims (1)
と、このＦＥＴのドレインと発光素子のカソードとの間
に接続された抵抗・コンデンサの並列回路と、第１の端
子が発光素子のカソードと上記並列回路との間に接続さ
れるとともに、第２の端子が上記発光素子のアノード電
位以上の任意の電位を有する電源に接続され、上記変調
信号又はその反転信号が制御信号として入力される３端
子スイッチとを具備することを特徴とする発光素子駆動
回路。A field effect transistor whose gate receives a modulation signal, a parallel circuit of a resistor/capacitor connected between the drain of this FET and the cathode of the light emitting element, and a first terminal connected to the cathode of the light emitting element and the above parallel circuit. a three-terminal switch, the second terminal of which is connected to a power supply having an arbitrary potential higher than the anode potential of the light emitting element, and into which the modulation signal or its inverted signal is input as a control signal; A light emitting element drive circuit comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63026063A JPH01201972A (en) | 1988-02-06 | 1988-02-06 | Luminescent element driving circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63026063A JPH01201972A (en) | 1988-02-06 | 1988-02-06 | Luminescent element driving circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01201972A true JPH01201972A (en) | 1989-08-14 |
Family
ID=12183225
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63026063A Pending JPH01201972A (en) | 1988-02-06 | 1988-02-06 | Luminescent element driving circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01201972A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01298774A (en) * | 1988-05-27 | 1989-12-01 | Nec Corp | Drive circuit for light emitting deode |
| JPH04233776A (en) * | 1990-08-06 | 1992-08-21 | American Teleph & Telegr Co <Att> | Led driving circuit |
| JPH05308158A (en) * | 1992-04-30 | 1993-11-19 | Mitsubishi Electric Corp | Transmitting circuit |
| JPH06296042A (en) * | 1993-04-05 | 1994-10-21 | Murata Mach Ltd | High-speed on/off circuit for light-emitting diode |
-
1988
- 1988-02-06 JP JP63026063A patent/JPH01201972A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01298774A (en) * | 1988-05-27 | 1989-12-01 | Nec Corp | Drive circuit for light emitting deode |
| JPH04233776A (en) * | 1990-08-06 | 1992-08-21 | American Teleph & Telegr Co <Att> | Led driving circuit |
| JPH05308158A (en) * | 1992-04-30 | 1993-11-19 | Mitsubishi Electric Corp | Transmitting circuit |
| JPH06296042A (en) * | 1993-04-05 | 1994-10-21 | Murata Mach Ltd | High-speed on/off circuit for light-emitting diode |
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