JPH01201868A - System for controlling time base of disk player - Google Patents

Abstract

PURPOSE:To realize stable control even when external synchronization is performed by adjusting a time base by controlling rotating speed based on a frequency error signal and a phase error signal generated by starting the rotary driving of a recording disk corresponding to a command. CONSTITUTION:The rotary driving of the recording disk 1 is started responding to the command of a system controller 10. The rotating speed of the disk 1 is controlled based on the frequency error signal from a frequency discrimination circuit 13 corresponding to the frequency of the second synchronizing signal of a horizontal synchronizing signal, etc., from a synchronizing separator circuit 11 obtained by a signal read-means 3, and the phase error signals from phase comparator circuit 14 and 29 corresponding to the phase difference of the first synchronizing signal of a vertical synchronizing signal, et., and the output of a reference clock generation circuit 20 or the reference signal of an external synchronizing signal IN1, then, the time base control is performed. The external synchronization is performed by using field synchronization or the signal IN1 of frame synchronization supplied from the outside as a reference signal, and it is possible to prevent disturbance in the control of the time base from being generated even when plural players play the same frame.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a time axis control method for a disc player that reproduces information such as video information recorded on a recording disc.

BACKGROUND ART A disk player performs coarse adjustment of the time axis by controlling the relative speed between the disk and a pickup serving as a signal reading means by controlling the drive of a spindle motor that rotates the disk. Fine 2J adjustment of the time axis is performed by delaying the signal by a time corresponding to the phase difference between the synchronization signal in the read signal and a separately generated reference signal using a CCD, memory, etc., which cannot be removed by coarse adjustment alone. It is usually constructed to remove residual jitter and ivy caused by eccentricity of the disk, etc.

On the other hand, for example, so-called high-definition (HLgh)
Def'1nltion) The video signal is recorded on multiple discs by channel division, and the signals recorded on multiple discs are combined in the reverse procedure of recording by synchronizing multiple players. It has been proposed to record and reproduce signals with a wide signal band by doing so.

In such cases, it is necessary for multiple players to play the same frame. However, CLV
On a disc, video signals for about 3 frames are recorded on the outermost track, and unlike CAV discs, video signals for 1 frame are recorded on 1 track. It is not possible to play the same frame only by track jumping and frame synchronization.

Therefore, an error signal is generated depending on the phase difference between the synchronization signal in the read signal obtained by the pickup and the reference signal of the frame period, and the difference between the address information in the read signal and the address information supplied from the outside. It is conceivable that a plurality of players play the same frame by changing the rotational speed of the spindle motor. However, in the conventional time axis control method, the time axis is roughly adjusted by driving the spindle motor and controlling the relative speed between the disk and the pickup. There was a risk that axis control would become unstable.

Summary of the Invention The present invention has been made in view of the above points, and includes:
An object of the present invention is to provide a time axis control method for a disc player that can perform stable control even when external synchronization is performed.

The time axis control method for a disc player according to the present invention starts rotating the recording disc in response to a command, and responds to the frequency of a second synchronization signal such as a horizontal synchronization signal in a read signal obtained by a signal reading means. A phase error signal is generated according to the phase difference between a reference signal and a first synchronization signal such as a vertical synchronization signal in a read signal, and a frequency error signal is generated based on the generated frequency error signal and phase error signal. It is characterized by adjusting the time axis by controlling the rotation speed.

Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In FIG. 1, a disk 1 is rotationally driven by a spindle motor 2. As shown in FIG. As the disk 1 rotates, signals recorded on the disk 1 are read by the pickup 3. The pickup 3 includes a laser diode, an objective lens, a focus actuator, a tracking actuator, a photodetector, and the like.

The output of the photodetector in the pickup 3 is supplied to an RF amplifier 4 and at the same time, a focus servo circuit 5 and a tracking servo circuit 6. The focus actuator and the tracking actuator in the pickup 3 are driven by the focus servo circuit 5 and the tracking servo circuit 6, and the laser light emitted from the laser diode in the pickup 3 is focused on the recording surface of the disk 1 to reach the signal reading point. (light spot)
is formed, and this signal reading point is controlled to be located on the track.

The pickup 3 is carried by a slider (not shown) supported movably in the radial direction of the disk 1, and a slider servo circuit 7 controls a slider motor for driving the slider. The relative position of the pickup 3 in the radial direction is controlled.

The RF multiplied signal output from the RF amplifier 4 is supplied to a demodulation circuit 8 comprising an FM demodulator and the like. A video signal is reproduced by this demodulation circuit 8. This playback video signal is
The signal is supplied to a jitter correction circuit (not shown) that performs fine adjustment of the time axis and removes residual jitter, and at the same time is supplied to the synchronization separation circuit 11 and the time code reading circuit 12. In the synchronization separation circuit 11, vertical and horizontal synchronization signals in the reproduced video signal are separated. Further, the time code reading circuit 12 outputs time codes obtained by reading the Philips codes inserted in portions corresponding to the 16th to 18th lines and the 279th to 281st lines of the video signal. The output of this time code reading circuit 12 is
It is supplied to the system controller 10.

On the other hand, the reproduced horizontal synchronization signal output from the synchronization separation circuit 11 is supplied to a frequency discrimination circuit 13 and a phase comparison circuit 14. The frequency discrimination circuit 13 is supplied with counting pulses having the same frequency as the color subcarrier, for example, from the frequency dividing circuit 17. Further, the phase comparison circuit 14 is supplied with a reference horizontal synchronization signal output from the changeover switch 18. The changeover switch 18 is configured to selectively output one of the reference horizontal synchronization signals output from each of the frequency dividing circuit 17 and the synchronization separation circuit 19 in response to the switching command signal SA output from the system controller 10. It has become. The frequency dividing circuit 17 is configured to divide the frequency of the reference clock output from the reference clock generation circuit 20 made of a crystal oscillator or the like to generate a reference horizontal synchronization signal and a counting pulse. Further, the synchronous separation circuit 19 is
The vertical and horizontal synchronization signals are separated from the composite synchronization signal supplied from the outside via the input terminal IN+ and output as a reference vertical synchronization signal and a reference horizontal synchronization signal, respectively.

The frequency discrimination circuit 13 has a counter that is reset by, for example, a reproduced horizontal synchronizing signal and counts up by a counting pulse, and outputs a frequency discrimination signal having a level corresponding to the frequency of the reproduced horizontal synchronizing signal based on the output of this counter. It becomes. The output of this frequency discrimination circuit 13 is supplied to a control signal generation circuit 22. Further, the phase comparison circuit 14 compares the phases of the reproduced horizontal synchronization signal and the reference synchronization signal, and outputs a phase difference signal corresponding to the phase difference between the two signals. This phase difference signal is supplied to the lock detection circuit 23 and simultaneously supplied to the control signal generation circuit 22 via the switch 24. The output of the adder circuit 25 is also supplied to the control signal generation circuit 22 . The control signal generation circuit 22 is configured to add and synthesize these frequency discrimination signals, phase difference signals, and addition outputs, and then outputs the resultant signals via a loop filter, a loop gain adjustment circuit, and the like. The lock detection circuit 23 is configured to output a lock detection signal jll+, for example, when the absolute value of the phase difference signal becomes less than or equal to a predetermined value. The detection output of this lock detection circuit 23 is transmitted to the system controller 10.
is supplied to Further, the switch 24 is configured to be turned on in response to an on command signal sB output from the system controller 10.

The output of the control signal generation circuit 22 is supplied to the spindle motor 2 via a drive amplifier 27 as a drive signal.

Here, a pickup 3, an RF amplifier 4, a demodulation circuit 8,
Synchronous separation circuit 11, frequency discrimination circuit 13, control signal generation circuit 22, drive amplifier 27, and spindle motor 2
Therefore, the frequency control loop of the spindle servo based on the horizontal synchronization signal is always closed, and the spindle motor 2 is driven by this frequency control loop so that the frequency of the reproduced horizontal synchronization signal becomes a specified value. Moreover, when the switch 24 is turned on, the frequency discrimination circuit 13 in the frequency control loop of the spindle servo based on the horizontal synchronization signal
A phase control loop obtained by replacing the phase comparison circuit 14 with the phase comparison circuit 14 is closed. The spindle motor 2 is driven by this phase control loop so that the reproduced horizontal synchronizing signal and the reference horizontal synchronizing signal match in phase. Rough adjustment of the time axis is performed by drive control of the spindle motor 2 using these frequency and phase control loops.

On the other hand, the reproduced vertical synchronization signal output from the synchronization separation circuit 11 is supplied to the phase comparator circuit 29 and output from the synchronization separation circuit 19.
2 outputted from! -■ A phase comparison is made with the vertical synchronization signal, and a phase difference signal corresponding to the phase difference between both signals is output. This phase difference signal is supplied to the lock detection circuit 30 and simultaneously supplied to the addition circuit 25 via the switch 31. The adder circuit 25 is supplied with the output of an error signal generation circuit 33, which is composed of, for example, a D/A (digital-to-analog) converter and generates an error signal according to data sent from the system controller 10. Like the lock detection circuit 23, the lock detection circuit 30 is configured to output a lock detection signal I2 when the absolute value of the phase difference signal becomes a predetermined value or less. The detection output of this lock detection circuit 30 is supplied to the system controller 10.

Further, the switch 31 is configured to be turned on in response to an on-command signal S ( output from the system controller 10 ).

When this switch 31 is turned on, the pickup 3, R
F amplifier 4, demodulation circuit 8, synchronous separation circuit 11, phase comparison circuit 29, switch 31, addition circuit 25, control signal generation circuit 22, drive amplifier 27, and spindle motor 2
A phase control loop is closed by the vertical synchronization signal formed by: - The spindle motor 2 is driven so that the reproduced vertical synchronization signal and the reference vertical synchronization signal match in phase.

The system controller 10 includes, for example, Procera f, RO
It is formed by a microcomputer consisting of MSRAM and the like. In addition to the read time code and the lock detection signal, the system controller 10 is supplied with various commands issued by key operations on an operation section (not shown), a reference time code supplied from the outside to the input terminal IN2, and the like. In this system controller 10, the processor is R
The input signals are processed according to the program stored in advance in the OM, and the switching command signal SAs and the on-command signal SB are generated.
Each part is controlled by sending out %SC.

The operation of the processor of the system controller 1° in the above configuration will be explained with reference to the flowcharts of FIGS. 2 and 3.

When a command to command a play operation synchronized with an external composite synchronization signal is issued by operating a key on the operation unit during execution of a main routine, etc., the processor moves to step S1 and outputs a switching command signal SA and an on-command signal SB. The transmission of the switching command signal SA and the ON command signal sB of %SC is started, and the horizontal synchronization signal of the external composite synchronization signal is selectively output from the changeover switch 18, and the switch 24 is turned on and the switch 31 is turned off. Initialize so that

Next, the processor sends predetermined data to the error signal generation circuit 33 for a predetermined period of time to cause the spindle motor 2 to
is forcibly accelerated (step S2).

Next, the processor repeatedly determines whether or not the lock detection signal 11+ has been output from the lock detection circuit 23 (step S3), and only when it is determined that the lock detection signal II+ has been output, sends the ON command signal sB. At the same time as it stops, it starts sending out the on command signal sc (step S4). Next, the processor repeatedly determines whether or not the lock detection signal N2 has been output from the lock detection circuit 30 (step S5), and only when it is determined that the lock detection signal g2 has been output, turns on the ON command signal s.
B is started, and execution of the routine that was being executed immediately before proceeding to step S1 is resumed.

Furthermore, when a command to command a play operation synchronized with the reference time code is issued by a key operation on the operation unit during execution of a main routine, etc., the processor moves to step S10 and outputs a switching command signal SA and an on-command signal 5BSSC.
The transmission of the switching command signal SA and the ON command signal sB is started, and the horizontal synchronization signal of the external composite synchronization signal is selectively output from the changeover switch 18, so that the switch 24 is turned on and the switch 31 is turned off. Initialize to . Next, the processor sends predetermined data to the error signal generation circuit 33 to forcibly drive the spindle motor 2 (step 511). Next, the processor takes in the time code output from the time code reading circuit 12 (step 512). Next, the processor calculates the difference between the captured time code and the externally supplied reference time code (step 513). The processor then determines whether the calculated value of D is less than n (step 514).

When it is determined in step S14 that the value of D is not smaller than n, the processor sends a slider feed command to the slider servo circuit 7 or a track jump command to the tracking servo circuit 6 according to the value of D. Step 515), the process returns to step S12. When it is determined in step S14 that the value of D is smaller than n, the processor stops sending out the on-command signal sB and simultaneously starts sending out the on-command signal s (step 516), depending on the value of D. The generated data is supplied to the error signal generation circuit 33 (step 517). Next, the processor captures the time code output from the time code reading circuit 12 (step 518). Next, the processor calculates the difference between the captured time code and the externally supplied reference time code (step 51).
9). The processor then determines whether the calculated value of D is 0 (step 520).

When it is determined in step S20 that the value of D is not 0, the processor moves to step S17 again.

When it is determined in step S20 that the value of D is 0, the processor starts sending out the ON command signal sB (step 521), and resumes execution of the routine that was being executed immediately before proceeding to step SIO.

In the above operation, when a play operation synchronized with an external composite synchronization signal is commanded, the phase control loop by the horizontal synchronization signal is closed in step S1, and then the spindle motor 2 is forced to operate for a predetermined time in step S2. be accelerated. Then, the demodulation circuit 8 starts demodulating the video signal, and the synchronization separation circuit 11 starts outputting a reproduced horizontal synchronization signal. Then, the frequency control loop by the horizontal synchronization signal is always closed,
In addition, since the phase control loop using the horizontal synchronizing signal is closed in step S1, the frequency of the reproduced horizontal synchronizing signal becomes a predetermined value and the phase of the reproduced horizontal synchronizing signal is supplied as the reference horizontal synchronizing signal. The spindle motor 2 is driven and controlled so as to match the phase of the horizontal synchronization signal in the signal.

After this, as the phase control loop based on the horizontal synchronization signal locks, the lock detection circuit 23 sends a lock detection signal g.
1 is output. When it is detected in step S3 that this lock detection signal Ω1 is output, step S
4 is executed to open the phase control loop based on the horizontal synchronizing signal, and at the same time, the phase control loop based on the vertical synchronizing signal is closed. Then, the spindle motor 2 is driven and controlled so that the phase of the reproduced vertical synchronization signal matches the phase of the vertical synchronization signal in the external composite synchronization signal supplied as the reference vertical synchronization signal. At this time, since the frequency control loop based on the horizontal synchronization signal is closed, stable control is achieved.

After that, as the phase control loop based on the vertical synchronization signal is locked, a lock detection signal g is sent from the lock detection circuit 30.
2 is output. When it is detected in step S5 that this lock detection signal g2 has been output, step S5
6 is executed and the phase control loop based on the horizontal synchronization signal is closed again.

As a result, the spindle servo loop becomes more stable, and rough adjustment of the time axis synchronized with the external composite synchronization signal can be made in a stable state.

In addition, when a play operation synchronized with the reference time code is commanded, steps S1 and S2 and step S
10. The spindle motor is controlled so that the frequency of the reproduced horizontal synchronizing signal becomes a predetermined value by the SLL and the phase of the reproduced horizontal synchronizing signal matches the phase of the horizontal synchronizing signal in the external composite synchronizing signal supplied as the reference horizontal synchronizing signal. 2 is driven and controlled. Thereafter, in steps S12 to S15, slider feeding and track jumping are repeated until the difference between the time code read from the disc 1 and the reference time code becomes smaller than n. As a result, approximately 3 frames worth of video signals are recorded on the outermost track of the CLV disk on which the NTSC video signal is recorded, so the reading position of the pickup 3 and the position indicated by the U quasi-time code are The separation distance can be set to 5 frames or less.

When it is detected in step S14 that the value of D has become smaller than n, step S16 is executed to open the phase control loop based on the synchronization signal and simultaneously close the phase control loop based on the vertical synchronization signal. After this,
In steps S17 to S20, phase difference information according to the value of D is added to the phase control loop based on the vertical synchronization signal,
The lock phase of the phase control loop by the vertical synchronization signal is shifted. As a result, the spindle motor 2 is driven and controlled so that the phase of the reproduced vertical synchronization signal matches the phase of the vertical synchronization signal in the external composite synchronization signal supplied as the reference vertical synchronization signal, and the value of D converges to 0. be done.

In addition, D added to the phase control loop by the vertical synchronization signal
The phase difference information according to the value of can be outputted continuously from the error signal generation circuit 33, or can be outputted intermittently, but in either case, the horizontal synchronization Since the frequency control loop based on the signal is closed, stable control is achieved.

When it is detected in step S20 that the value of D has become O, step S21 is executed and the phase control loop based on the horizontal synchronization signal is closed again. As a result, the spindle servo loop becomes more stable, and rough adjustment of the time axis in synchronization with the reference time code and external composite synchronization signal can be performed in a stable state.

In the above embodiment, the phase control in the phase control loop using the vertical synchronization signal is performed every time the vertical synchronization cycle, that is, the vertical synchronization signal is detected, but even if the phase control is performed at the frame cycle, good. however,
Using vertical synchronization cycles allows for a wider loop band and is superior in terms of stability and responsiveness.

The above has described a performance device for a disc on which a video signal according to the NTSC system is recorded. However, the present invention is directed to a disc on which a so-called MUSE signal obtained by band-compressing a high-definition video signal to a bandwidth of approximately 8 MHz is recorded. It can also be applied to other musical performance devices. In that case, in addition to the configuration shown in FIG. 1, an A/D conversion circuit for analog-to-digital conversion of the MUSE signal output from the demodulation circuit 8 is required, and at the same time, the synchronization separation circuit 11 is replaced by a synchronization detection circuit as shown in FIG. It is necessary to replace it with .

In FIG. 4, data obtained by A/D converting the MUSE signal is supplied to an FPP output circuit 40, an HD pattern detection circuit 41, and a delay circuit .

In addition, a clock pulse C output from a VCO (voltage controlled oscillator) (not shown) is transmitted to the FPP output circuit 40, the HD detection window generation circuit 43, the HD pattern detection circuit 41, and the delay circuit 4.
2. HD phase detection circuit 44, clamp pulse generation circuit 4
5.

The FPP output circuit 40 detects the frame pulse in the MUSE signal by pattern recognition and outputs the FP detection detection pulse. That is, the frame pulse pattern as shown in FIG. 5(A) is sequentially recognized by the clock pulse C as shown in FIG. p is detected, and an FP detection detection pulse signal as shown in FIG. 3(C) is generated. This FP detection pulse generator is supplied to an HD detection window generation circuit 43 and a clamp pulse generation circuit 45. The HD detection window generation circuit 43 generates a detection window signal that exists for 24 clock periods to detect the HD signal immediately after the frame pulse point p using the FP detection detection pulse signal, and then
HD detection signal e output from the D pattern detection circuit 41
Every time the FP detection detection pulse signal is generated, a signal that exists for 24 clock periods from a point after 465 clock periods to a point after 489 clock periods with reference to the rising point of 2 is output as a detection window signal. Repeat.

The detection window signal is supplied to the HD pattern detection circuit 41. The HD pattern detection circuit 41 recognizes the existence of the HD signal as shown in FIG. 6(A) based on the pattern only when the detection window signal exists, and detects the HD signal in synchronization with the clock pulse C as shown in FIG. 6(B). The HD detection signal e2 is generated as shown in FIG. The pattern recognition in the HD pattern detection circuit 41 is performed, for example, on the pattern in section A shown in FIG. 6, that is, in about three clock periods immediately before and after the HD point. HD points are
If there is no jitter, it will exist 477 clock periods away from the rising point of the HD detection signal e2, so
The HDD bay window signal output from the HDOD window generation circuit 43 exists for 24 clock periods centered on the next HD point. This 24 clock period width is HD
This is the detection range.

Furthermore, data obtained by A/D converting the MUSE signal is delayed by a predetermined clock period by a delay circuit 42 and then supplied to an HD position I detection circuit 44 . The HDD phase detection circuit 44 corresponds to a value obtained by subtracting 128 level, which is the reference value of the HD point, from the output data of the delay circuit 44 in synchronization with the first clock pulse C after the generation of the first HD detection signal e2. An analog signal having a level of 1 is output as the HD detection signal layer 1, and thereafter, an analog signal obtained in the same manner is output as the HD detection signal layer 1 every 480 clock periods. At the same time, the HDD phase detection circuit 44 detects the HD detection signal layer 1 every 480 clock periods.
The HD detection OK signal d is output by the occurrence of the signal d and e2.

The HD detection signal layer 1 output from this HDD phase detection circuit 44 has phase error information of the clock pulse C with respect to the HD point. By supplying this HD detection signal to the VCO through the layer 1 loop filter, etc., and obtaining the clock pulse C from this VCO, a clock pulse C synchronized with the HD point can be obtained. You can make fine adjustments to the time axis.

Incidentally, since the HD point is located three clock periods before the generation of the HD detection signal e2, the delay circuit 42 is provided to adjust this delay, and is constituted by a latch circuit or the like.

Further, the clamp pulse generation circuit 45 detects a clamp level period provided on, for example, the 563rd line of the MUSE signal using the FP detection pulse g and the HD detection OK signal d, and outputs a clamp pulse f over the period. . This clamp pulse f can be used when clamping is performed for DC reproduction of the MUSE signal.

The HD detection signal e2 output from the HD pattern detection circuit 41 in the above configuration is used as a reproduction horizontal synchronization signal in the apparatus shown in FIG. 1, and the FP detection pulse g output from the FP detection circuit 40 is used as a reproduction vertical synchronization signal. By using this, when playing a disc on which MUSE signals are recorded, the same effect as when playing a disc on which NTSC signals are recorded will work.

Effects of the Invention As detailed above, the time axis control method for a disc player according to the present invention starts the rotational drive of the recording disc in response to a command, and controls the horizontal synchronization, signal, etc. in the read signal obtained by the signal reading means. A frequency error signal corresponding to the frequency of the second synchronization signal and a phase error signal corresponding to the phase difference between the first synchronization signal such as the vertical synchronization signal in the read signal and the reference signal are generated, and the generated frequency error signal and Since the rotation speed of the recording disk is controlled based on the phase error signal and the time axis is adjusted, external synchronization is performed by using a field period or frame period signal supplied from the outside as a reference signal. It is possible to prevent disturbances in time axis control.

Additionally, by generating an error signal according to the difference between the address information in the read signal and the reference address information and adding it to the phase error signal, multiple players can read the same frame while performing stable time axis control. It can be made to play.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIGS. 2 and 3 are flowcharts showing the operation of the processor in the device shown in FIG. 1, and FIG. 4 is a disk on which the MUSE signal is recorded. 5 and 6 are waveform diagrams showing the operation of the circuit shown in FIG. 4. FIGS. Applicant Pioneer Corporation

Claims (2)

[Claims] (1) A first synchronization signal generated at a period N (N is a natural number) times one field period and 1/M (M
is a natural number), the time axis is determined by the first and second synchronization signals obtained by the signal reading means from the video signal into which the second synchronization signal is inserted and which carries the address information for information search. A time axis control method that performs adjustment, in which rotation of the recording disk is started in response to a command, and a frequency error signal is generated according to the frequency of a second synchronization signal in a read signal obtained by the signal reading means. and generating a phase error signal according to the phase difference between the first synchronization signal and the reference signal in the read signal, and controlling the rotational speed of the recording disk based on the frequency error signal and the phase error signal. A time axis control method for a disc player characterized by adjusting the axis. (2) The disk according to claim 1, wherein an address error signal is generated according to a difference between address information in the read signal and reference address information, and the address error signal is added to the phase error signal. Player time axis control method.