JPH0644681A - Video disk player - Google Patents

Abstract

PURPOSE:To obtain a constant frame phase by accelerating or decelerating the rotation of a video disk until the phase difference becomes half and changing over acceleration or deceleration to deceleration or acceleration when the phase difference reaches half. CONSTITUTION:A video signal from a demodulating circuit 12 is supplied to a synchronizing separator circuit 55, a frame synchronizing signal PBFM is fetched, supplied to a phase control circuit 52 and a phase difference theta between the signal PBFM and a frame signal REFFM having a reference phase is measured. When the acceleration of the rotation of the disk VD is started, the phase difference theta decreases. When the phase difference theta becomes half, an accelerating signal is stopped, a deceleration signal is formed and a driving voltage toward deceleration is formed and supplied to a spindle motor 21. Thus, the deceleration of the disk VD is started. When the phase difference theta is detected, formation of the deceleration is stopped and also the driving voltage toward deceleration signal is not formed. Consequently, the frame phase is stabilized in a short time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video disc player.

[0002]

2. Description of the Related Art NT is the current standard television system.
There are SC method, PAL method, SECAM method, etc.,
In the case of the NTSC system, the standard is horizontal frequency fHN = 4.5 MHz / 286 = approximately 15.734 kHz vertical frequency fVN = 2fHN / 525 = approximately 59.94 Hz aspect ratio = 3: 4.

A high-definition television system has been developed as a television system of higher quality than the NTSC system. The standard is vertical frequency fVM = 60Hz horizontal frequency fHM = 1125 × fVM / 2 = 33.75 kHz aspect ratio. = 9: 16.

Therefore, the video signal according to the high-definition system has an information amount about 5 times that of the video signal according to the NTSC system, and the video signal according to the high-definition system cannot be transmitted as it is by a broadcasting satellite, a video disc or the like.

Therefore, the video signal of the high-definition system is transmitted after being compressed by the so-called MUSE system (multiplex sub-Nyquist sampling system) so that the base band width becomes about 8 MHz. This MUSE method is basically dot interlaced transmission, and the sampling pattern is repeated in a 4-field cycle with offsets between frames, between fields, and between lines.

In the MUSE system, the video signal (luminance signal and color signal) and the quasi-instantaneous companding DPCM are used.
Audio data encoded by the method and an independent additional information signal are multiplexed on the time axis. However, MU
The horizontal frequency and the vertical frequency of the high-definition video signal compressed by the SE method are equal to the horizontal frequency fHM and the vertical frequency fVM of the original high-definition video signal.

In the following description, for simplification, a high-definition video signal data-compressed by the MUSE method is referred to as a "MUSE video signal". A video disc on which an NTSC video signal is recorded is referred to as "NTSC video disc", M
A video disc on which a USE video signal is recorded is called a "MUSE video disc".

An example of a video disc player for reproducing a MUSE type video disc, in particular, a rotation drive system for the disc will be described below with reference to FIGS. 1 and 2. However, the illustrated video disc player is a compatible player that can also reproduce an NTSC video disc. The right side of FIG. 1 is followed by the left side of FIG.

That is, in these figures, VD indicates an optical video disc, and this disc VD includes:
An NTSC video signal SNT or a MUSE video signal SMS is recorded.

In this case, when the disk VD is an NTSC video disk, the video signal SNT is converted into an FM signal, and the FM video signal, the FM audio signal, and the digital audio signal are frequency-multiplexed. The frequency multiplexed signal SN is recorded.

When the disc VD is a MUSE type video disc, the video signal SMS is converted into an FM signal, and the FM signal and the pilot signal S are converted.
P and P are frequency-multiplexed, and the frequency-multiplexed signal SM is recorded. The frequency f of the pilot signal SP
P is fP = 135 fHM / 2 = about 2.28 MHz (1).

Reference numeral 11 denotes an optical head, which reproduces a video signal from the disk VD. When the reproduced signal is the MUSE video signal SM, the original baseband video signal SMS is demodulated when the reproduced signal SM is supplied to the demodulation circuit 12, and the demodulated video signal SMS is converted to the TBC13. Through the MUSE output terminal 14. When the video signal SMS is reproduced, the head 11 also outputs the pilot signal SP at the same time. In addition, a decoder 1 for decoding the video signal SMS into an original high definition video signal is provided at the terminal 14.
Are connected.

The reproduction signal of the optical head 11 is NTC.
In the case of the S type video signal SN, the reproduction signal SN
Are supplied to the demodulation circuit 16 to demodulate the original baseband video signal SNT from the FM signal, and the demodulated video signal SNT is taken out to the NTSC output terminal 18 through the TBC 17. At this time, although the FM audio signal and the digital audio signal are simultaneously output from the head 11, these audio signals are supplied to the audio reproducing circuit 19 and the original audio signals are taken out.

Further, 21 is a spindle motor,
In a steady state, the disk VD is rotated by the motor 21 at a predetermined speed, and a frequency generator 22 is provided directly connected to the motor 21, for example, and an alternating signal S22 of 24 cycles is taken out per one rotation of the disk VD.

The optical head 11 is supported by the sled feed mechanism 23 to control the position of the disk VD in the radial direction, and the optical head 11 is moved in the radial direction of the head 11 from a potentiometer (not shown) provided in the feed mechanism 23. A DC voltage V23 having a value proportional to the position at is taken out.

Further, reference numeral 31 denotes an FG servo circuit, which is for keeping the rotational speed of the disk VD within a range of, for example, ± 20% of a specified value (normal value) during reproduction of the disk VD. The control signal S31 of the switch circuit 32 is also extracted from the servo circuit 31. For this reason,
The servo circuit 31 is configured, for example, as shown in FIG.

That is, the output signal S of the frequency generator 22
22 is supplied to the frequency discrimination circuit (frequency / voltage conversion circuit) 311 and the DC voltage V having a value proportional to the frequency of the signal S22.
22 and this voltage V22 is the voltage comparison circuit 312-314.
Is supplied to. When the disk VD is a CLV disk, the position voltage V23 of the head 11 from the sled feed mechanism 23 is supplied to the voltage dividing circuit 315, and the reference voltages VR + and V +.
R and VR- (VR +>VR> VR-) are formed, and these voltages are supplied to the comparison circuits 312 to 314, respectively.

In this case, the value of the voltage VR is the disk VD
Corresponds to the value of the voltage V22 when the rotation speed of the disk is the specified value, and the value of the voltage VR + corresponds to the value of the voltage V22 when the rotation speed of the disk VD is + 20% faster than the specified value.
Value is -20% of the rotation speed of the disk VD than the specified value.
Corresponds to the value of the voltage V22 at the slowest time.

The comparison output of the comparison circuit 313 is output as the error voltage V31.

The comparison output of the comparison circuit 313 is supplied to the T input of the T flip-flop circuit 318, and the comparison outputs of the comparison circuits 312 and 314 are supplied to the NOR circuit 3.
It is supplied to the reset input! R of the flip-flop circuit 318 through 17 (! R indicates negation, and so on).

Then, the Q of the flip-flop circuit 318
The output is supplied to the switch circuit 32 as its control signal S31, and the switch circuit 32 is connected to the state shown in the drawing when the rotation speed of the disk VD is not within the range of ± 20% of the specified value, and ± 20%. When it is within the range of, the connection is made in the opposite state to that shown in the figure.

Although not shown, the disk VD is C
In the case of an AV disc, instead of the position voltage V23, a constant reference voltage corresponding to the reference rotation speed is applied to the voltage dividing circuit 315.
And the voltage V31 and the signal S31 are output. Furthermore, when the disc VD is a MUSE type disc,
The frequency discriminating characteristic of the frequency discriminating circuit 311 is changed to the optimum characteristic when the disc is of the NTSC system.

Reference numeral 40 is a PLL, and 47 and 48 are bandpass filters. These are disc VD MUS
Although it is effective in the case of the E type disc, the reproduction signal SM from the head 11 is transmitted by the band pass filter 4
7 and 48 are sequentially supplied. In this case, the pass bands of these filters 47 and 48 are, for example, the filter 4
7 is fP ± 500 kHz (= fP ± 20%), and the filter 48 is fP ± 20 kHz.

Therefore, when the disk VD is rotating within the range of ± 20% of the normal rotation speed, the pilot signal SP can be obtained from the filter 47, and the disk VD can be rotated at the normal rotation speed (or sufficiently high). The pilot signal SP can also be obtained from the filter 48 when rotating at a close rotation speed.

Then, a filter 48 is provided by the PLL 40.
An alternating signal is formed in synchronism with the pilot signal SP from. That is, an oscillation signal S43 whose frequency is, for example, 12 times the frequency fP of the pilot signal SP is extracted from the VCO 43, and this signal S43 is supplied to the frequency dividing circuit 44 and divided into a frequency of 1/12, that is, the frequency fP. The frequency divided signal S44 is supplied to the phase comparison circuit 41, and the pilot signal SP from the filter 48 is supplied to the comparison circuit 41. Then, the comparison output of the comparison circuit 41 is supplied to the VCO 43 as its control voltage through the low pass filter 42 for the loop filter.

Therefore, from the filter 48 to the PLL 40
When the pilot signal SP is supplied to the VCO 43, an oscillation signal S43 having a frequency 12 times that of the pilot signal SP and having a synchronized phase is extracted from the VCO 43, and the frequency divider circuit 44 outputs a frequency equal to the pilot signal SP. Then, the alternating signal S44 having a synchronized phase is extracted.

At this time, a part of the comparison output of the comparison circuit 41 is supplied to the lock detection circuit 45, and the PLL 40
A detection signal S45 is taken out which indicates whether or not is locked to the pilot signal SP.

Further, 51 is a system controller composed of a microcomputer, 56 is a sync separation circuit, and 57 is a reference signal forming circuit for forming signals of various timings serving as a reference. Further, 63 is a frequency dividing circuit for dividing the frequency of the pilot signal SP into 1/135, 65 is a phase comparison circuit, and 66 is a low-pass filter for a loop filter. And, these circuits, when the rotation speed of the spindle motor 21 is within ± 20% of the specified value,
This is for realizing servo control of the motor 21 with higher precision than the servo circuit 31.

That is, as will be described in detail later, the disk V
When D is the MUSE system and the rotation speed of the spindle motor 21 is within ± 20% of the specified value, servo control is executed by the frequency dividing circuit 63, the comparing circuit 65, the pilot signal SP, and the frequency dividing signal S44. In addition, the disk VD is N
In the TSC method, when the rotation speed of the spindle motor 21 is within ± 20% of the specified value, the servo control is executed by the comparison circuit 65 and the horizontal synchronizing signal.

Further, reference numeral 68 denotes a lock detection circuit, and this detection circuit 68 detects when the servo of the servo loop including the phase comparison circuit 65 is locked. In addition, the switch circuit 64, 66 by the system controller 51
Is controlled, and the switch circuits 64 and 66 are connected to the disk VD.
Is a MUSE type disc, the state shown in the figure, NTS
In the case of a C type disc, the disc is connected in a state opposite to that shown in the drawing.

When the MUSE type disc VD is set in the player, the FG servo (servo control by the servo circuit 31) and the pilot servo (servo control using the pilot signal SP) are sequentially executed, and the disc VD is rotated at a prescribed rotational speed. The desired MUSE video signal SMS is reproduced.

When an NTSC type disc VD is set in the player, FG servo H servo (servo control using a horizontal synchronizing signal) is sequentially executed to set the disc VD at a prescribed rotation speed, and the target NTSC type Is reproduced. Then, these servo controls 1 to 3 are executed as follows.

When the MUSE type disc VD is set in the FG servo player, various detections are performed by the syscon 51 and the focus servo circuit and the tracking servo circuit (both not shown) are activated. Further, the rotation permission signal SPDL from the system controller 51 is set to “H”, this signal SPDL is supplied to the drive circuit 34, and a predetermined drive voltage is supplied from the drive circuit 34 to the spindle motor 21. Thus, the disk VD starts rotating.

When the disk VD starts to rotate, the rotation speed thereof is not yet within the range of ± 20% of the specified value, and the switch circuit 32 is connected in the state shown in the figure. Therefore, the servo circuit 31 Error voltage V31 output from
Are supplied to the drive circuit 34 through the lines of the switch circuit 32 and the adder circuit 33.

Therefore, the rotation speed of the disk VD is gradually increased by the FG servo circuit 31 and approaches the specified value.

Pilot Servo This pilot servo is executed when the disk VD is a MUSE type disk, but is executed first using the pilot signal SP and then using the frequency division signal S44.

That is, when the rotation speed of the disk VD falls within the range of ± 20% of the specified value, the FG servo circuit 31
The switch circuit 32 is switched to a state opposite to that shown in the figure by the control signal S31 from the. Therefore, first, the FG servo by the servo circuit 31 is turned off.

Further, in this state, since the PLL 40 is not yet locked, the lock detection signal S45 is "L", and this signal S45 is supplied to the switch circuit 61 through the AND circuit 62 as its control signal. 6
1 is connected in a state opposite to that shown in the figure.

At this time, since the rotational speed of the disk VD is within the range of ± 20% of the specified value, the pilot signal SP is output from the filter 47, but the pilot signal SP from this filter 47 is It is supplied to the frequency dividing circuit 63 through the switch circuit 61 and frequency-divided into a signal S63 having a frequency of 1/135. At this time, if the rotation speed of the disk VD is a specified value, the pilot signal SP
The frequency fP of the divided signal S63 is f63 = fP / 135 = fHM / 2 = 16.875 kHz (2)

Further, since the disc VD is a MUSE type disc and the switch circuits 64 and 66 are connected in the state shown in the figure, the frequency divided signal S63 is supplied to the phase comparison circuit 65 through the switch circuit 64. Further, in the forming circuit 57, the signal RE of the reference phase with the frequency fHM / 2 is used.
FH2M is formed, and this signal REFH2M is supplied to the comparison circuit 65 through the switch circuit 66 as a reference signal.

Thus, in the comparison circuit 65, the divided signal S63 obtained by dividing the pilot signal SP and the reference signal
The phase is compared with that of REFH2M, and the comparison output voltage V65 thereof is supplied to the drive circuit 34 through the line of the low pass filter 67 → the switch circuit 32 → the addition circuit 33 which is connected in the state opposite to that in the figure.

Therefore, in this case, the FG servo by the servo circuit 31 is turned off, and at the same time, the servo using the pilot signal SP, that is, the pilot servo is applied.
The rotation speed of the disk VD further approaches the specified value, and eventually reaches the specified value.

When the rotation speed of the disk VD reaches a specified value, the pilot servo locks at this time, but this is detected by the spindle lock detection circuit 68, and its detection output S68 = "H". Further, at this time, the pilot signal SP is obtained from the filter 48, and the PLL 40 is locked to this pilot signal SP, so that S45 = "H".

When S68 = "H" and S45 = "H", the output of the AND circuit 62 becomes "H", so that the switch circuit 61 is connected in the state opposite to that shown in FIG.
The frequency-divided signal S44 from is supplied to subsequent circuits through the switch circuit 61.

Therefore, thereafter, the pilot servo is continued by the frequency dividing signal S44 synchronized with the pilot signal SP, and the rotation speed of the disk VD is servo-controlled to a specified value.

At this time, the signal S from the PLL 40
43 is supplied to the TBC 13 as a clock for writing, and the forming circuit 57 forms a clock having a reference phase with the same frequency as the signal S43, and this clock is supplied to the TBC 13 as its reading clock. . Thus, the TBC 13 corrects the time axis of the reproduced MUSE video signal SMS.

H Servo This H servo is executed after the FG servo of when the disk VD is an NTSC disk.

That is, when the rotation speed of the disk VD falls within the range of ± 20% of the specified value, the FG servo circuit 31
The switch circuit 32 is switched to a state opposite to that shown in the figure by the control signal S31 from the. Therefore, first, the FG servo by the servo circuit 31 is turned off.

The disk VD is an NTSC disk, and the switch circuits 64 and 66 are connected in a state opposite to that shown in the drawing.

Then, the video signal S from the demodulation circuit 16
NT is supplied to the sync separation circuit 56 and the horizontal sync signal PBHN
Is taken out, and this synchronizing signal PBHN is sent to the switch circuit 64.
Is supplied to the phase comparison circuit 65 through the formation circuit 57 and the reference phase signal RE at the horizontal frequency fHN
FHN is formed, and this signal REFHN is supplied to the comparison circuit 65 through the switch circuit 66.

Thus, in the comparison circuit 65, the horizontal synchronizing signal PBHN separated from the video signal SNT and the reference signal
The phase is compared with that of REFHN, and the comparison output voltage V65 is supplied to the subsequent circuits through the low pass filter 67.

Therefore, in this case, the FG servo by the servo circuit 31 is turned off, and at the same time, the horizontal synchronizing signal PB
Since the servo using HN, that is, the H servo is applied, the rotation speed of the disk VD further approaches the specified value by the H servo, and eventually reaches the specified value.

Then, thereafter, the rotation speed of the disk VD is servo-controlled to a specified value by this H-servo.

At this time, the horizontal sync signal PBHN from the sync separation circuit 56 is supplied to the PLL 58 to form a signal of a predetermined frequency in synchronization with the signal PBHN.
The clock is supplied to the BC 17 as a clock for writing, and in the forming circuit 57, a clock having a phase serving as a reference of a predetermined frequency is formed.
7 is supplied as a clock for the reading. Thus, the TBC 17 corrects the reproduced NTSC video signal SNT on the time axis.

Summary In this way, according to the above-mentioned player, the MUSE type video disc VD and the NTSC type video disc V are used.
It is compatible with D and can be played back on either type of video disc VD.

In addition, in this case, when the pilot servo is performed on the MUSE type disk VD, the frequency f63 of the divided signal S63 supplied to the phase comparison circuit 65 is
As shown in equation (2), it is 16.875 kHz. Also, NT
When performing H-servo on the disk VD of SC system,
The frequency fHN of the horizontal synchronizing signal PBHN supplied to the phase comparison circuit 65 is about 15.734 kHz.

Therefore, the frequency f63 of the divided signal S63 during the pilot servo and the re-horizontal synchronization signal PB during the H servo are used.
Since the frequency fHN of HN is almost equal, as described above, the low-pass filter 67 can be used for both the pilot servo and the H servo, and it is not necessary to switch its characteristics. Therefore, it is possible to simplify the configuration of the servo loop of the pilot servo and the H servo, particularly the low-pass filter 67 that is a loop filter.

Further, during reproduction of the MUSE disc VD, the pilot signal SP is easily affected by dropout, and the waveform may be missing or missing. Therefore, the pilot signal SP from the filter 47 is always separated. When the frequency is supplied to the frequency dividing circuit 63 and the pilot servo is performed, the frequency dividing operation of the frequency dividing circuit 63 is disturbed by the dropout of the pilot signal SP, and the frequency dividing signal S63 contains about 4.4 per cycle of the pilot signal SP. μsec (= 1 / f
A phase error of P) is generated, and thereafter, the phase error is accumulated.

However, in the above-mentioned pilot servo, when the pilot servo is locked, since it is switched to the divided signal S44 synchronized with the pilot signal SP from the PLL 40 and the pilot servo is continued, the pilot signal SP is dropped out. Even if there is such a situation, a phase error does not occur in the divided signal S63 and the pilot servo is not adversely affected.

Moreover, the PLL 40 used at this time is
Originally, it is for forming the write clock of the TBC 13, and therefore the cost does not increase. That is, it is possible to realize a pilot servo that is resistant to dropout without increasing costs.

[0061]

By the way, in the above player, when reproducing the MUSE disc VD,
As long as the normal reproduction mode is continued, the frame phase of the reproduced video signal SMS seen from the MUSE decoder 1 is constant and does not change.

However, for example, when the reproduction mode is changed to the stop mode and then the reproduction mode is changed again, as described above, first, the FG servo is performed and then the pilot servo is performed. When
Video signal SMS reproduced from MUSE decoder 1
The frame phase of changes from the frame phase when the reproduction was performed last time.

That is, when the disc VD is a CLV disc, and 1 is changed from the stop mode to the reproduction mode, 2 is changed from the pause mode to the reproduction mode, 3 is changed from the search mode to the reproduction mode, 4 When the scan mode is changed to the reproduction mode, the frame phase of the video signal SMS reproduced from the disk VD is changed from the frame phase when the reproduction is performed before that. Further, even when the disc VD is a CAV disc, in the case of the above item 1, the frame phase also changes.

Even if the frame phase of the video signal SMS thus reproduced changes, if the correction range of the TBC 13 is more than ± 1 frame period, the TBC 13 changes the frame phase to the previous frame phase. It can be corrected and the MUSE decoder 1 can always be supplied with the video signal SMS having a constant frame phase.

However, in practice, due to cost reasons, the correction range of the TBC 13 (and 17) is, for example,
Since it is as small as 74 μsec pp (= 2.5 Hp-p. 1H is one horizontal period), if the frame phase change of the reproduced video signal SMS is large, the TBC 13 can completely correct the frame phase change. Can not.

Therefore, it is necessary to keep the frame phase of the video signal SMS supplied to the TBC 13 within several microseconds in accordance with the correction range of the TBC 13, but in such a case, in general, the disc The VD rotation speed is servo-controlled to suppress the frame phase of the reproduced video signal SMS within several microseconds.

That is, if the frame synchronization signal PBFM included in the video signal SMS reproduced from the disk VD is compared with the frame signal REFFM having the reference phase, and the comparison output is supplied to the spindle motor 21, reproduction is performed. The frame synchronization signal PBFM of the video signal SMS thus generated is within the correction range of the TBC 13 with respect to the reference frame signal REFFM.

Therefore, the video signal SMS having a constant frame phase based on the phase of the frame signal REFFM is set to M
It can be supplied to the USE decoder 1.

However, when the frame phase of the reproduced video signal SMS is controlled to be constant by the servo control as described above, the inertia of the disk VD is large,
By the time the rotation of the disk VD stabilizes, that is, TB
It takes several seconds until the frame phase of the video signal SMS supplied to C13 becomes stable.

The present invention is intended to solve such a problem.

[0071]

For this reason, in the present invention, when the reference numerals of the respective parts correspond to the embodiments described later, the video signal SMS of the television system of higher quality than the standard television system is recorded. Video disc VD
In the video disc player that reproduces the video signal, the phase difference θ between the frame signal PBFM of the video signal SMS reproduced from the video disc VD and the reference frame signal REFFM is measured, and the measured phase difference θ is improved to 1/2. Until the video disc VD is accelerated or decelerated until the phase difference θ becomes 1/2,
The acceleration or deceleration of the rotation of D is switched to the deceleration or acceleration, and when the rotation speed of the video disk VD returns to the original value by this switching, the deceleration or acceleration is stopped.

[0072]

When the video disk VD is in the normal reproduction mode, its rotation speed and rotation phase are quickly changed to the specified values by the open control, and the frame phase of the reproduced video signal converges to the reference phase in a short time. .

[0073]

1 and 2, 52 is a frame phase control circuit, 53 is a torque control circuit, and 54 is a current detection circuit.

During reproduction of the MUSE disc VD, the video signal SMS from the demodulation circuit 12 is supplied to the sync separation circuit 55 to extract the frame sync signal PBFM, and this signal PBFM is supplied to the phase control circuit 52. To be done. Further, in the signal forming circuit 57, a frame signal REFFM having a reference frequency and a frequency of fVM is formed.
Is supplied to the phase control circuit 52 as a reference signal.

The optical head 11 performs the track jump according to the above items 1 to 4, and when the last track jump is completed, the syscon 51 notifies the phase control circuit 52 of the completion of the track jump. .

Then, the phase control circuit 52 executes the forced acceleration / deceleration processing of the algorithm as shown in FIG. 4 for the rotation of the disk VD. That is, first, in step 101, it is checked whether or not the pilot servo is locked by checking the detection signal S68 of the detection circuit 68, and until it is locked,
That is, the process waits until S68 = "H".

Then, the pilot servo locks and S
When 68 = "H", in step 102, the reproduction frame synchronization signal PBFM and the reference phase frame signal REFFM
And the phase difference θ with is measured. Then, in step 103, it is checked whether or not | θ | ≦ 360 μsec (= 12 horizontal periods). When | θ |> 360 μsec, in step 104, It is checked whether the reproduction frame synchronization signal PBFM leads or lags the frame signal REFFM of the reference phase.

Then, when the reproduction frame synchronization signal PBFM is delayed with respect to the frame signal REFFM of the reference phase, in step 111, the rotation acceleration of the disk VD is started. That is, the acceleration signal ACCEL is formed, this signal ACCEL is supplied to the torque control circuit 53, and the drive voltage V53 in the acceleration direction is formed.
Is supplied to the spindle motor 21 through the adder circuit 33 and the drive circuit 34. Thus, the acceleration of rotation of the disk VD is started. Also, from the time of step 111, the pilot servo is prohibited.

Then, when the acceleration of the rotation of the disk VD is started, the phase difference θ gradually becomes smaller, but when the phase difference θ is improved to ½, this ½ point is the step 112. Detected in. When the time of 1/2 is detected, in step 113, the formation of the acceleration signal ACCEL is stopped and the deceleration signal BRK is formed, and this signal BRK is supplied to the torque control circuit 53 and the deceleration direction is supplied. Drive voltage V53 is generated, and this voltage V53 is supplied to the spindle motor 21 through the adder circuit 33 and the drive circuit 34. Thus, the disc V
The rotation deceleration of D is started.

When deceleration is started, the speed difference (frequency difference) between the reproduction frame synchronization signal PBFM and the frame signal REFFM of the reference phase approaches "0". It is detected in step 114. When this "0" time point is detected, step 11
At 5, the formation of the deceleration signal BRK is stopped and the drive voltage V53 in the deceleration direction is also not formed. In addition, the pilot servo is restarted.

Then, in step 102, the phase difference θ is checked again, and thereafter, the processes shown in steps 102 to 104 and 111 to 115 are executed until | θ | ≦ 360 μsec.

When the reproduced frame synchronization signal PBFM is ahead of the frame signal REFFM of the reference phase in step 104, the rotation speed of the disk VD is decelerated in step 121. That is, the deceleration signal BRK is formed, and this signal BRK is generated by the torque control circuit 5.
3 to form a drive voltage V53 in the deceleration direction, and this voltage V53 is added to the adder circuit 33 and the drive circuit 34.
Through the spindle motor 21. Thus, the deceleration of the rotation of the disk VD is started. Also, from the time of step 121, the pilot servo is prohibited.

When the deceleration of the rotation of the disk VD is started, the phase difference θ gradually becomes smaller. However, when the phase difference θ is improved to 1/2, the time point of 1/2 becomes step 122. Detected in. Then, when the time point of 1/2 is detected, in step 123, the formation of the deceleration signal BRK is stopped and the addition signal ACCEL is formed, and this signal ACCEL is supplied to the torque control circuit 53 to accelerate the vehicle. Drive voltage V53 is generated, and this voltage V53 is supplied to the spindle motor 21 through the adder circuit 33 and the drive circuit 34. Thus, the acceleration of rotation of the disk VD is started.

When the acceleration is started, the speed difference between the reproduction frame synchronization signal PBFM and the frame signal REFFM of the reference phase approaches "0", but this time "0" is detected in step 124. To be done. When the time "0" is detected, in step 125, the formation of the acceleration signal ACCEL is stopped and the drive voltage V53 in the acceleration direction is not formed. In addition, the pilot servo is restarted.

Then, in step 102, the phase difference θ is checked again, and thereafter, the processes shown in steps 102 to 104 and 121 to 125 are executed until | θ | ≦ 360 μsec.

By the above processing, the reproduction frame synchronization signal PBFM for the frame signal REFFM of the reference phase is obtained.
When the phase difference θ of is | θ | ≦ 360 μsec, step 1
As shown in 03, the above forced acceleration / deceleration processing is terminated,
After that, as shown in step 131, the fine adjustment mode is entered.

Since this fine adjustment mode is not the gist of the present invention, a detailed description thereof will be omitted, but the rotation speed of the disk VD is controlled by the pilot servo, and the reproduction frame synchronization signal is generated with respect to the frame signal REFFM of the reference phase.
Detect whether the phase difference of PBFM is advanced or delayed, and correct the pilot servo according to this detection result.
The condition of θ | ≦ 5 μsec is maintained.

Further, the above-mentioned forced acceleration / deceleration processing is performed by
Since it is executed in the case of item 4, the player is in the reproduction mode in the pilot servo state, but in this reproduction mode, | θ |> 27μ due to a scratch on the disk VD or the like.
When the second state continues for 0.5 seconds or more, the processing from step 101 is executed again. Further, the current detection circuit 54
Is for correcting the drive voltage V53 by detecting the magnitude of the drive current actually supplied to the motor 21.

Thus, according to the forced acceleration / deceleration processing of FIG. 4, the disc VD is reduced until the phase difference θ between the frame signal REFM of the reference phase and the reproduction frame synchronization signal PBFM becomes 1/2.
When the phase difference θ becomes 1/2, the rotation of the disk VD is decelerated (or accelerated) until the speed difference becomes 0. Therefore, this deceleration (or acceleration) is performed. ) Is completed, the video signal SMS reproduced from the disc VD can have a constant frame phase with the phase of the frame signal REFFM as a reference.

Moreover, at this time, the reproduced video signal S
The frame phase of the MS is first detected once by detecting the phase difference θ of the frame, and then controlled by the open control. Therefore, the operation is fast and the frame phase of the video signal SMS supplied to the TBC 13 in a short time. Can be stabilized.

Further, since the frame frequency of the reproduced video signal SMS matches the frame frequency of the reference signal REFFM and the phases of these signals also match, a transient may occur even when switching to the pilot servo. There is no.

When the phase difference θ between the reproduction frame synchronization signal PBFM and the reference frame signal REFFM is │θ│> 360 μsec in step 103, step 104
Since ~ 125 are repeated, even if there is an imbalance between the acceleration by the acceleration signal ACCEL and the deceleration by the deceleration signal BRK, the phases converge to the correct phase.

FIG. 5 shows an example of a circuit in which the circuit for executing the algorithm of the forced acceleration / deceleration processing of steps 101 to 125 in the phase control circuit 52 is constituted by a gate array. That is, in this figure, 521
Is a 1/2 divider circuit, 523 is a 12-bit up / down counter, 524 is a frequency or phase comparison circuit, 52
Reference numerals 5 and 526 are RS flip-flop circuits and 527 is a phase comparison circuit.

The reproduction frame synchronization signal PBFM from the sync separation circuit 55 and the frame signal REFFM of the reference phase from the formation circuit 57 are supplied to the phase comparison circuit 527 for phase comparison, and the phase of the reproduction frame synchronization signal PBFM is compared. Is "L" when is behind the reference frame signal REFFM, and is "H" when the phase of the playback frame synchronization signal PBFM is ahead of the reference frame signal REFFM.
DIR is taken out, and this signal DIR is sent to the switch circuit 71.
To 76 are supplied as their control signals, and the switch circuits 71 to 76, when DIR = “L”, are in the state shown in FIG.
When R = "H", the state is reversed to that shown in the figure.

Further, the output Q525 of the flip-flop circuit 525 is supplied to the switch circuits 81 and 82 as their control signals, and the switch circuits 81 and 82 have Q525 =
When "L", the state shown in the drawing is connected, and when Q525 = "H", the state opposite to that shown in the drawing is connected.

Now, as shown in FIGS. 6A and 6B, it is assumed that the phase of the reproduction frame synchronization signal PBFM lags behind the frame signal REFFM of the reference phase by θ. Then DIR
= “L”, the switch circuits 71 to 76 are connected in the state shown in the figure. Also, when the signal REFFM falls, t
Before 1, the flip-flop circuit 525 is reset and Q525 = “L”, so the switch circuits 81 and 82 are in the state shown in the figure.

Therefore, the frame signal REFFM of the reference phase from the forming circuit 57 is supplied to the reset input! R of the counter 523 through the switch circuit 73, and
As shown in FIG. 6B, at time t1, REFFM = “L”
Since the counter 523 is reset by this fall, the count value of the counter 523 becomes "0" at time t1 as shown in FIG. 6C.

At this time, the reference signal REFH2M having the frequency fHM / 2 from the forming circuit 57 is supplied to the frequency dividing circuit 521 and becomes a signal REFH4M having a frequency of 1/2, that is, a signal REFH4M having a frequency fHM / 4. This signal is divided by REFH4M
Is supplied to the up-count input! UP of the counter 523 through the switch circuit 81, and the down-count input! DN is set to "H" through the switch circuit 82. Therefore, as shown in FIG. 6C, the count value of the count 523 increases from "0" by "1" for each cycle of the signal REFH4M from the time t1.

The reproduction frame synchronization signal PBFM is supplied to the set input! S of the flip-flop circuit 525 through the switch circuit 74, and at the time point t2 when the phase difference θ has elapsed from the time point t1, PBFM = “L”. ”
And this fall causes the flip-flop circuit 5
25 is set. Therefore, from time t2, Q52
5 = “H”, and as shown in FIG. 6E, this signal Q525 is transmitted through the switch circuit 75 to the acceleration signal ACCE.
Output as L. Thus, from the time t2, the acceleration of the rotation of the disk VD is started, and the rotation speed thereof gradually increases.

When Q525 becomes "H" at the time point t2, the switch circuits 81 and 82 are connected in the state opposite to that shown in the figure, and the reference signal REFH2M is input to the up-counter of the counter 523 through the switch circuits 71 and 81! In addition to being supplied to UP, the frequency division signal S63 from the frequency division circuit 63 is supplied to the down count input! DN of the counter 523 through the switch circuits 72 and 82. That is, the counter 52
3, the reference signal REFH2M (frequency fHM /
2) is supplied as an upcount input,
The frequency-divided signal S63 (frequency fHM / 2) synchronized with the reproduction pilot signal SP is supplied as the down-count input.

Then, in this case, if the counter 523
If only the signal REFH2M (up-count input) is supplied to the counter 523, the carry output! CY is output from the counter 523 at the cycle corresponding to the frequency of the signal REFH2M and at the phase corresponding to the count value at the time point t2. Is output. If only the signal S63 (down count input) is supplied to the counter 523, the counter 52
From 3, the period corresponding to the frequency of the signal S63, and
The borrow output! BR is output in the phase corresponding to the count value at time t2.

Further, the counter 523 receives the signal REFH2M.
Even if both (up-count input) and signal S63 (down-count input) are supplied, if the frequencies of these signals are equal, the count value of the counter 523 does not change from the value at the time point t2.

However, in this case, since both signals REFH2M and S63 are supplied to the counter 523 and the rotation of the disk VD is accelerated by the signal ACCEL (= Q525), the frequency of the signal S63 is Higher than REFH2M frequency. Therefore, as shown after time t2 in FIG. 6C, the count value of the counter 523 gradually decreases, the count value becomes “0” at a time t3, and the borrow output! BR is output as shown in FIG. 6D. To be done.

In this case, the period f1 to t2 is the frequency fHM.
Since the signal REFH4M of / 4 is counted and the signals REFH2M and S63 of the frequency fHM / 2 are counted during the period t2 to t3, that is, the frequency fHM / 2 of the signal counted in the period t2 to t3 is equal to the period t1. Since it is twice the frequency fHM / 4 of the signal counted up to t2, at the time t3, the phase difference θ
Has been improved to 1/2.

When the borrow output! BR is output from the counter 523 at time t3, the flip-flop circuit 525 is reset by this borrow output! BR, and the time t3 is reached.
Therefore, Q525 becomes "L". Therefore, from time t3
Since ACCEL = “L”, the disk VD starts from time t3.
Acceleration is stopped. That is, the rotation of the disk VD is accelerated only during the period t2 to t3.

Then, the signal Q525 is supplied to the set input! S of the flip-flop circuit 526, and when Q525 becomes "L", the flip-flop circuit 526 is set and the output Q526 thereof is set as shown in FIG. 6F. "H"
And this signal Q526 is output to the switch circuit 7
It is output as a deceleration signal BRK through 6. Thus
From time t3, the deceleration of the rotation of the disk VD is started,
The rotation speed gradually decreases.

At this time, the reference signal REFH2M from the forming circuit 57 and the signal S63 are frequency-compared in the comparison circuit 524. When the frequencies of the two signals do not match, the signal becomes "H", and when they match, the signal becomes "L". A signal Q524 which becomes "" is taken out, and this signal Q524 is supplied to the reset input! R of the flip-flop circuit 525.

Therefore, when the speed difference between the signal REFH2M and the signal S63 becomes "0" at time t4, the frequencies of both signals match at this time, so that Q524 = "L" and the flip-flop circuit 526 is reset. Q526 = "L"
As a result, the deceleration signal BRK is not output from the time point t4 and the deceleration of the disk VD is stopped. That is, the rotation of the disk VD is decelerated only during the period t3 to t4.

On the other hand, when the phase relationship between the reference frame signal REFM and the reproduction frame synchronization signal PBFM is the opposite of the above, DIR = “H”, and therefore the switch circuit 71.
And, 76 is connected in a state opposite to that shown in the drawing. Therefore, the relationship between the signal REFFM and the signal PBFM and the relationship between the signal REFH2M and the signal S63 are opposite to the above, and the deceleration is executed in the periods t2 to t3 and the acceleration is executed in the periods t3 to t4.

In FIG. 7, in step 103, the reproduction frame synchronization signal PBFM and the reference phase frame signal REFFM are used.
When the phase difference θ with and is | θ |> 360 μsec, step 1
Phase control circuit 52 when 04 to 115 are repeated
Shows the operation of.

That is, as shown in FIG. 7A, the frame phase matching request signal XST1 becomes "L" at time t11 in accordance with the instruction from the system controller 51, and as a result, as shown in FIG. 7B, SQ1 at time t11. = “H”.

Then, as shown in FIG. 7C, SQ2 becomes “H” at time t12 in synchronization with the reference frame signal REFFM, and whether | θ | ≦ 360 μsec is satisfied during one cycle of the signal REFFM. Is detected. Then, when | θ |> 360 μsec, as shown in FIGS. 7C and 7D, at time t13, S
Q2 = "L" and SQ3 = "H".

Then, from the time t13 to the time t14, the phase difference θ
Is measured, and as shown in FIG. 7E, during the period t14 to t15, Q
525 = "H" (ACCEL = "H") and disk VD
Is accelerated, and then, as shown in FIG. 7F,
During the period from t15 to t16, Q526 is set to "H" (BRK = "H") to decelerate the rotation of the disk VD (time point t13,
t14, t15, and t16 are times t1, t2, t3, and t in FIG.
4 respectively).

Then, at the time point t16, Q526 becomes "L" and the deceleration is completed. Then, as shown in FIG.
Thus, the end signal ST2 is temporarily set to ST2 = "L", and this signal ST2 sets SQ1 = "L". In this way, one processing of steps 103, 104, 111 to 115 in FIG. 4 is completed.

Then, as shown in FIG. 7H, the start signal S
T2D is temporarily set to ST2D = "L", and this signal ST2D
Is set to SQ1 = "H" again at time t21, and the period t21-
At t26, a series of operations similar to those in the periods t11 to 16 are repeated.

Then, in the period t32 to t33, the phase difference θ becomes |
When it is detected that θ | ≦ 360 μsec, SQ7 = “H”, as shown in FIG. 7I, whereby the forced acceleration / deceleration mode is ended, and thereafter the fine adjustment mode is entered.

[0117]

The rotation of the disc VD is accelerated (or decelerated) until the phase difference θ between the frame signal REFM of the reference phase and the reproduction frame synchronization signal PBFM becomes 1/2, and the phase difference θ
When becomes 1/2, the rotation of the disk VD is decelerated (or accelerated) until the speed difference becomes 0.
When this deceleration (or acceleration) ends, the disk V
The video signal SMS reproduced from D is the frame signal REFF
It can be a constant frame phase based on the phase of M.

Moreover, at this time, the reproduced video signal S
The frame phase of the MS is first detected once by detecting the phase difference θ of the frame, and then controlled by the open control. Therefore, the operation is fast and the frame phase of the video signal SMS supplied to the TBC 13 in a short time. Can be stabilized.

Furthermore, since the frame frequency of the reproduced video signal SMS matches the frame frequency of the reference signal REFFM and the phases of these signals also match, transients may occur even when switching to the pilot servo. There is no.

If the phase difference θ between the reproduction frame synchronization signal PBFM and the reference frame signal REFFM is | θ |> 360 μsec in step 103, step 104
Since ~ 125 are repeated, even if there is an imbalance between the acceleration by the acceleration signal ACCEL and the deceleration by the deceleration signal BRK, the phases converge to the correct phase.

[Brief description of drawings]

FIG. 1 is a system diagram showing a part of an example of the present invention.

FIG. 2 is a system diagram showing a continuation of FIG.

FIG. 3 is a system diagram showing an example of a part of the present invention.

FIG. 4 is a flowchart showing an example of processing of the present invention.

FIG. 5 is a system diagram showing an example of a part of the present invention.

6 is a waveform diagram for explaining the operation of the circuit of FIG.

FIG. 7 is a waveform diagram for explaining the operation of FIG.

[Explanation of symbols]

 11 optical head 12 demodulation circuit 13 TBC 16 demodulation circuit 17 TBC 21 spindle motor 22 frequency generator 31 FG servo circuit 34 drive circuit 40 PLL 45 lock detection circuit 47 wideband bandpass filter 48 narrowband bandpass filter 51 system controller 52 frame phase Control circuit 53 Torque control circuit 54 Current detection circuit 55 Sync separation circuit 56 Sync separation circuit 57 Reference signal formation circuit 58 PLL 63 Frequency division circuit 65 Phase comparison circuit 67 Low pass filter 68 Lock detection circuit VD video disk

Claims (5)

[Claims] 1. A video disc player for reproducing a video disc recorded with a video signal of a television system of higher definition than a standard television system, wherein a frame signal of the video signal reproduced from the video disc and a reference signal The phase difference from the frame signal is measured, and the rotation of the video disk is accelerated or decelerated until the measured phase difference is reduced to 1/2. When the phase difference becomes 1/2, A video disc player in which acceleration or deceleration of rotation of a video disc is switched to deceleration or acceleration, and when the rotation speed of the video disc returns to the original value by this switching, the deceleration or acceleration is stopped. 2. A video disc player for reproducing a video disc recorded with a video signal of a television system of higher definition than a standard television system, wherein a frame signal of the video signal reproduced from the video disc and a reference signal During the period corresponding to the phase difference from the frame signal, the first and second reference frequencies are set in the up / down counter.
Signal is up-counted, and after the end of the above period, the acceleration or deceleration of the rotation of the video disc is started, and
A second signal having a frequency of 2 is supplied to the up / down counter as an up-count input or a down-count input. A signal equal to the frequency of the second signal is supplied to the up-down counter as a down-count input or an up-count input, and when the count value of the up-down counter reaches "0", rotation of the video disc is stopped. A video disc player that switches to deceleration or acceleration, and stops the deceleration or acceleration when the rotational speed of the video disc returns to the original level by this switching. 3. A video disc player for reproducing a video disc recorded with a video signal of a television system of higher definition than a standard television system, wherein a frame signal of the video signal reproduced from the video disc and a reference signal During the period corresponding to the phase difference from the frame signal, the first and second reference frequencies are
Signal is up-counted, and after the end of the above period, the acceleration or deceleration of the rotation of the video disc is started, and
A second signal having a frequency of 2 is supplied to the up / down counter as an up-count input or a down-count input, and at the same time as this supply, the second signal is synchronized with the sync signal included in the reproduction signal of the video disc, When the third signal equal to the frequency of the second signal is supplied to the up-down counter as a down-count input or an up-count input and the count value of the up-down counter becomes "0", the video disc Is switched to deceleration or acceleration, and the second signal and the third signal are compared in phase, and the phase difference between the second signal and the third signal falls within a predetermined range. At this time, a video disc player that stops the deceleration or acceleration. 4. A video disc player for reproducing a video disc recorded with a video signal of a television system of higher definition than a standard television system, wherein a frame signal of the video signal reproduced from the video disc and a reference signal The phase difference from the frame signal is measured, and the rotation of the video disk is accelerated or decelerated until the measured phase difference is reduced to 1/2. When the phase difference becomes 1/2, The acceleration or deceleration of the rotation of the video disc is switched to the deceleration or acceleration, and when the rotation speed of the video disc returns to a predetermined range by this switching, the deceleration or acceleration is stopped, and the phase difference measurement is decelerated. Alternatively, repeat the operation until the acceleration is stopped until the rotational speed of the video disc falls within a predetermined narrow range. Video disc player who has to Suyo. 5. A video disc player for reproducing a video disc recorded with a video signal of a television system of higher definition than a standard television system, wherein a frame signal of the video signal reproduced from the video disc and a reference signal During the period corresponding to the phase difference from the frame signal, the first and second reference frequencies are
Signal is up-counted, and after the end of the above period, the acceleration or deceleration of the rotation of the video disc is started, and
A second signal having a frequency of 2 is supplied to the up / down counter as an up-count input or a down-count input. A third signal equal to the frequency of the second signal is supplied to the up / down counter as a down count input or an up count input, and when the count value of the up / down counter becomes "0", the video disc Is switched to deceleration or acceleration, and the second signal and the third signal are compared in phase, and the phase difference between the second signal and the third signal falls within a predetermined range. When the deceleration or acceleration is stopped, the operation from the phase difference measurement to the deceleration or acceleration stop is described in the video above. A video disc player in which the rotation speed of the disc is repeated until it falls within a predetermined narrow range.