JPH01201782A - Picture recognizing device - Google Patents

Abstract

PURPOSE:To generate a histogram with a simple constitution by adding the content of a memory corresponding to a density of picture elements by one whenever picture element data are inputted. CONSTITUTION:The memory 101 corresponds to the number of gradations of 256 and has the addresses of 0-255. When data of 0-255 are inputted from an address bus 106 in correspondence with the gradations of a picture, the content of the corresponding address is read to a latch 102, inputted to an adder 103, added by one and stored again in the corresponding address in the memory 101. When the memory 101 is initially cleared, the histogram of the gradation is generated in the memory 101 when the input of picture data is terminated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image recognition device capable of capturing grayscale images from a camera.

[Summary of the Invention] The present invention provides an image recognition device capable of capturing grayscale images from a camera, which can perform binarization by compressing data into the number of occurrences of density values (hereinafter referred to as a density value histogram) in an arbitrary image area. The threshold value can be determined and the degree of blur can be recognized from the degree of contrast, and this can be achieved quickly by using hardware-based density value counting means.

[Prior Art] In counting density value histograms in a conventional image processing apparatus, a computer directly reads the density data of each pixel and decomposes it into histogram data for each density value.

[Problems to be Solved by the Invention] However, the above-mentioned conventional technology has a problem in that the speed of density value histogram processing depends on the processing speed of the computer, and high-speed processing is not possible.

Therefore, the present invention aims to solve these problems.
The purpose of this is to determine the binarization threshold by executing density value histogram processing at high speed,
The objective is to quickly recognize the degree of blur from the degree of contrast.

[Means for Solving the Problems] The image processing device of the present invention uses image data (density value data)
The present invention is characterized in that it has a counting means for counting the number of data (density value histogram) for each density value data by inputting the data to the address of the memory and adding 1 to the data indicated by the address.

[Operation] According to the above configuration of the present invention, when image data (density data) is applied in synchronization with the read/write signal of the memory, the data is read from the address corresponding to the density data, and +
It is incremented by 1 and stored at the same address. First, the memory is cleared, and when data for the entire required image area has been provided, the number of appearances of the density data is stored at the address corresponding to the density data, that is, the density value histogram is completed.

[Embodiment] FIG. 1 is a block diagram in an embodiment of the present invention. The usage procedure will be explained below.

As an example, it is assumed that this image processing device has a multi-value function of 256 gradations and can take data from 0 to 255.

First, data from address 0 to address 255 is initialized (cleared).

The 0 image data inputted to the address input of the memory 101 through the address bus 106 is density data. For example, if the density data at this time is 234, address 234 is indicated.

The memory 101 outputs the contents of address 234 to the data bus 104 according to the density data instruction.

Initially it is 0. Data bus 104 is connected to the input of latch 102, and the data is latched. The adder 103 normally has a function of adding +1, and the data at address 234 is added +1 to become l. However, while the data bus 104 is being output, the adder 103 is in high impedance. When the latch 102 latches data, the memory 101 becomes an input state, and the +
1 data is also output. When the data in the adder 103 becomes stable, it is written to the memory 101 and one cycle ends.

The image data of the entire arbitrary area is sent one after another to the address bus 10.
6, and when all input is completed, histogram data corresponding to the density value is completed in the memory.

If the data at address 234 is 12, this indicates that the data of the 234th gradation has appeared 12 times.

The image data may be data of the entire image memory, data of a partial area thereof, or data from a camera may be directly input.

FIG. 2 is a timing diagram of the memory 101 of FIG.

The timing of the address bus 106 is shown as 2ol, the timing of the data bus 104 is shown as 202, and the timing of the memory read/write clock is shown as 203.

Memory 101 serves as a clock 207 output, and 2
The 0 image data, which is inserted at 09 and finalized at timing 210, is finalized during 204, and here indicates address 234 of the memory 101. The content O at address 234 is output to data bus 104 at address 205. The latch 102 has a timing of 234 at a timing of 208.
Latch address data 0.

During 206, the data bus becomes an input, and the output of the adder 103 comes out. Even if there is a delay in the adder circuit, the data is finalized after a while, and the memory reads the data at timing 210.

Although this embodiment has been explained using a data bus type memory, the circuit configuration would be simpler if the data were separated into output and input.

The maximum value of the density value histogram is determined by the size of the image memory, and with the number of pixels of 256 x 256, 65,536 (assuming that all of them show normal density values), that is, a 16-bit memory is required. 512x512 requires 18 bits of memory. However, in reality, this does not happen, so we use memory that is easy to select from 16 bits to 8 bits, but in this case we use adder 1 for safety.
It is better to include an overflow function in 03 so that the value does not exceed -.

[Effects of the Invention] As described above, according to the present invention, the density value histogram of an image can be created at high speed with a simple circuit, and it is possible to determine the threshold value of the binarization level, judge the degree of blur based on contrast, etc. This has the advantage that it can be done at high speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the image recognition apparatus of the present invention, and FIG. 2 is a timing chart of the memory 101. 101, Memory 102, Latch 103, Adder (+1 and overflow function) 104, Data bus 105 of memory 101,...
Output 106 of latch 102, , address bus 201 of memory 101, .
, memory 101 address bus timing 202, memory 101 data bus timing 203, memory 101 click timing 204, image data determination section 205, memory output section 206,... Memory input section 207, memory output signal 208, latch timing 209 of latch 102,
,,Memory input signal 210, ,,Memory write timing or more Applicant Seiko Epson Corporation Patent attorney Tsutomu Mogami and 1 other person - 1 Kaya.

Claims (1)

[Claims] It is characterized by having a counting means for inputting image data (density value data) into an address of the memory and counting the number of data (density value histogram) for each density value data by adding 1 to the data indicated by the address. Image recognition device.