JPS61281382A - Character position information preparing circuit - Google Patents

Abstract

PURPOSE:To speed up the processing of a character recognizing device by preparing character position information for cutting out characters simultaneously with storing binarization image element information in a picture memory. CONSTITUTION:A character picture frame additional recording section 2 that OR stores binarization image element information consists of a shift register 21, an OR gate 22, a memory controlling circuit 23 and a character frame additional recording memory 24. The shift register 21 has the length of (n) bits, and the output obtained by OR of the binarization image data and the shift output of the shift register 21 in the OR gate 22 is inputted and cleared by writing pulse. The memory controlling circuit 23 writes the data of the shift register 21 in the character frame additional recording memory 24 by the writing pulse. For address to be written in the character frame additional recording memory 24, the forefront address is designated by a main controlling section, and controlled by the memory controlling circuit 23 to count up at every input of writing pulse.

Description

[Detailed Description of the Invention] [Summary] A pixel state detection unit that detects the existence of a pixel state indicating a character image in each main scan of binary pixel information input, and a pixel state detection unit that detects the presence of a pixel state indicating a character image during consecutive scans in which a character image exists. The system includes a character image frame appending section that stores the logical sum of input binary pixel information, and a position information storage section that records the start scanning position where the character image exists and the number of scans thereof. is stored in the image memory, and character position information is created at the same time, speeding up character extraction and improving the processing speed of the character recognition device.

[Industrial Field of Application] The present invention relates to a character recognition device, and more particularly to a character position information creation circuit that quickly creates positioning information for cutting out a character image area.

[Prior Art] Conventional character recognition devices estimate character positions from image information stored in an image memory based on a format definition body that stores character positions on a document in advance, and calculate the actual character positions. Recognition was performed by cutting out the character image part of 1 character.

[Problems to be Solved by the Invention] In the conventional method as described above, a considerable amount of time is required due to the position calculation related to cutting out and the tracking of the character image, and there is a limit to high-speed processing.

The present invention aims to solve these problems and provide a method for creating character position information at high speed.

[Means for Solving the Problems] FIG. 1 shows a block diagram of the principle of a character position information generating circuit according to the present invention.

In FIG. 1, reference numeral 1 denotes a pixel state detection section, which examines input binary pixel information and detects the presence of a pixel state indicating a character image within each unit scanning area.

That is, it is detected during each main scan whether there are "black" pixels representing a character image or whether all "white" pixels are present in one scan.

Reference numeral 2 denotes a character image frame appending unit, which inputs binary pixel information with the stored binary pixel information from one scanning cycle before while the pixel state detection unit 1 continues scanning in which a "black" pixel is detected. Iteratively ORing and re-storing is repeated.

Therefore, data of the maximum width of each character in the character line is recorded in the character image frame additional recording section.

Reference numeral 3 is a position information storage unit that stores the "additional recording start scan position" at which the additional recording is started after changing from the scan of all "white" pixels to the scan where "black" pixels exist, and the scan where "black" pixels exist. The consecutive "number of additional scans" is stored.

The operations of each of the above parts are common when a known image information storage section 4 quantizes and binarizes the scanned image signal of the scanner, and stores the binarized pixel information obtained by preprocessing in the image memory. The timing is controlled by the timing control circuit 5, and the data of "character frame additional recording information", "additional recording start scan position", and "number of additional recording scans" are formed at the same time as they are stored in the image memory.

[Operations] As explained above, the character position information creation circuit of the present invention simultaneously generates "character frame additional recording information" and "additional recording start scanning position" when storing input binarized pixel information in the image memory. and "number of additional scans" data is created.

Figure 2 shows "Character frame additional recording information" and "Additional recording start scanning position"
and “number of additional scans” are stored.

FIG. 2(a) shows binarized pixel information stored in the image memory. There are two character lines to be read, and the size in the main scanning direction is n bits.

FIG. 2(b) shows the stored "character frame additional information" data, and indicates the maximum width of each character in the i-th line and the i+1-th line using black data.

FIG. 2(c) shows the stored data of "additional recording start scanning position", and indicates that the character lines start from the ml-th and m2-th scanning, respectively.

FIG. 2(d) shows the stored "number of additional scans" data, in which the number of scans of a character line starting with ml is 1. , which indicates that the number of scans of the character line starting at m2 is 12.

Therefore, the "additional recording start scan position" and the "number of additional scans" indicate the position of the circumscribing frame of the character line to be recognized, and the "character frame additional information" indicates the position of the circumscribing frame of each character in the line. From these data, it is possible to immediately cut out each character one by one using its circumscribing frame.

In this manner, the present invention allows character frame information in which character images exist to be created extremely quickly.

[Example] The present invention will be explained in more detail below with reference to Examples shown in FIGS. 3 and 4.

FIG. 3 is a circuit diagram of an embodiment of the present invention, and FIG. 4 is a time chart showing its operation.

In FIG. 3, 4 is a known image information storage unit,
The image scanning analog signal input output from the COD of the scanner (photoelectric conversion section) is quantized by the quantization circuit 41 and converted into a 4-bit digital signal, which is then binarized and converted into a 4-bit digital signal.
The preprocessing circuit 42 performs preprocessing such as binarizing and removing high frequency components, and the serial/parallel conversion circuit 43 converts the data into, for example, 8-bit parallel data, which is then sent to the memory control circuit 44.
is stored in the image memory 45 under the control of.

The stored binary image data is used for recognition processing under the control of a main control section (not shown).

Reference numeral 1 denotes a pixel state detection unit that detects whether or not a pixel state indicating a character image exists in each unit scanning area, and includes flip-flops (FF■) 11, (FF■) 12 and A
ND gate (Al) 13, (A2) 14, (A
3) Consists of 15.

In the flip-flop (FF) 11, a binary image signal is input to its J terminal, and a scanning pulse is input to its K terminal, so that the Q output becomes "1" at the first black pixel in each main scan. , becomes a signal that is reset to "0" by the scanning pulse.

Flip-flop (FF■) 12 has a PF on its J terminal.
■The Q output of 11 is input, and the output of (A2) 14 is input to the K terminal (AND game described later), and as shown in the time chart of Fig. 4, the Q output becomes "1" at the first black pixel.
Therefore, all one scanning becomes a signal that is reset to "O'" by a white scanning pulse.

The Q output of FF 11 and the output of FF 12 are input to the ND gate (AI) 13, and as shown in the time chart in Fig. A pulse is generated at the black pixel of , which becomes a preset signal for the register 31 and counter 34, which will be described later.

The AND gate (A2) 14 has the Q output of FF12 and the FF.

■The output of 11 is input, and ■All scanning generates a pulse for the first scanning pulse of white, and each character position information memory 24
．． 33.36 is used as the write pulse.

AND gate (A3) 15 has scanning pulse and FP■
12 Q outputs are input, and the scan pulse is output during the continuation of the scan in which a black pixel exists (except for the first scan),
Used as a count pulse for counter 34.

Reference numeral 2 denotes a character image frame addition unit that stores the logical sum of binary pixel information input while the scans in which “black” pixels are detected are continuous, and includes a shift register 21, an OR gate 22, and a memory control circuit 23. , and a character frame additional recording memory 24.

The shift register 21 has a length of n bits, which is the quantization number for one main scan, and its shift input receives the output obtained by ORing the binary image data and the shift output of the shift register 21 using an OR gate 22. is input and cleared by a write pulse.

Therefore, during a scan in which a black pixel exists, the binary image signal is ORed with the signal from one scan period before, and at the end, the "1" bit indicates the maximum width of each character in the line. Become.

The memory control circuit 23 writes the data in the shift register 21 to the character frame additional memory 24 in response to a write pulse.

As the address to be written to the character frame append memory 24, the first address is specified by the main control section, and in the memory control circuit ■, each time a write pulse is input, = i+, '+
It is controlled to count up as = +i° + i+2°.

In addition, as shown in the time chart of Fig. 4, there is an example in which shift register data is written to each of n/8 memory groups in which n bits are divided into 8-bit units in correspondence with byte-configured memories. It shows.

3 is a position information storage unit that stores the additional recording start scanning position and the number of additional recording scans, and includes a register 31 and a memory control circuit.
32, additional recording start position memory 33, and counter 34
, a memory control circuit 35, and an additional scan number memory 36.

Register 31 contains the scan address and AND gate (A2)
14 output, and the scan address at that time is precented at the first black pixel after one scan of all white scans. This is the additional recording start scanning position.

The memory control circuit 32 writes the value of the register 31 to the additional recording start scanning position memory 33 at the timing of the write pulse.

The counter 34 is preset to a count value of "1" by the output pulse of the AND gate (AI) 13, and counts up by one by the output of the ND gate (A3) 15.

Here, the reason why the count value °1 is preset is because, as mentioned above, the first scanning pulse when a black pixel exists is not output from the AND gate (A3) 15, and thus the count value of the counter 34 is indicates the number of additional scans.

The memory control circuit (1) 35 writes the current count value of the counter 34 into the additional scan number memory 36 in response to a write pulse.

Additional recording start scan position memory 33 and additional scan number memory 3
The address to be written in No. 6 is the first address specified by the main control unit, and each address is memory-based. IDu road ■ and ■
For each write pulse input, "i',
It is controlled to count up as 'i+l°*' i+2°.

Additional recording start scan position memory 33 and additional scan number memory 3
The timing situation of data m19m2 and 12+, Q2, and addresses i and i'+1 of No. 6 is as shown in the time chart of FIG.

[Effects of the Invention] As explained above, according to the present invention, character position information for character segmentation is created at the same time as binarized pixel information is stored in the image memory, thereby speeding up the processing of the character recognition device. The effect of this change is extremely large.

[Brief explanation of drawings]

Figure 1 is a block diagram of the principle of the present invention. Figure 2 is a diagram showing the storage contents of character position information according to the present invention. Figure 3 is a circuit diagram of an embodiment of the present invention. Figure 4 is an embodiment of the present invention. This is a time chart. In the drawings, 1 is a pixel state detection unit, 2 is a character image frame addition unit, 3 is a position information storage unit, 4 is an image information storage unit, 5 is a timing control circuit, 11 and 12 are flip-flops, 13, 14.15 is an AND gate, 21 is a shift register, 22 is an OR gate, 2
3, 32.35 is a memory control circuit, 24 is a character frame additional memory, 31 is a register, 33
is an additional recording start scan position memory, 34 is a counter, 36 is an additional scan number memory, 41 is a quantization circuit, 42 is a binarization/preprocessing circuit, 43 is a serial/parallel conversion circuit, 44 is a memory control circuit, 45 is a image memory, respectively. leather twice

Claims (1)

[Scope of Claims] A pixel state detection unit (1) that detects the presence of a pixel state indicating a character image within a scanning unit area when inputting binarized pixel information that has been subjected to binarization processing and smoothing processing; , while the scanning unit in which the pixel state indicating the character image exists is continuous, the character image frame appending unit (2) stores the logical sum of the binary pixel information input, and the scanning unit in which the pixel state indicating the character image exists. a position information storage unit (3) for recording the starting scanning position of each successive unit and the number of consecutive scans; the image information storage unit (4) stores the binarized pixel information input in an image memory; A character position information creation circuit characterized in that the character position information creation circuit is configured to create character frame information circumscribing a character image at the same time.