JPH01200454A - Protection system for write to random access memory - Google Patents

Abstract

PURPOSE:To prevent the breakage of the memory contents due to a program debugging action by outputting an instruction which loads the memory contents in response to a program to an instruction identifying means when a CPU loads the program to a random access memory RAM. CONSTITUTION:When a CPU 1 loads a program to an RAM3-1 or 3-2, the CPU 1 outputs an instruction to a write protection circuit 4-1 or 4-2 in response to a program to load the contents of an external storage 6. The instruction identifying means of both circuits 4-1 and 4-2 set the contents of the memory 6 in response to the instruction given from the CPU 1. Thus the write enable and write unable areas are set in accordance with the program which is loaded in a program loading state. In case the address of the RAM to which the CPU 1 gave an access for writing is equal to an address stored in an area that is instructed to be turned into a write unable area by the information stored in the memory 6, the circuit 4-1 or 4-2 invalidates the access to said address.

Description

[Detailed Description of the Invention] [Industrial Field of Application] The present invention relates to random access memory in electronic computers.
The present invention relates to a write protection method for (RAM), and particularly to a random access memory write protection method that can prevent memory contents from being destroyed due to a program error.

[Conventional technology]

Traditionally, write protection for stored data, programs, etc.
Part of the address space is read-only memory (ROM)
2 and store non-rewritable data 2 programs in the ROM, or set a non-writable area in the RAM using software.

[Problem that the invention seeks to solve]

However, with the method of using ROM, it is not easy to change the memory contents, and when creating a program, it is difficult to use ROM.
Since the program must be created taking into consideration the address space allocated to the system, there is a problem that the degree of freedom of the system is low.

Furthermore, the software method has the problem that there are significant restrictions on the software, and data may easily be written to a write-inhibited area due to a program bug.

The present invention solves these problems, and its purpose is to provide a system with a high degree of freedom and to prevent memory contents from being destroyed by program bugs.

Means for Solving Problem C] In order to solve the above problems, the present invention provides a system including a random access memory and a CPU, in which each area of the random access memory is made a writable area. a storage means for storing information indicating whether the area is a write-inhibited area; an instruction identification means for determining the storage contents of the storage means in accordance with an instruction from the CPU; write protection means for disabling access when the accessed address of the random access memory is within an area that is instructed to be a write-inhibited area by information stored in the storage means; and when the CPU loads a program into the random access memory, the CPU outputs a command to the command identifying means to make the stored contents of the storage means correspond to the program to be loaded.

[For production]

When loading a program into the random access memory, the CPU outputs an instruction to make the stored contents of the storage means correspond to the program to be loaded.

The command identifying means determines the contents of the storage means according to the command from the CPU. Therefore, when loading the program,
A writable area and a writable area are set depending on the program to be loaded. In addition, since the instruction identification means changes the storage contents of the storage means according to the command from the CPU, even after the program is loaded, the storage contents of the storage means can be changed by adding an instruction from the CPU to the instruction identification means. can do. If the address of the random access memory accessed by the CPU for writing is within an area that is instructed to be a write-inhibited area by information stored in the storage means, the write protection means Disable access.

〔Example〕

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, in which the CPU
, memory usage status storage circuit 2, and RAM3-1.3-
2, write protection circuit 4-1.4-2, and abnormality detection circuit 5
-1.5-2, an external storage bag W6 in which a program to be loaded into the RAM 3-1.3-2 is stored, and a bus 7.

Note that the RAMs 3-1 and 3-2 have continuous address spaces.

The program stored in the external storage device 6 and loaded into the RAM 3-1.3-2 is stored in the external storage device 6 as a program load module file having the file structure shown in FIG. Program 22.23. Loaded into RAM3-1.3-2. 256 at the beginning of the program load module file that stores...
A byte header section 21 is provided, in which, in addition to the name of the module, the number of included programs, the name of each program, and each program 22.23. ... data/work area section 22-1.23-1. ... and program area section 22-2゜23-2. ... and the relative start address (each program 22, 23... is RA
Data/work area section 22-1.23-1 when loaded to M3-1.3-2. ...and program area section 22-2゜23-2. ...) is stored.

In addition, each data/work area section 22-1.23-1°... and program area section 22-2.23-2.・
... has a size that is an integral multiple of 256 bytes.

FIG. 3 is a block diagram showing an example of a write protection circuit 4-1 provided corresponding to the RAM 3-1, and includes an instruction identification circuit 41, an address selection circuit 42, flip-flops FFO to FFn, Antogame) ANDI ~AND
1B, OR gate ORI, OR2, and inverter IN
It is composed of I and IN2. The instruction identification circuit 41 sets its output signal S to "1" when a write-disable setting instruction is added from the CPU 1 via the bus 7, and sets its output signal r to "1" when a write-enable setting instruction is added.
”.The address selection circuit 42 is connected to the bus 7 from the CPUI.
When the address added via the address is 0 to FF in hexadecimal notation, only the signal aO is set to "1" among the output signals aO to an, and when it is from 100 to IFF, only the signal a1 is set to "1". When noO to nFF, only the signal an is set to 1''.

Flip-flop FF0=FFn sets RAM3-1 to 25
This is provided for each area when it is divided into areas of 6 bytes each, and if the corresponding area is a writable area, it is set to the reset state, and if it is a non-writable area, it is set to the set state. be done. Note that the write protection circuit 4-2 provided for RAM3-2 is also the write protection circuit 4-2.
It has the same configuration as 1.

Next, the operation of this embodiment will be explained.

When the power is turned on, CPIJI clears the memory usage status storage circuit 2 and sets the contents of each address to all "0", and also clears the flip-flops FFO to FFn and FFn provided in the write protection circuit 4-1. All the flip-flops provided in the write protection circuit 4-2 are reset.Flip-flop FF in the write protection circuit 4-1
To reset 0-FFn, a write enable setting command is output to the lotus 7, and the address to be output is expressed in hexadecimal, for example, 0.100, 200, etc. . . . This is done by incrementing by 100 addresses up to address nX100. As described above, the instruction identification circuit 41 sets the signal r to "L" when a write enable setting instruction is applied, and the address selection circuit 42 selects whether the applied address is 0~OFF, 100~
IFF, -5neo-nFF, signals ao, al
, -, an are set to "1", so by doing as described above, the flip-flops FFO to FFn
The signals applied to the reset terminals R of the flip-flops sequentially become "1", and the flip-flops FFO to FFn are put into a reset state. Further, the flip-flop in write protection circuit 4-2 is reset in the same manner.

Programs 22 and 23 stored in the external storage device 6
When loading ,... into RAM3-1.3-2, CP
The UI executes programs 22, 23, .・
The memory usage status storage circuit 2 stores information indicating the usage status of RAM3-1゜3-2 after loading (information indicating whether the data/work section or program area section is stored). to be memorized.

FIG. 4 shows the memory contents of the memory usage status storage circuit 2 and the RA
It is a diagram showing the usage status of M3-1.3-2 and its relationship with write protection. Each bit of the memory usage status storage circuit 2 is as follows: 50 bits in the 0th row are stored in 0-FF of the address space of RAM3-1.3-2, and 50 bits in the first row are stored in RAM3-FF.
It corresponds to each area when the address space of RAM3-1.3-2 is divided into areas of 256 bytes, such as corresponding to FOO-FFF of the address space of 1.3-2, and 1" indicates the program area and 0'' indicates the data/work area.

In the example in Figure 4, 0 to 7FF, COO to D in hexadecimal notation.
FF, 1000~IFFF, 2200~2FFF addresses (
800~BFF, EOO~F
This indicates that addresses FF and 2000 to 21FF become writable areas as data/work areas. As mentioned above, the flip-flops FFO to FFn in the write protection circuit 4-1 and the flip-flops in the write protection circuit 4-2 cover the address space of the RAM 3-1.3-2 by 256.
Since it corresponds to each area when divided into areas for each byte, each bit of the memory usage status storage circuit 2 has a one-to-one correspondence with the flip-flops in the write protection circuit 4-1 and 4-2. It turns out.

When the program loading is completed, the CPU 1 stores the states of the flip-flops FFO to FFn in the write protection circuit 4-1 and the flip-flops in the write protection circuit 4-2 to the corresponding bits of the memory usage status storage circuit 2. The content of “1”
If the value is "10", the state is set, and if the value is 10, the state is reset. The set of the flip-flop F F O” F F n in the write protection circuit 4-1 is connected to the bus 7.
The reset is performed by outputting a write disable setting command to the bus 7 and one of the addresses in the area corresponding to the flip-flop to be set (for example, the start address of the area). This is done by outputting a writable setting command to the flip-flop and outputting one of the addresses in the area corresponding to the flip-flop to be reset. As will become clear from the explanation that will be given later, the area corresponding to the flip-flop in the cent state becomes a writable area, and the area corresponding to the flip-flop in the reset state becomes a writable area.

That is, when loading the program, RAM3-1.3
The program area -2 is set as a non-writable area, and the data/work area is set as a writable area.

As mentioned above, when loading a program, RAM3-1
．． The program area of 3-2 is designated as a non-writable area,
The data/work area is set as a writable area, but for the data/work area where you want to make rewriting impossible, do the following. That is, the CPU 1 outputs a write-disable setting command according to a prepared program to the bus 7, and also outputs one of the addresses in the data/work area to be made write-disabled. As a result, a flip-flop corresponding to an area to be made unwritable is set, and that area is made a writable area, so that it is possible to prevent important data from being erroneously rewritten. Also, as described above, if you want to make an area that has been set as a non-writable area a writable area again, output a writable setting command to the bus 7 and output one of the addresses in the above area. Just do it.

Next, the CPU writes data to RAM3-1.
The operation when accessing 3-2 will be explained.

First, an explanation will be given of the operation when the CPUI attempts to write data to a write-disabled area. Now, for example, flip-flop FFO is set, and corresponding O to FF(1
When the area at the address (in hexadecimal notation) is set as a write-disabled area, the CPU attempts to write data to a certain address A within the area, and the read/write signal R/W is output as “
0'' and output data such as address A to bus 7.

When the address selection circuit 42 in the write protection circuit 4-1 is applied with the address A, the output signal aO is set to '1'', and the AND gate AND7.ANDIO is turned on. When /W becomes "0", AND13 and AND16 are turned on. At this time, the flip-flop FFO is in the seven-node state, and the Q and Q outputs are "1" and "0", respectively.
”, the output signals of OR gates OR1 and OR2 are “1” and “0”, respectively.OR gate OR
The output signal of 2 is sent to RAM3-1 via inverter rN2.
Since the read/write signal R/W applied to the RAM 3-1 becomes "1", the RAM 3-1 does not write data. In other words, the 0-FF address is write-protected.

The abnormality detection circuit 5-1 to which the output signal of the OR gate ORI is applied generates an interrupt to the CPUI when the output signal of the OR gate OR1 becomes "1". C
Upon occurrence of an interrupt from the abnormality detection circuit 5-1, the PUI monitor program considers the program to be abnormal, terminates the processing of the execution program, and performs failure recovery processing.

Next, the operation when the CPUI attempts to write data to the writable area will be explained. Now, for example, flip-flop FFI is put into the reset state and the corresponding 100-IF
When area F (in hexadecimal notation) is set as a writable area, the CPU attempts to write data to address A1 in the above area, and the read/write signal R/W is set to “
0'' and output data such as address A to bus 7.

When the address selection circuit 42 in the write protection circuit 4-1 is applied with the address A1, the output signal a1 is set to "1", and the AND gate AND8. Turn on ANDII. Also, when the read/write signal R/W becomes "0", the AND gate AND14. AND17 is turned on. At this time, the flip-flop FFI is in the recent state, and the Q and Q outputs are "O" and "O", respectively.
1", the output signals of OR gates ORI and OR2 become "0" and "l", respectively. OR gate O
The output signal of R2 is sent to RAM3- through inverter IN2.
Since the read/write signal R/W applied to the RAM 3-1 becomes "0", the RAM 3-1 writes the data added via the bus 7 to the address A.

In the above-described embodiment, the memory usage status storage circuit 2 stores information indicating the usage status of the RAM 3-1. Although the state of the flip-flops in the internal protection circuits 4-1 and 4-2 is controlled, the memory usage status storage circuit 2 does not store information indicating usage status.
It is also possible to control the states of the flip-flops in the write protection circuit 4-1, 4-2 at the time of program loading. However, as in this embodiment, by storing information indicating the usage status of RAM3-1.3-2 in the memory usage status storage circuit 2, the usage status of RAM3-1.3-2 can be easily checked. It becomes possible to know.

〔Effect of the invention〕

As explained above, the present invention provides storage means for storing information indicating whether each area of a RAM is a writable area or a writable area, and a CP that stores the storage contents of the storage means.
A writable area and a writable area can be set by outputting an instruction from the CPU when loading a program and at any arbitrary time. Unlike conventional examples that use ROM, there is no need to create a program taking into account the address space allocated to ROM.
Furthermore, since it is easy to change the program, there is an effect that the degree of freedom in the system can be increased compared to the conventional example using a ROM.

Further, the present invention provides that when the address of the RAM accessed by the CPU for writing is within an area that is instructed to be a write-inhibited area by information stored in the storage means, Since it is equipped with write protection means that disables access, it also has the effect of preventing memory contents from being destroyed due to programming errors.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is a diagram showing an example of the configuration of a program load module file, Fig. 3 is a block diagram showing an example of a write protection circuit, and - Fig. 4 is a memory Memory contents of usage status memory circuit and RAM
FIG. 3 is a diagram showing the usage status of and the relationship with write protection. In the figure, 1...CPU, 2...Memory usage status storage circuit, 3-1.3-2...RAM, 4-1.4-
2... Write protection circuit, 5-1.5-2... Abnormality detection circuit, 6... External storage device, 7... Bus, 21...
・Part of header, 22.23...Program, 22-1
, 23-1...data/work area section, 22-2
, 23-2...Program area section, 41...Instruction identification circuit, 42...Address selection circuit, FFO
= F F n...Flip-flop, AND 1~
AND18...and gate, ORI, OR2...
OR gate, INI, IN2...inverter.

Claims (1)

[Scope of Claims] In a system including a random access memory and a CPU, a memory that stores information indicating whether each area of the random access memory is a writable area or a writable area. means for determining the storage contents of the storage means according to an instruction from the CPU; and an address of the random access memory accessed by the CPU for writing is stored in the storage means. write protection means for disabling access if the address is in an area that is instructed to be a write-inhibited area by information contained in the memory; . A random access memory write protection system, characterized in that a command is output to the command identification means to make the storage contents of the storage means correspond to a program to be loaded.