JPH01198438A - Extrafine au alloy wire for bonding semiconductor devices - Google Patents

Extrafine au alloy wire for bonding semiconductor devices

Info

Publication number
JPH01198438A
JPH01198438A JP63022571A JP2257188A JPH01198438A JP H01198438 A JPH01198438 A JP H01198438A JP 63022571 A JP63022571 A JP 63022571A JP 2257188 A JP2257188 A JP 2257188A JP H01198438 A JPH01198438 A JP H01198438A
Authority
JP
Japan
Prior art keywords
loop
wire
bonding
extrafine
semiconductor devices
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP63022571A
Other languages
Japanese (ja)
Other versions
JP2621288B2 (en
Inventor
Juichi Hirasawa
平澤　寿一
Naoki Uchiyama
直樹 内山
Masayuki Tanaka
正幸 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Metal Corp
Original Assignee
Mitsubishi Metal Corp
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Filing date
Publication date
Application filed by Mitsubishi Metal Corp filed Critical Mitsubishi Metal Corp
Priority to JP63022571A priority Critical patent/JP2621288B2/en
Publication of JPH01198438A publication Critical patent/JPH01198438A/en
Application granted granted Critical
Publication of JP2621288B2 publication Critical patent/JP2621288B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • C—CHEMISTRY; METALLURGY
    • C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22C—ALLOYS
    • C22C5/00—Alloys based on noble metals
    • C22C5/02—Alloys based on gold
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0102—Calcium [Ca]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01031—Gallium [Ga]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01049—Indium [In]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01056—Barium [Ba]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01058—Cerium [Ce]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/011—Groups of the periodic table
    • H01L2924/01105—Rare earth metals

Abstract

PURPOSE:To obtain the title extrafine Au alloy wire having excellent strength at ordinary and high temp. and heat resistance by incorporating specified amts. of >=1 kind among Ce, Pr, Nd, and Sm, Si and/or Ag, and >=1 kind among Ba, In, Ge, and Ca into the wire. CONSTITUTION:The extrafine Au alloy wire for bonding semiconductor devices is formed from an Au alloy consisting of 0.2-50ppm of >=1 kind among the Ce-family rare-earth elements such as Ce, Pr, Nd, and Sm, 1-100ppm Si and/or Ag, 1-30ppm of >=1 kind among Be, In, Ga, and Ca, the balance Au, and inevitable impurities. In addition to the above-mentioned characteristics, the wire is capable of forming a stabilized high loop with reduced variance in height when a loop is formed. Furthermore, the wire is not deformed by the thermal effect in the bonding stage, and the loop twist formation by the thermal effect in the succeeding resin molding stage is suppressed.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、すぐれた常温および高温強度、並びにすぐ
れた耐熱性を有し、特に半導体装置の製造に際して、半
導体素子と外部リードとのボンディング（結線）に用い
た場合比、−段と高いループ高さを保ち、その高さのバ
ラツキも小さく、かつ変形ループや、樹脂モールドの際
のループ流れが小さく、さらに高温にさらされる環境下
でも素地中に分散する金属間化合物の成長が抑制され、
高い信頼性を確保することができるＡｕ合金極細線に関
するものである。Detailed Description of the Invention [Industrial Field of Application] The present invention has excellent room temperature and high temperature strength as well as excellent heat resistance, and is particularly suitable for bonding between semiconductor elements and external leads ( It maintains a much higher loop height than when used for wire connection (wire connection), has small variations in height, and has minimal deformed loops and loop flow during resin molding. The growth of intermetallic compounds dispersed in the material is suppressed,
The present invention relates to an Au alloy ultrafine wire that can ensure high reliability.

〔従来の技術〕[Conventional technology]

一般に、半導体装置の組立てに際しては、（ａ）　　ま
ず、ボンディングキャピラリーを通して供給されたＡｕ
またはＡｕ合金極細線の先端部を、電気的に、あるいは
水素炎などで加熱溶融してボールを形成し、 （ｂ）　　このボールを１５０〜３００℃の加熱状態に
おかれた半導体素子上の電極にキャピラリーで押し付け
て接合（ボールボンド）し、 （Ｃ）　　ついでキャピラリーをループを形成しながら
外部リード上に移動し、 （ｄ）　　キャピラリーを外部リード上に押し付けて、
ループの他端部をこれに接合（ウェッジボンド）し、 （ｅ）　　引続いて、極細線を挾んで上方に引張って、
これを切断する、 以上（ａ）〜（ｅ）の工程を一工程とし、これを繰り返
し行なうことによって、半導体素子と外部リードとをボ
ンディングすることが行なわれており、これには手動式
あるいは自動式ボンダーが用いられている。Generally, when assembling a semiconductor device, (a) first, Au is supplied through a bonding capillary.
Alternatively, the tip of an ultra-fine Au alloy wire is heated and melted electrically or with a hydrogen flame to form a ball, and (b) this ball is heated to 150 to 300°C as an electrode on a semiconductor element. (C) Then, move the capillary onto the external lead while forming a loop, (d) Press the capillary onto the external lead,
The other end of the loop is bonded to this (wedge bond), (e) Subsequently, the ultra-fine wire is pinched and pulled upward,
Cutting the semiconductor element and external leads are bonded by repeating steps (a) to (e) above as one step, and bonding is performed manually or automatically. A type bonder is used.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

一方、最近の半導体技術の進展によって、半導体装置の
高集積度化や組立ての高速化、さらに品種形状の多様化
や苛酷な条件下での使用を余儀なくされる傾向にあり、
これに伴ってボンディングの高速化や半導体装置の高密
度化とともにパッケージ形状の多様化が進行し、中には
配線距離が従来のものよりずっと長いデバイスや、極端
に短かいデバイスの組立てを高速でボンディングする必
要が生ずるようになってきたが、従来使用されている各
種の高純度Ａｕ極細線やＡｕ合金極細線では、ループ高
さに不足が生じたり、さらにループ高さのバラツキが大
きいために不安定なループの形成が避けられず、この結
果半導体素子のエツジと接触してエツジショートを起し
易く、さらに半導体装置が高温の苛酷な使用環境にさら
されると、極細線の例えばＡＩの電極材との接合界面に
おいて、素地中に分散する金属間化合物が急速に成長す
るようになり、このような金属間化合物の粗大化は信頼
性を著しく低下させるなどループに関する深刻な問題が
新たに発生するようになっているのが現状であり、した
がってループ高さが高く、その高さのバラツキも小さく
、かつ変形ループの形成もなく、さらに樹脂モールドの
際のループ流れが小さく、加えて金属間化合物の成長が
抑制されて、信頼性を一段と増した半導体素子ボンディ
ング用極細線の開発が強く望まれている。On the other hand, recent advances in semiconductor technology have resulted in semiconductor devices becoming more highly integrated, faster to assemble, becoming more diverse in product shape, and being used under harsher conditions.
Along with this, the speed of bonding has increased, the density of semiconductor devices has become higher, and package shapes have become more diverse. In some cases, devices with much longer wiring distances than conventional ones, and devices with extremely short wiring distances can be assembled at high speed. Bonding has become necessary, but the various high-purity Au ultra-fine wires and Au alloy ultra-fine wires that have been used conventionally have insufficient loop height or large variations in loop height. The formation of unstable loops is unavoidable, and as a result, it is easy to contact the edges of semiconductor elements and cause edge shorts.Furthermore, when semiconductor devices are exposed to harsh operating environments at high temperatures, ultra-thin wires such as AI electrodes At the bonding interface with materials, intermetallic compounds that are dispersed in the base material begin to grow rapidly, and the coarsening of these intermetallic compounds significantly reduces reliability, creating new serious loop-related problems. Currently, the loop height is high, the variation in height is small, there is no formation of deformed loops, the loop flow during resin molding is small, and the metal There is a strong desire to develop ultrafine wires for semiconductor device bonding that suppress the growth of compounds and further increase reliability.

〔課題を解決するための手段〕[Means to solve the problem]

そこで、本発明者等は、上述のような観点から、ボンデ
ィングの高速化、並びに半導体装置の高密度および多様
化に対応できる半導体素子ボンディング用極細線を開発
すべく研究を行なった結果、半導体素子ボンディング用
極細線を、Ｃｅ、Ｐｒ、Ｎｄ、およびＳｉからなるＣｅ
族希土類元素のうちの１種または２種以上：０．２〜５
０ｐｐａ＋　。Therefore, from the above-mentioned viewpoint, the present inventors conducted research to develop ultra-thin wires for bonding semiconductor devices that can increase the speed of bonding and cope with the high density and diversification of semiconductor devices. The bonding ultrafine wire is made of Ce, Pr, Nd, and Si.
One or more of group rare earth elements: 0.2 to 5
0ppa+.

ＳｉおよびＡｇのうちの１種または２種：１〜１１００
ｐｐ＋。One or two of Si and Ag: 1 to 1100
pp+.

Ｂｅ、Ｉｎ、Ｇｅ、およびＣａのうちの１種または２種
以上＝１〜３０ｐｐｍ　。One or more of Be, In, Ge, and Ca = 1 to 30 ppm.

を含有し、残りがＡｕと不可避不純物からなる組成を有
するＡｕ合金で構成すると、このＡｕ合金は、すぐれた
常温および高温強度、並びにすぐれた耐熱性をもつ一方
、ボンディングに際しては、高さが高く、シかも高さの
バラツキが小さい安に続く樹脂モ・−ルドの熱影響によ
るループ流れの発生を抑制することができるほか、高温
使用環境下においても金属間化合物の成長が著しく抑制
されるようになるという知見を得たのである。This Au alloy has excellent room temperature and high temperature strength as well as excellent heat resistance, but has a high height when bonding. In addition to suppressing the occurrence of loop flow due to thermal effects of the resin mold, the growth of intermetallic compounds is significantly suppressed even in high-temperature usage environments. We have obtained the knowledge that

この発明は、上記知見にもとづいてなされたものであっ
て、以下に成分組成を上記の通りに限定した理由を説明
する。This invention was made based on the above knowledge, and the reason why the component composition was limited as described above will be explained below.

（ａ）Ｃｅ族希土類元素 これらの成分には、極細線の常温および高温の強度、さ
らに耐熱性を向上せしめ、熱影響によるループの変形や
流れを防止する作用があるが、その含有量が０．２ｐｐ
ｍ未満では、前記作用に所望の効果が得られず、一方そ
の含有量が５０ｐｐｍを越えると、所望の高いループ高
さを確保することができなくなることから、その含有量
を０．２〜５０ｐｐａ＋（０，００００２〜０．００５
重二重量と定めた。(a) Ce group rare earth elements These components have the effect of improving the strength of ultrafine wires at room and high temperatures, as well as their heat resistance, and preventing loop deformation and flow due to heat effects. .2pp
If the content is less than 50 ppm, the desired effect cannot be obtained. On the other hand, if the content exceeds 50 ppm, it becomes impossible to secure the desired high loop height. (0,00002~0.005
It was defined as a double weight.

（ｂ）　　８１およびＡｇ これらの成分には、Ｃｅ族希土類元素との共存において
、極細線の軟化温度を高め、もってボンディング時の極
細線自体の強度低下並びに変形ループの発生を抑制する
作用があるが、その含有量が１　ｐｐａ＋未満では前記
作用に所望の効果が得られず、一方１１００ｐｐを越え
て含有させると、脆化して線引加工性が低下するように
なるばかりでなく、ボンディング時の加熱温度で結晶粒
界破断を起し易くなることから、その含有量を１〜１０
０１００ｐｐ、０００１〜０．０１重量％）と定めた。(b) 81 and Ag These components have the effect of increasing the softening temperature of the ultra-fine wire in coexistence with the Ce group rare earth element, thereby suppressing a decrease in the strength of the ultra-fine wire itself and the occurrence of deformation loops during bonding. However, if the content is less than 1 ppa+, the desired effect cannot be obtained, while if the content exceeds 1,100 pp, it not only becomes brittle and reduces the wire drawability, but also causes problems during bonding. Since grain boundary rupture is likely to occur at heating temperatures, the content should be set at 1 to 10.
0100pp, 0001 to 0.01% by weight).

（ｃ）Ｂｅ、ｉｎ、Ｇｅ、およびＣａ これらの成分には、Ｃｅ族希土類元素、Ｓｌ。(c) Be, in, Ge, and Ca These components include Ce group rare earth elements, Sl.

およびＡｇとの共存において、さらにループ高さを一段
と高め、かつループ高さのバラツキを小さくする作用が
あるほか、高温下における金属間化合物の成長を著しく
抑制する作用があるが、その含有量が１　ｐｐｍ未満で
は前記作用に所望の効果が得られず、一方その含有量が
３０ｐｐ−を越えると、脆化して線引加工性などが低下
するようになり、さらにボンディング時の加熱温度で結
晶粒破断を起し易くなることから、その含有量を１〜３
０ｐｐｍ（０，０Ｇ０１〜ｏ、ｏｏａ重量％）と定めた
。In coexistence with Ag and Ag, it has the effect of further increasing the loop height and reducing the variation in loop height, and also has the effect of significantly suppressing the growth of intermetallic compounds at high temperatures. If the content is less than 1 ppm, the desired effect cannot be obtained; on the other hand, if the content exceeds 30 ppm, the content becomes brittle and the wire drawability deteriorates, and furthermore, the heating temperature during bonding causes crystal grains to deteriorate. Since it becomes easier to break, the content should be reduced to 1 to 3.
It was determined to be 0 ppm (0,0G01-o, ooa weight %).

〔実　施　例〕〔Example〕

つぎに、この発明のＡｕ合金極細線を実施例により具体
的に説明する。Next, the Au alloy ultrafine wire of the present invention will be specifically explained using examples.

通常の溶解法によりそれぞれ第１表に示される成分組成
をもったＡｕ合金溶湯を調製し、鋳造した後、公知の溝
型圧延機を用いて圧延し、引続いて線引加工を行なうこ
とによって、直径：０．０２５１１■を有する本発明Ａ
ｕ合金極細線１〜２０および比較Ａｕ合金極細線１〜２
０をそれぞれ製造した。By preparing molten Au alloys having the compositions shown in Table 1 by a normal melting method, casting them, rolling them using a known groove rolling mill, and subsequently performing wire drawing. , diameter: 0.02511■ Invention A
U alloy ultrafine wires 1 to 20 and comparative Au alloy ultrafine wires 1 to 2
0 were produced respectively.

なお、比較Ａｕ合金極細線１〜２０は、いずれも構成成
分のうちの少なくともいずれかの成分を含有しないもの
である。Note that none of the comparative Au alloy ultrafine wires 1 to 20 contain at least one of the constituent components.

ついで、この結果得られた各種の極細線について、極細
線がボンディング時にさらされる条件に相当する条件、
すなわち温度：２５０℃に２０秒間保持した条件で高温
引張試験を行ない、それぞれ破断強度と伸びを測定した
。Next, for the various ultra-fine wires obtained as a result, conditions corresponding to the conditions to which the ultra-fine wires are exposed during bonding,
That is, a high-temperature tensile test was conducted at a temperature of 250° C. for 20 seconds, and the breaking strength and elongation were measured.

また、これらの極細線をボンディングワイヤとして用い
、高速自動ボンダーにてボンディングを行ない、ループ
高さ、ループ高さのバラツキ、ループ変形の有無、およ
び樹脂モールド後のループの流れ量を測定し、さらにボ
ンディング後のループのＡＩＩ電極材との接合部におけ
る金属間化合物層の厚みと剪断強度（接合強度）を測定
し、加えて樹脂モールド後の半導体装置（ＩＣ）につい
て、高温保持信頼性試験を行なった。これらの結果を第
２表に示した。In addition, using these ultra-thin wires as bonding wires, we performed bonding with a high-speed automatic bonder, measured the loop height, loop height variation, presence or absence of loop deformation, and the flow rate of the loop after resin molding. We measured the thickness and shear strength (joint strength) of the intermetallic compound layer at the joint between the loop and the AII electrode material after bonding, and also conducted a high temperature retention reliability test on the semiconductor device (IC) after resin molding. Ta. These results are shown in Table 2.

なお、ループ高さは、第１図に正面図で示されるように
、半導体素子Ｓと外部リードＬを極細線Ｗでボンディン
グした場合のｈをＺｌｌｈ測微計を用いて測定し、８０
個の測定値の平均値をもって表わし、ループ高さのバラ
ツキは、前記の８０個のループ高さ測定値より標準偏差
を求め、３σの値で表わし、この場合、実用的にはｈ：
２５０ＩＭ以上、バラツキ：３０ＩＩＩａ以下であるこ
とが要求される。The loop height is determined by measuring h using a Zllh micrometer when the semiconductor element S and the external lead L are bonded with a very thin wire W, as shown in the front view in FIG.
The variation in loop height is expressed by finding the standard deviation from the 80 loop height measurements mentioned above and expressing it by the value of 3σ. In this case, practically h:
It is required that it is 250 IM or more and the variation is 30 IIIa or less.

また、ループ変形の有無は、ボンディング後の結線Ｗを
顕微鏡を用いて観察し、第１図に点線で示されるように
結線Ｗが垂れ下がって半導体素子Ｓのエツジに接触（エ
ツジショート）している場合を「有」とし、接触してい
ない場合を「無」として判定した。In addition, the presence or absence of loop deformation can be determined by observing the wire connection W after bonding using a microscope, and as shown by the dotted line in FIG. 1, the wire connection W hangs down and contacts the edge of the semiconductor element S (edge short). If there was no contact, it was judged as "present", and if there was no contact, it was judged as "absent".

さらに、ループ流れ量は、樹脂モールド後の結線（細線
Ｗ）を直上からＸ線撮影し、゛この結果のＸ線写真にも
とづいて４つのコーナ一部における半導体素子と外部リ
ードのボンディング点を結んだ直線に対する結線の最大
膨量を測定し、これらの平均値をもって表わした。この
場合ループ流れ量としては、最大値で１００−まで許容
される。Furthermore, the loop flow rate was determined by taking an X-ray photograph of the connection (thin wire W) after resin molding from directly above, and connecting the bonding points of the semiconductor element and external lead at some of the four corners based on the resulting X-ray photograph. The maximum amount of expansion of the connection with respect to the diagonal line was measured, and the average value of these values was expressed. In this case, the maximum loop flow rate is allowed to be 100-.

また、金属間化合物層の厚みは、３００℃に１時間保持
の条件でベーキング処理を施した後の断面を研磨した状
態で測定し、剪断強度はシェアテストにより測定し、さ
らに高温保持信頼性試験は、ＩＣを２５０℃に５００時
間保持した後で、ループの抵抗値を測定し、高抵抗を示
すものや、断線しているものを不良とし、試験数：５０
個のうちの不良数を測定することにより行なった。この
場合、金属間化合物層の厚みは３−以下、接合強度は５
０ｇ以上が望まれ、かつ高温保持信頼性試験では５０個
の試験数のうち１個でも不良が発生すると信頼性の低い
ものとなる。In addition, the thickness of the intermetallic compound layer was measured by polishing the cross section after baking at 300°C for 1 hour, and the shear strength was measured by a shear test, followed by a high temperature retention reliability test. After holding the IC at 250°C for 500 hours, measure the resistance value of the loop, and those that show high resistance or are disconnected are considered defective.Number of tests: 50
This was done by measuring the number of defective items. In this case, the thickness of the intermetallic compound layer is 3-3 or less, and the bonding strength is 5
0 g or more is desired, and in the high temperature holding reliability test, if even one defective out of 50 tests occurs, the reliability will be low.

〔発明の効果〕〔Effect of the invention〕

第１表および第２表に示される結果から、本発明Ａｕ合
金極細線１〜２０は、いずれも高い高温強度を有し、ル
ープ高さが高く、かつそのバラツキもきわめて小さく、
またループ変形の発生がなく、ループ流れも著しく少な
く、シかもループは金属間化合物の成長が著しく抑制さ
れた状態で、きわめて高い接合強享を示し、かつ高温に
長時間加熱保持されても不良数の発生が皆無で信頼性の
著しく高いものであるのに対して、比較Ａｌ１合金極細
線１〜２０に見られるように、構成成分のすべてを含有
しないと、上記特性のすべてを満足して具備することが
できないことが明らかである。From the results shown in Tables 1 and 2, the Au alloy ultrafine wires 1 to 20 of the present invention all have high high temperature strength, high loop height, and extremely small variation.
In addition, there is no occurrence of loop deformation, there is extremely little loop flow, and the Shikamo loop exhibits extremely high bond strength with the growth of intermetallic compounds being significantly suppressed, and it does not fail even when heated at high temperatures for long periods of time. On the other hand, as seen in Comparative Al1 Alloy Ultrafine Wires 1 to 20, if all of the constituent components are not included, all of the above characteristics cannot be satisfied. It is clear that this is not possible.

性にもすぐれ、通常の半導体装置は勿論のこと、高密度
にして多様な半導体装置の組立てに際して、高速ボンデ
ィングを採用した場合にも、高さが高く、かつ高さのバ
ラツキも著しく小さいループを安定して形成することが
でき、さらにループの変形がほとんどないので、タブシ
ョートやエツジショートなどの不良発生が著しく抑制さ
れるほか、高温にさらされる使用環境下でも、特にルー
プの接合部における金属間化合物の粒成長が著しく抑制
されるので、ループが高抵抗を示したり、断線したりす
ることがなくなり、信頼性の著しく高いものとなるなど
工業上有用な特性を有するのである。It has excellent performance characteristics, and can be used not only for ordinary semiconductor devices but also for high-density and various semiconductor device assemblies, even when high-speed bonding is used. It can be formed stably, and there is almost no deformation of the loop, which significantly suppresses the occurrence of defects such as tab shorts and edge shorts. Since the grain growth of interlayer compounds is significantly suppressed, the loop does not show high resistance or break, resulting in extremely high reliability and other industrially useful properties.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図はボンディング状態を示す正面図である。 Ｓ・・・半導体素子、　　　　Ｌ・・・外部リード、Ｗ
・・・極細線。FIG. 1 is a front view showing the bonding state. S...Semiconductor element, L...External lead, W
...Extremely thin wire.

Claims (1)

【特許請求の範囲】[Claims] （１）Ｃｅ、Ｐｒ、Ｎｄ、およびＳｍからなるＣｅ族希
土類元素のうちの１種または２種以上：０．２〜５０ｐ
ｐｍ、 ＳｉおよびＡｇのうちの１種または２種：１〜１００ｐ
ｐｍ、 Ｂｅ、Ｉｎ、Ｇｅ、およびＣａのうちの１種または２種
以上：１〜３０ｐｐｍ、 を含有し、残りがＡｕと不可避不純物からなる組成を有
するＡｕ合金からなることを特徴とする半導体素子ボン
ディング用Ａｕ合金極細線。(1) One or more of the Ce group rare earth elements consisting of Ce, Pr, Nd, and Sm: 0.2 to 50p
pm, one or two of Si and Ag: 1 to 100p
pm, Be, In, Ge, and Ca: 1 to 30 ppm, and the remainder is Au and inevitable impurities. Au alloy ultra-fine wire for bonding.
JP63022571A 1988-02-02 1988-02-02 Au alloy extra fine wire for semiconductor element bonding Expired - Lifetime JP2621288B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63022571A JP2621288B2 (en) 1988-02-02 1988-02-02 Au alloy extra fine wire for semiconductor element bonding

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63022571A JP2621288B2 (en) 1988-02-02 1988-02-02 Au alloy extra fine wire for semiconductor element bonding

Publications (2)

Publication Number Publication Date
JPH01198438A true JPH01198438A (en) 1989-08-10
JP2621288B2 JP2621288B2 (en) 1997-06-18

Family

ID=12086563

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JP2621288B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5945065A (en) * 1996-07-31 1999-08-31 Tanaka Denshi Kogyo Method for wedge bonding using a gold alloy wire
WO2006078076A1 (en) * 2005-01-24 2006-07-27 Nippon Steel Corporation Gold wire for semiconductor device connection

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2773202B2 (en) 1989-03-24 1998-07-09 三菱マテリアル株式会社 Au alloy extra fine wire for semiconductor element bonding

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58154242A (en) * 1982-03-10 1983-09-13 Mitsubishi Metal Corp Fine wire of gold alloy for bonding semiconductor element
JPS6030158A (en) * 1983-07-29 1985-02-15 Sumitomo Metal Mining Co Ltd Bonding wire
JPS6179741A (en) * 1984-09-27 1986-04-23 Sumitomo Metal Mining Co Ltd Bonding wire

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58154242A (en) * 1982-03-10 1983-09-13 Mitsubishi Metal Corp Fine wire of gold alloy for bonding semiconductor element
JPS6030158A (en) * 1983-07-29 1985-02-15 Sumitomo Metal Mining Co Ltd Bonding wire
JPS6179741A (en) * 1984-09-27 1986-04-23 Sumitomo Metal Mining Co Ltd Bonding wire

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5945065A (en) * 1996-07-31 1999-08-31 Tanaka Denshi Kogyo Method for wedge bonding using a gold alloy wire
WO2006078076A1 (en) * 2005-01-24 2006-07-27 Nippon Steel Corporation Gold wire for semiconductor device connection
JP2006229202A (en) * 2005-01-24 2006-08-31 Nippon Steel Corp Gold wire for semiconductor device connection
US7830008B2 (en) 2005-01-24 2010-11-09 Nippon Steel Materials Co., Ltd. Gold wire for connecting semiconductor chip

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