JPH01197834A - Vram control circuit - Google Patents

Abstract

PURPOSE:To reduce a memory scale by outputting in parallel the data written in one single color area, as the output of each color, at the time of a single color display. CONSTITUTION:A single color area 2 stores single color display data, and a write control circuit 3 writes simultaneously display data of each color in plural VRAMs 1 corresponding to each color at the time of a multicolor display, and also, writes the data of a single color in one of plural single color areas 2 at the time of a single color display. A read-out control circuit 4 reads out the data written in the VRAMs 1 of each color at the time of a multicolor display and outputs them in parallel, and also, outputs in parallel the data written in one single color area 2, as the outputs of each color at the time of a single color display. In such a way, the VRAM in the single color display area can be allowed to have the same capacity as that for one color.

Description

[Detailed Description of the Invention] [Summary] Regarding a VRAM control circuit that can reduce the VRAM capacity when displaying a single-color window using a VRAM for multi-color display, the VRAM for a single-color area is the same as that for one color. The purpose of this invention is to provide a VRAM1# control circuit that can increase the capacity of a color display device that is equipped with a plurality of image memories (VRAM) corresponding to multicolor display and capable of displaying a single color window. A single color area is provided in each VRAM for color display, and when displaying multiple colors, display data for each color is simultaneously written to multiple VRAMs corresponding to each color, and when displaying a single color, data for a single color is written to multiple A write control circuit 3'11 writes to any of the single color areas, and when displaying multiple colors, reads out the data written to the VRAM of each color and outputs it in parallel, and when displaying a single color, writes to any of the single color areas. and a readout control circuit that outputs the data written in in parallel as an output for each color.

[Industrial application field]

The present invention relates to a circuit for controlling a dual-image memory (VRAM), and more particularly to a VRAM control circuit that can reduce the VRAM capacity when displaying a single color window using a VRAM for multicolor display.

In a color display device, a VRAM is used to perform multicolor display, but during multi-window display, a single color display may be performed in a certain window.

In this way, when displaying a single color window using a VRAM for multicolor display, it is desired to be able to reduce the VRAM capacity.

(Conventional technology) In conventional color display devices, R (red).

For each color information such as G (green), B (blue), ■ (luminance), etc., an independent system of VRAM is provided, and parallel/serial conversion is performed independently for display.

FIG. 7 is a diagram schematically showing the overall configuration of a color display device. In the figure, 11 is a central processing unit (CPU), which is connected to a read-only memory (RO) via a bus 12.
M) 1), random access memory (RAM) 14,
Display control times? r15, etc., and the overall operation is controlled by a program stored in the ROM1). At this time, data etc. are accumulated in the RAM 14 according to the operation of the CPU II. The display control circuit 15 has an internal VRAM, stores the image information received via the bus 12 in the VRAM, converts it into a display signal, and outputs it to the display 16.
The required image is displayed by q.

Figure 8 shows a conventional VRAM in a display control circuit.
21a shows a control method.

21b, 21c, and 21d are R, G, and B, respectively.

VRAM, 22a, 22b, 22c for (2).

22d are VRAMs 21a, 21b, 21c, 2, respectively.
This is a parallel/serial (P/S) conversion circuit that converts the output of 1d from parallel to serial.

Further, FIG. 9 shows the V RAM ft+ shown in FIG.
This figure shows the display data per display address in the 1779 system and the resulting display on both sides.

In the circuit shown in Fig. 8, when performing a display consisting of the three colors R, G, and B and luminance information l, each display address corresponds to the three colors and luminance, as shown in Fig. 9 (a). and simultaneously writes each data to its corresponding VRAM. At the time of reading, the data in each VRAM is read out in parallel and converted into serial signals in the respective P/S conversion circuits to produce respective outputs, thereby displaying an image as shown in Figure 9). be exposed. In other words, on both sides, red, green, blue, and brightness are displayed corresponding to R, G, B, and I data, respectively, so R, G, B, and r data are displayed for each dot. Multicolor image display can be performed by arbitrarily specifying the values.

[Problem to be solved by the invention]

In conventional color display devices, R, G, B.

Independent system V for each color information of 1st class
It had a RAM and was designed to perform independent parallel/serial conversion and display.

Therefore, when displaying a window in a single color during multi-window display, it is only necessary to indicate the presence or absence of pixels, so although one system of VRAM is sufficient for storage on both sides of the window, there are multiple VRAM of
Therefore, there is a problem in that the VRAM usage efficiency decreases.

The present invention is intended to solve the problems of the prior art, and it is an object of the present invention to provide a VRAM control circuit that can make a VRAM for a single color display AF region have the same capacity as that for one color. It is said that

[Means to solve the problem]

FIG. 1 shows the basic configuration of the present invention. In a color display device that is equipped with a plurality of VRAMIs corresponding to multicolor display and capable of displaying a window in a single color, each of the plurality of VRAMIs has a single one. In addition to providing a single color area 2,
It includes a write control circuit 3 and a read control circuit 4.

Single color area 2 is for storing single color display data.

The write control circuit 3 performs control to simultaneously write display data of each color to a plurality of VRAMIs corresponding to each color during multi-color display, and to write single-color data to any of a plurality of single-color areas 2 during single-color display. This is what we do.

When displaying multiple colors, the readout control circuit 4 controls the VRA of each color.
The data written in MI is read and output in parallel, and when displaying a single color, any single color area 2
This control performs control to output the data written in in parallel as output for each color.

[For production]

To reduce the circuit scale of a VRAM control circuit in a color display device which is equipped with a plurality of VRAMs corresponding to multicolor display and can also display a single color window.

Therefore, each of the plurality of VRAMs is provided with a single color area for displaying a single color, and a write control circuit is also provided.
When writing display data to VRAM, when performing multi-color display, display data for each color is simultaneously written to multiple VRAMs provided corresponding to each color, and when performing single-color display, single-color data is written simultaneously. to be written to one of multiple single-color areas. When the data in the VRAM is read and displayed, the data written in the VRAM for each color is read out and outputted in parallel to the display device, thereby performing multicolor display. Furthermore, when displaying a single color, data written in any single color area is read out and outputted in parallel as outputs of each color, thereby performing a single color display.

In the present invention, when performing a single-color window display, any m-color area is used without using multiple VRAMs for multi-colors, so the VRAM for single-color display is
M capacity is 1/number of colors, so VRAM capacity can be reduced.

〔Example〕

FIG. 2 is a diagram showing an embodiment of the present invention, in which R, G,
The case of a color display device with three colors B and luminance I is illustrated, and 3
1a to 31d are VRAMs for multicolor display, and 32 is a VRAM for single color display. Portions corresponding to each color and brightness I in VRAM32 (R), (G), (B),
(1) is a VRAM 31a-3 for multicolor display, respectively.
It is provided in a part of 1d. 33 is an address decoder, 34 and 35 are write control circuits and read control circuits each operated by a gate signal of the address decoder 33, and 36a to 36d are parallel/serial conversion circuits.

Further, FIG. 3 is a diagram showing display data per display address in the embodiment shown in FIG. 2 during multi-color display and single-color display.

Address decoder 33 generates a gate signal according to the display address to control write control circuit 34 and read control circuit 35. Display data R, G when displaying multiple colors
, B, and T are sent to the VRAM 318 through the write control circuit 34, as in the case of the conventional example shown in FIG.
-31d and are read independently, thereby producing outputs of R, G, B, and I data. The display data in this case is the same as in the conventional example, as shown in FIG. 3(8).

When displaying a single color, the write control circuit 34 transfers the display data R, ('',, Fl, T to the VRA for medium-color display.
Control is performed to write in the R, G, B, and I areas of M32, respectively. In this case, R in the VRAM32,
G, +1. In each area of T, only l systems are written for one dot. In other words, each data of RO, GO, 80, and 10 is written to each VRAM at the same address in the case of multicolor display, but in the case of single color display, they are written to separate addresses, and the write data per display address is written to each VRAM. Limit to 4 dots. Also, when reading, VRAM
If there is data in any of R, G, B, and I in 32, the read control circuit 35 performs control so that the input data is present in all of the P/S conversion circuits 36a to 36d. In FIG. 3(h), display data RO, G
It is shown that o, BO, and To are written in the R, G, B, and I areas of the VRAM 32 as data of 1 bit per 1 dot to produce an output.

In any case, each output of R, G, B, and I is P/S.
It is converted into a series signal through conversion circuits 36a to 36d, producing an output of 4 dots per display address. The display for each dot is generated corresponding to R, G, B, and T data in the case of multicolor display, and R, G, and B in the case of single color display.

■By simultaneously producing output in a single color (white).

black).

Therefore, in the embodiment shown in FIG. 2, when displaying a single color, VR
AM capacity is 1/number of colors + brightness, VR for one color
All that is required is the capacity of AM.

FIG. 4 shows an example of the configuration of the write control circuit 34, in which 33 is an address decoder, 61 to G4 . G6～
G9 is the gate, G5. G20 to G23 are OR circuits.

Further, FIG. 5 shows the relationship between addresses and gate signal outputs in the address decoder.

The address decoder 33 generates gate signals SO to S4 as shown in FIG. 5 based on the lower order al''a1g of display addresses a0 to a16 given from the CPU.

During multi-color display, G)06 to G9 are all turned off, and G)G1 to G4 are all turned on, so that display data R, G, B, and T are transmitted to the output side, respectively.
As described above, the data are written to the VRAMs 31a to 31d, respectively. When displaying a single color, all gates G1 to G4 are turned off, and gate signals 81 to S4 are applied to gates G1 to G9.
One of them is turned on depending on the Display data is R,G.

When either B or ■ is output, it is applied to the gates G6 to G9 via the OR circuit G5, and written to the corresponding page area in the VRAM 32 via the gates that are turned on according to the gate signals 81 to S4. . At this time, using the gate signals SO to S4 from the address decoder 33, each VRAM 31a to
31 Write enable signals WER, WEc for d
, WEs.

WE generates. The timing of each signal in this case is
It is created by gating the signal 5l-34, which is synchronized with the input timing of data R, G, B, and I, with a multicolor or monochrome identification signal SO.

FIG. 6 shows an example of the configuration of the readout control circuit 35.
0-Gl 3. Gl 5 to G18, 019 to G22 are gates, and ■ is an inverter.

During multicolor display, the gates G15 to G1B are activated by the signal SO.
are all turned on, and the gates G19 to G are turned on by the signal SO.
22 are all turned off, and VRAM31a to 31d
R, G, B, and T data are output respectively.

During single color display, gates 015 to G18 are all turned off, gates 019 to G22 are all turned on, and when any one of gates 1-GlO-G1) is turned on by signals 31-34, R, G.

Output is generated at all numbers B and I. In this case R2O,
By producing or not producing output in all of B and I, inner or black dots are displayed on both sides.

In this circuit, gates G15-018. G19~G2
2, it should also be able to adjust impedance.

〔Effect of the invention〕

As explained above, according to the present invention, when a single color display is performed in a multicolor display circuit, a single color display area,
Compared to the conventional case, the VRAM can be reduced to 1/number of colors + brightness, which is effective in reducing the memory size.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing the basic configuration of the present invention, Fig. 2 is a diagram showing the configuration of an embodiment of the invention, and Fig. 3 is a diagram showing display data per display address in the embodiment of Fig. 2. Figure 4 is a diagram showing an example of the configuration of the write control circuit, Figure 5 is a diagram showing input/output signals of the address decoder, Figure 6 is a diagram showing an example of the configuration of the read control circuit, and Figure 7 is a color display. FIG. 8 is a diagram showing an outline of the overall configuration of the device; FIG. 8 is a diagram showing a conventional VRAM control method; FIG. 9 is a diagram showing display data per display address and its image display in the VRAM control method of FIG. 8. It is a diagram. 31a to 31d, 32-image memory (VRA
M) 33...Address decoder 34...Write control circuit 35...Read control circuit 36a-36d...Parallel/serial (P/S) variable IQ circuit Patent applicant Fujitsu Ltd. Agent Patent attorney Figure 1 shows the basic structure of the present invention. jfIl; FIG. 3 shows a display table per one display address δ in the embodiment of the mask FIG. 2 according to the display address. GIS-G18. G19-G22-・
・Gate I... Whistle 6 diagram showing an example of the configuration of an inverter readout control circuit Diagram 6 diagram showing the overall configuration of a color display device

Claims (1)

[Claims] A plurality of image memories (hereinafter referred to as VRAM) correspond to multicolor display.
In a color display device equipped with (1) and capable of displaying a single-color window, each of the plurality of VRAMs (1) is provided with a single-color area (2) for displaying a single color, and when displaying multiple colors, , the display data of each color is simultaneously written to a plurality of VRAMs (1) corresponding to each color, and when displaying a single color, the data of a single color is written to the plurality of single color areas (
A write control circuit (3) that writes data to one of the above-mentioned VRAMs (2) and, when displaying multiple colors, reads out the data written in the VRAM (1) of each color and outputs it in parallel, and when displaying a single color, reads the data written to the VRAM (1) of each color and outputs the data in parallel. A VRAM control circuit comprising: a readout control circuit (4) that outputs data written in the area (2) in parallel as outputs for each color.