JPH0119655B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Description of the Technical Field] The present invention relates to a clock generation circuit suitable for a commonly controlled switching device. In particular, the present invention relates to a clock generation circuit that specifies the order of commonly used circuits.

[Description of prior art]

If a plurality of communication paths, etc. in a communication device are provided with common functions, providing a common function circuit for each communication path on a one-to-one basis will make the device expensive. Therefore, it is necessary to use these common function circuits by concentrating them in a number that corresponds to the traffic. If the number of common function circuits is n, it is necessary that each communication channel can access n common function circuits.

For this reason, conventionally, a multi-stage shift register circuit 1 as shown in FIG. 1 is used to determine in advance the order in which n common function circuits are used. That is, the output terminals of the shift register circuit 1 are connected to the order designation input terminals of n identical common function circuits, and the output terminal of the last stage of the shift register circuit 1 is connected to the data input terminal of this shift register circuit 1. let them return. As a result, a clock signal is inputted to the clock terminal CK of the shift register circuit 1, and designated clock signals as shown in FIG. 2 are sequentially generated.

However, each output terminal of shift register circuit 1
When CP ₁ to CP _o are connected to each common function circuit,
The common function circuits are always used in a fixed order. Therefore, shift register circuit 1
Since the common function circuit connected to the output terminal of the subsequent stage has a low priority, it becomes difficult to use even if it is not used when the amount of traffic is small.

Further, if a common function circuit with a high priority becomes a failure, this common function circuit continues to be accessed, and the communication path cannot complete its operation.

[Object of the present invention] The present invention improves this point, and an object thereof is to provide a selection clock generation circuit that can generate a plurality of usage orders for common function circuits from the communication path side.

[Summary of the invention]

The present invention provides a first multistage shift register circuit for transmitting a reference priority signal, the output terminals of which are respectively connected to the input terminals of a NAND circuit, and the output of this NAND circuit is connected to its data input terminal; A second multi-stage shift register circuit in which the output of the final stage of the multi-stage shift register circuit is connected to the clock signal input terminal, and the output of the first multi-stage shift register circuit is input, and the arrangement order of the inputs is the control terminal. A data select circuit that is inverted according to the input and output as an output clock signal, and a data select circuit that is reset by the output of the first stage of the second shift register circuit and set by the output of the intermediate stage, and is sent to the control terminal of the data select circuit. It is characterized by comprising a flip-flop circuit to which the output is input.

[Explanation of Examples]

An embodiment of the present invention will be described based on the drawings.

FIG. 3 is a block diagram of essential parts of an embodiment of the present invention. A reference clock CLK is led to the clock terminal CK of the first multi-stage shift register circuit 2. The outputs of this multi-stage shift register circuit 2 are respectively led to input terminals of a NAND circuit 3, and the output of this NAND circuit 3 is led to a data input terminal D of this multi-stage shift register circuit 2. Further, the output of the final stage of this multi-stage shift register circuit 2 is sent to the clock terminal of the second multi-stage shift register circuit 5.
Guided by CK. The output of the final stage of this multistage shift register circuit 5 is led to a data input terminal D.

The output φ ₁ of the first stage of the multi-stage shift register circuit 5 is led to the reset terminal R of the flip-flop circuit 6, and the output φ ₁₁ of the eleventh stage is led to the set terminal S of the flip-flop circuit 6. Output terminals Q and F of flip-flop circuit 6 are led to control terminals B and A of data select circuit 7, respectively. Further, the outputs of the second stage, third stage, fifth stage, and sixth stage of the multistage shift register circuit 2 are led to input terminals X ₁ to X ₄ of the data select circuit 7, respectively. Further, the outputs of the sixth stage, fifth stage, third stage, and second stage of the multistage shift register circuit 2 are led to input terminals Y ₁ to _{Y 4} of the data select circuit 7, respectively. The output of the data select circuit 7 and the output of the fourth stage of the multi-stage shift register circuit 2 are respectively led to output terminals that output rank designation pulses CP ₁ to CP ₅ .

FIG. 4 is an operation time chart showing the output waveform at the points indicated by the x marks in FIG. That is,
φ ₁ to _{φ 20} are output signals of the multistage shift register circuit 5,
CP ₁ to CP ₅ indicate output signals of the data select circuit 7, respectively.

In such a circuit configuration, output signals are sent out from each output terminal of the multi-stage shift register circuit 2 at the timing shown in FIG. Further, since the output of the final stage of this multi-stage shift register circuit 2 is given as a clock signal to the multi-stage shift register circuit 5, each output terminal of this multi-stage shift register circuit 5 outputs an output signal φ at the timing shown in FIG. ₁
~ _φ20 are sent out respectively. Further, the flip-flop circuit 6 is reset by the output of the first stage of the multi-stage shift register circuit 5, and the control terminal A of the data select circuit 7 becomes high level. This allows input terminals X ₁ to
The input of X ₄ is output. This state continues until the flip-flop circuit 6 is set, and the order specifying pulses CP ₁ to _{CP 5} shown at α in FIG. 4 are output.

Further, when the output _φ11 of the 11th stage of the multi-stage shift register circuit 5 becomes high level, the flip-flop circuit 6 is set. As a result, the control terminal B of the data select circuit 7 becomes high level, and the inputs from the input terminals _Y1 to _Y4 are output. This state continues until the flip-flop circuit 6 is reset, and the order designation pulse shown at β in FIG.
CP ₁ to CP ₅ are output.

[Explanation of effects]

As explained above, according to the present invention, a reference priority output signal is led to a select circuit, and a plurality of sets of priority clocks are outputted via this select circuit.

Therefore, the priority clock that indicates the priority can be automatically changed. Therefore, it is possible to automatically generate multiple usage orders for common function circuits from the communication path side, and even if a common function circuit with a high priority fails, it will continue to be accessed and the communication path will be considered incomplete. It has the effect of being able to prevent such phenomena.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the main circuit configuration of a conventional example. Figure 2 is an operation time chart of Figure 1. FIG. 3 is a diagram showing the main circuit configuration of an embodiment of the present invention. FIG. 4 is an operation time chart showing the output waveform at the points marked with an x in FIG. 3. 1, 2, 5...Multi-stage shift register circuit, 3...
...NAND circuit, 6...Flip-flop circuit, 7
...Data selection circuit.

Claims (1)

[Claims] 1. A first multi-stage shift register circuit for transmitting a reference priority signal, the output terminals of which are respectively connected to the input terminals of a NAND circuit, and the output of the NAND circuit is connected to its data input terminal; a second multi-stage shift register circuit in which the output of the final stage of the first multi-stage shift register circuit is connected to the clock signal input terminal, respectively; and the output of the first multi-stage shift register circuit is inputted, and the inputs are arranged in the order of arrangement. a data select circuit which is inverted according to a control terminal input and outputted as an output clock signal; and a data select circuit which is reset by the output of the first stage of the second shift register circuit and set by the output of the intermediate stage, and which controls the data select circuit. 1. A selection clock generation circuit comprising a flip-flop circuit whose output is input to a terminal.