JPH01195321A - Digital position detecting system - Google Patents

Abstract

PURPOSE:To stably and at a low cost execute a position detection, and also, to obtain a speed data as a digital data by constituting a digital phase comparator, a pulse gate, an up-down counter, a differentiator and a conversion table, a digital element. CONSTITUTION:An output of a ring counter 10 which uses a crystal oscillator as an original oscillation is inputted to an adder 9 and a 2-phase exciter 12. A sine wave signal and a cosine wave signal from the exciter 12 excite a resolver 1, and a rotating magnetic field is generated in the resolver 1. An output signal from the resolver 1 passes through a waveform shaping device 2 and inputted to a digital phase comparator 3. The comparator 3 compares it with a reference signal S from the adder 9 and a sends out a shifted phase portion pulse width T to a pulse gate 4. By a clock pulse CP outputted by the gate 4, up-down counters 5, 6 are driven. An output A of the counter 5 is utilized as a digital position output. Also, the counter 6 is reset by a differential waveform of the reference signal S, and an output B of the counter 6 becomes a digital speed data by a conversion table 8.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital position detection method, and more particularly to a digital position detection method for a position detector such as a resolver using a phase modulation signal.

[Conventional technology]

An example of a position detection method including a conventional phase difference tracking control system is shown in FIG. 5 and will be described.

In the figure, 21 is a resolver, 22 is this resolver 21
23 is an analog phase comparator, 24 is a low-pass filter, 25 is a voltage frequency converter, 26 is an up/down counter, 27 is an adder, 28 is a ring counter, and 29 is a crystal. Oscillator, 30 is 2
It is a phase exciter. Further, θ is the rotation angle of the resolver 21 from the reference position.

Next, the operation will be explained.

First, the output signal from the resolver 21 is shaped into a rectangular wave by the waveform shaper 22, and then input to the analog phase comparator 23, where the phase is compared with the reference signal from the adder 2T, and the phase difference between the two is converted into an analog voltage. converted.

Next, this analog voltage is input to the voltage frequency converter 25 through the low pass filter 24.

Then, depending on the magnitude of this input voltage, the voltage frequency converter 25 converts it into a pulse train, and the up/down counter 26
The pulse train is counted and digital position data is output.

On the other hand, the low-pass filter 24 outputs an analog speed signal.

[Problem to be solved by the invention]

The conventional position detection method described above includes analog sliding elements in its control loop, which causes the control system to become unstable due to drift and element variations, and increases costs due to the use of high-precision parts. Ash, LSI again
There was also the problem that it became an obstacle to the implementation of the system. Furthermore, with the spread of microprocessors in recent years, si-digital processing has become mainstream, and the inclusion of analog systems has been an obstacle when interfacing with microprocessors.

[Means to solve the problem]

The digital position detection method of the present invention includes a control system that changes the phase of the reference signal based on the phase difference between the output signal from the position detector using a phase modulation signal and the reference signal to follow the phase of the output signal. In the position detection method, there is a digital phase comparator that compares the phase of the output signal from the position detector and the phase of the reference signal, a pulse gate that uses the output of this digital phase comparator to turn on and off a pulse train, and from this pulse gate. The first to count the output pulse train of
a second up-down counter that counts and holds the output pulse train from the pulse gate; a differentiator that generates a signal to reset the second up-down counter at the edge of the reference signal; It has a conversion table for converting the data from the 7-up down counter of No. 2 into speed data.

[Effect]

In the present invention, the phase of the output signal from the position detector using a phase modulation signal is compared with the phase of the reference signal, and the output pulse train from the pulse gate is used to turn on and off the pulse train. A second up-down counter that counts and holds the output pulse train from the pulse gate is reset at the edge of the reference signal, and the data from this second up-down counter is converted into speed data. .

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 1 is a block diagram showing an embodiment of the digital position detection method according to the present invention.

In the figure, 1 is a resolver that is a position detector using a phase modulation signal, 2 is a waveform shaper that shapes the output of the resolver 1 into a rectangular wave of a digital signal, and 3 is a phase and a waveform shaper of the output signal from the resolver 1. 4 is a pulse gate that uses the output of this digital phase comparator 3 to turn on and off the pulse train; 5 is an up/down counter that counts the output pulse train from this pulse gate 4; 6 is a digital phase comparator that compares the phase of the reference signal; An up/down counter counts and holds the output pulse train from the pulse gate 4. 7 is a differentiator that generates a signal to reset the up/down counter 6 at the edge of the reference signal. 8 converts the data from the up/down counter 6 into speed data. A conversion table for conversion, 9 is an adder, 1° is a ring counter, 11 is a crystal oscillator, and 12 is a two-phase exciter.

Next, the operation of the embodiment shown in FIG. 1 will be explained.

First, a ring counter 1 whose source oscillation is a crystal oscillator 11 is used.
One of the zero outputs is input to the adder 9, and the other is input to the two-phase exciter 12. Then, a sine wave signal (SINωt) from this two-phase exciter 12.

The cosine wave signal (COSωt) excites the resolver 1 and generates a rotating magnetic field within the resolver. The output signal from the resolver 1 is shaped into a digital rectangular wave by a waveform shaper 2 and input to a digital phase comparator 3. This digital phase comparator 3 compares the phase of the output from the resolver 1 and the reference signal S from the adder 9, and if the phase is out of phase, outputs the deviated phase as a pulse width T to the pulse gate 4. This pulse gate 4 outputs a clock pulse CP corresponding to this pulse width. CLK is a high speed clock pulse. The clock pulse CP drives an up/down counter 5, and the up/down counter 5 converts the data into parallel digital data. Note that thick arrows mean parallel digital data. One of the outputs of the up/down counter 5 is used as a digital position output, and the other is input to an adder 9, which adds the data from the ring counter 10 to the topmost pit of the addition result. is output as the reference signal S.

On the other hand, the output signal from the pulse gate 4 is input to an up/down counter 6, and the phase difference is converted into a parallel digital data value. The up/down counter 6 is reset by the differential waveform of the reference signal S, and the digital value of the phase difference is counted every output cycle of the resolver 1. This digital count value is input to the conversion table 8 and output as digital speed data.

Next, the operation will be explained in more detail with reference to FIG. 1 and FIG.

Figure 2 is a time chart when detecting position data, where R indicates the output of the waveform shaper 2, S is the reference signal, T is the pulse width generator, CLK is the high speed clock pulse, and CP is the output of the waveform shaper 2. The clock pulse, A, represents digital parallel data.

Now, the excitation signal of resolver 1 is SINωt, cosω
If t, the output from resolver 1 is 5IN (ω is 10') −−−−−−−−−−−−−
-----------(1). However, θ is the rotation angle of the resolver from the reference position.

When the resolver 1 moves by θ from the reference position, the phase of the output R of the waveform shaper 2 shifts by 0 minutes as shown in FIG. At this time, since the reference signal S cannot follow immediately, a phase shift occurs between the output R of the waveform shaper 2 and the reference signal SK. This phase difference becomes a pulse width T and is output from the digital phase comparator 3. Then, the pulse gate 4 takes the logical product of this pulse width T and the high-speed clock pulse CLK, converts the pulse width into a clock pulse CP, and outputs the clock pulse CP.

By counting this clock pulse CP with an up/down counter 5, the resolver 10 rotation angle θ is output as digital parallel data A.

On the other hand, since this digital parallel data A is added with the data of the ring counter 10 in the adder 9, the reference signal S
is out of phase by θ and matches the phase of the output signal from the resolver 1 in the next period. In this way, the output R of the waveform shaper 2 and the reference signal S are controlled so that they always match in phase.

Next, a case where the resolver is rotating at a constant speed will be explained with reference to FIG.

FIG. 3 is a time chart when detecting speed data. In FIG. 3, the same reference numerals as in FIG. 2 indicate corresponding parts, B is data from the up/down counter 6, C is output data from the conversion table 8, and D is a differential signal.

The part where the clock pulse CP is output based on the phase difference θ between the output R of the waveform shaper 2 and the reference signal S is as explained in FIG. 2. By the way, since the resolver 1 rotates at a constant speed, the output R of the waveform shaper 2 will be shifted by lθ in the next cycle as well.

In this way, the phase shifts by lθθ one after another.

Since the up/down counter 5 cumulatively counts the pulses of θ, it is possible to output the rotational position of Δθ correctly as digital data.

On the other hand, the up/down counter 6 counts Δθ, and in the next cycle, it is reset once by the differential signal DK from the differentiator T and then starts counting, so that the value of Δθ is always counted.

Here, according to equation (1), the resolver is rotating at a constant speed.

Here, a description will be given with reference to FIG. 4, which is a time chart of the speed detection algorithm.

First, when the resolver 1 is stopped, the cycle of the solid line waveform is t. Next, the period when the resolver 1 is rotating at a constant speed is t'.

The waveform at this time is shown by a dotted line. Here t' is t'=t-2
Δθ −−−−−−−−−−−−−−−−−−(3
) holds true.

Then Therefore, from this equation (5), t t' t get. Then, by substituting equation (3), we get

It is uniquely determined if

Therefore, velocity data can be obtained by preparing a conversion table that satisfies the above equation (6).

C in FIG. 3 represents the output data of the conversion table 8.

Note that although the above explanation has been given using a resolver as an example, the present invention is not limited to this, and it goes without saying that it can be applied to any position detector that performs phase modulation. be.

〔Effect of the invention〕

As explained above, the digital position detector of the present invention has
By configuring the digital phase comparator, pulse gate, up/down counter, differentiator, and conversion table with digital elements, a stable and inexpensive position detector can be constructed.
Furthermore, since the speed data can be easily extracted as digital data, there is an advantage that it can be easily connected to a digital control device using a microcomputer.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the digital position detection method according to the present invention, and FIGS. 2 and 3 are time charts and speed data when detecting position data to explain the operation of FIG. 1. FIG. 4 is a time chart of a speed detection algorithm, and FIG. 5 is a block diagram showing an example of a conventional position detection method. 1... Resolver, 2... Waveform shaper, 3...
・Digital phase comparator, 4...Pulse gate, 5
, 6...up/down counter, T...differentiator, 8...conversion table, 9...adder, 10...
Fist...Ring counter, 11...Crystal oscillator, 12
...Two-phase exciter. \Tadashi 1

Claims (1)

[Claims] In a position detection method including a control system that changes the phase of a reference signal based on a phase difference between an output signal from a position detector using a phase modulation signal and a reference signal, and makes it follow the phase of the output signal, the position detector a digital phase comparator that compares the phase of the output signal from the reference signal with the phase of the reference signal; a pulse gate that uses the output of the digital phase comparator to turn on and off the pulse train; and a first pulse gate that counts the output pulse train from the pulse gate. an up-down counter, a second up-down counter that counts and holds the output pulse train from the pulse gate, a differentiator that generates a signal that resets the second up-down counter at an edge of the reference signal; A digital position detection method characterized by having a conversion table for converting data from an up/down counter into speed data.