JPH01194443A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To shield a salient-electrode from an alpha-ray and to reduce a variation in the threshold voltage of a complementary MISFET by forming an alpha-ray shielding film on the complementary MISFET forming region of a semiconductor chip when the element is formed by a lift-off technique on a bipolar transistor forming region. CONSTITUTION:In the region of a memory circuit RAM of a mixed semiconductor chip 21 having a bipolar transistor and a complementary MISFET and/or the region of a circuit formed of a complementary MISFET, an alpha-ray shielding film 22 is formed on a passivation film 21AB. The film 22 is so formed as to shield an alpha-ray radiated from a radioactive element (U, Th) generation source containing a small amount mainly in a salient-electrode 8. The film 22 is formed of a polyimide series resin film, such as a polyimide-isoindoloquinazolinedione film. The film 22 is formed on a region except a region formed with the electrode 8. Since the film 22 has different thermal expansion coefficient from that of the semiconductor substrate 21A of the chip 21, the film 22 is not brought into contact with the electrode 8 due to the damage or breakdown of the electrode 8 by a thermal stress.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a technique that is effective when applied to a semiconductor device having a conductor film on a substrate.

[Prior art]

In a semiconductor device currently being developed by the present inventor, a mother chip on which a plurality of semiconductor chips are mounted is sealed with a base substrate and a sealing cap. This semiconductor device is 1, for example RA
M (Random Access Mem.

It is used as a RAM module in which a plurality of semiconductor chips containing RY) are mounted on a mother chip.

Semiconductor chips are bonded using so-called face-down bonding (Controlled Collapses) using protruding electrodes.
It is mounted on the mother chip using the eBonding method.

One end side of the protruding electrode is connected to the external terminal (
The other end is connected to the terminal of the mother chip. The protruding electrodes are formed of solder deposited using a metal mask.

This type of semiconductor device is described, for example, in Nikkei Electronics, published by Nikkei McGraw-Hill, September 24, 1984, pages 265 to 294.

[Problem to be solved by the invention]

The present inventor has considered forming a protruding electrode that connects the semiconductor chip and the mother chip using a lift-off technique, and is conducting basic research thereon. A protruding electrode formed by lift-off technology can be formed with higher precision than a protruding electrode formed using a metal mask. In other words, the riff 1-off technique is characterized in that it is possible to form protruding electrodes at high density and to achieve high integration of semiconductor devices.

The manufacturing technology currently being developed by the present inventor is as follows.

First, a photoresist film is applied over the entire surface of the mother chip, including the terminals. After baking the photoresist film, the photoresist film on the terminals of the mother chip is removed by development to form an opening.

Next, solder is deposited on the photoresist film and on the terminals in the openings.

Next, the photoresist film is removed using a stripping solution, and the solder in the opening remains to form a protruding electrode.
Remove the solder on the photoresist film. That is, the protruding electrodes are formed by a lift-off technique using a photoresist film.

However, as a result of basic research conducted by the present inventors, it has been found that in areas where protruding electrodes are densely present, the stripping solution easily penetrates into the photoresist film through the openings during the lift-off process, and the photoresist film can be stripped well. In areas where protruding electrodes were absent or sparsely present, peeling failures of the photoresist film occurred frequently. According to the inventor's analysis, approximately 1 [mm"]
In the case where no protruding electrode is present as described above, the stripping solution does not reliably penetrate into the photoresist film, resulting in poor stripping of the photoresist film.

This defective peeling of the photoresist film occurs not only when protruding electrodes are formed on the mother chip side, but also when protruding electrodes are formed on the semiconductor chip side.6 In particular, in DRAM (Dynamic RAM) and SRAM.
Semiconductor chips with built-in (Static RAM) have protrusions on the memory cell array that makes up the majority of the chip to prevent soft errors from occurring due to alpha rays generated from trace amounts of radioactive elements (U and Th) contained in solder. No electrode was provided, and peeling failures of the photoresist film occurred frequently in this area. In addition, in a mixed semiconductor chip having a bipolar transistor and a complementary MISFET, since the threshold voltage of the complementary MISFET fluctuates due to the alpha rays generated from a radioactive element, the complementary MISFET is mixed.
No protruding electrode was provided in the ET region, and peeling failures of the photoresist film frequently occurred in this region.

The object of the invention is to provide bipolar transistors and complementary M
In a semiconductor device in which protruding electrodes are formed on a semiconductor chip having an ISFET by a lift-off technique, there is provided a technique capable of improving the removability of a resist film in an area where the protruding electrodes are not formed or an area where the protruding electrodes are sparse. There is a particular thing.

Another object of the present invention is to achieve the above object and to reduce fluctuations in the threshold voltage of a complementary MISFET caused by α rays generated from a small amount of radioactive element contained in the protruding electrode. Our goal is to provide the technology that is possible.

Another object of the present invention is to provide a technique capable of achieving the above object and preventing damage or destruction of the protruding electrode.

Another object of the present invention is to provide a technique that can reduce the number of manufacturing steps required to achieve the above object.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

Means for Solving Problem C] Among the inventions disclosed in this application, a brief overview of typical inventions is as follows.

A method for manufacturing a semiconductor device, comprising forming a protruding electrode on the surface of the bipolar transistor formation region of a mixed semiconductor chip having a bipolar transistor and a complementary MISFET by lift-off technology, the method comprising: forming a protruding electrode on the surface of the bipolar transistor formation region of the semiconductor chip, An α-ray shielding film is formed on the surface of the semiconductor chip, a first resist film is formed on the α°-ray shielding film, and a second resist film is formed on the entire surface of the semiconductor chip including the first resist film and the bipolar transistor formation region. A resist film is formed, a first opening for forming a protruding electrode is formed in the bipolar transistor forming region of the second resist film, and a dummy protruding electrode is formed in the complementary MISFET forming region of the second resist film. forming an opening;
depositing a metal film to form a protruding electrode over the entire surface of the semiconductor chip including on the surface of the semiconductor chip in the first opening, on the first resist film and on the second resist film in the second opening;
removing each of the second resist film and the first resist film,
A protruding electrode is formed by leaving the metal film in the first opening, and the metal film on the second resist film and the dummy protruding electrode on the first resist film are removed.

[For production]

According to the above-described means, a second opening for forming a dummy protruding electrode is formed in the complementary MISFET formation region, and the stripping liquid is actively infiltrated into the second resist film through the second opening. Complementary MIS that does not form protruding electrodes
The removability of the second resist film in the FET formation region can be improved.

Further, the α-ray shielding film shields α-rays from the protruding electrode,
Since fluctuations in the threshold voltage of the complementary MISFET can be reduced, deterioration of the characteristics of the complementary MISFET over time can be reduced.

In addition, an α-ray shielding film is formed in the area where the protruding electrode is not formed to separate the α-ray shielding film and the protruding electrode, and damage to the protruding electrode due to the difference in thermal expansion coefficient between the α-ray shielding film and the semiconductor chip can be avoided. Alternatively, since destruction can be prevented, the electrical reliability of the semiconductor device can be improved.

Hereinafter, the configuration of the present invention will be explained along with one embodiment.

In addition, in all the figures for explaining the embodiment, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

[Embodiments of the invention]

(Example I) This Example I is the first example of the present invention in which the present invention is applied to an example in which protruding electrodes are formed on the mother chip side in a semiconductor device in which a plurality of semiconductor chips are mounted on the mother chip. be.

FIG. 1 (schematic partial sectional view) shows the structure of a semiconductor device which is a first embodiment of the present invention.

As shown in FIG. 1, the semiconductor device 1 includes a mother chip (mounting substrate) on which each of a plurality of semiconductor chips 2.3 is mounted.
4 is sealed with a base substrate 5, a frame 7, and a sealing cap 6.

Each of the semiconductor chips 2.3 is mounted on the mother chip 4 with a protruding electrode 8 interposed therebetween. Semiconductor chips 2 and 3 each use the face-down bonding method (
or CCB method) is mounted on the mother chip 4. As shown in FIG. 2 (plan view of the mother chip), the mother chip 4 includes one semiconductor chip (logic LSI) 2 having a logic function and eight semiconductor chips (memory LSI) 3 having memory functions. It is equipped with. Since the semiconductor element forming surfaces of each of the semiconductor chips 2 and 3 are configured to face the mounting surface of the mother chip 4, each of the semiconductor chips 2 and 3 shown in FIG. 2 faces the semiconductor element forming surface. The back side is visible.

As shown in FIG. 2, the semiconductor chip (logic LSI) 2 has a logic circuit section Logic arranged in the center. The logic circuit section has basic cells made up of one or more semiconductor elements arranged regularly in a matrix. The basic cell and the semiconductor element of the basic cell are:
They are connected by multiple layers of wiring to form a predetermined logic circuit. That is, the semiconductor chip 2 configures a predetermined logic function using a so-called gate array method. The semiconductor chip 2 of this embodiment is composed of three wiring layers, and a predetermined logic circuit is mainly composed of the first and second layer wiring, and the third layer wiring is mainly composed of the first and second layer wiring. Used as power wiring. Logic circuit section L
The semiconductor element constituting the basic cell of OGIC is a bipolar transistor.

A peripheral circuit including an input circuit Din, an output circuit D out, and a power supply circuit VC is arranged around the semiconductor chip 2 . Input circuit Din, output circuit Dout,
Semiconductor elements constituting each of the power supply circuits VC are connected mainly by first-layer and second-layer wiring, similarly to the logic circuit section Logic. The semiconductor elements constituting the peripheral circuit are bipolar transistors like the logic circuit section Logic.

A specific structure of a bipolar transistor constituting each of the logic circuit section Logic and the peripheral circuit of the semiconductor chip 2 is shown in FIG. 3 (a sectional view of the main part).

As shown in FIG. 3, the bipolar transistor is formed on the main surface of a p-type semiconductor substrate 2A made of single crystal silicon. Bipolar transistor has a semiconductor substrate of 2A%
It is electrically isolated from other regions by an isolation region consisting of a p'' type semiconductor region 2D and an element isolation insulating film 2E.

The semiconductor region 2D is formed between the semiconductor substrate 2A and the type 1 pitaxial layer 2B grown on the surface thereof. In other words, the semiconductor region 2D is a buried semiconductor region.

The element isolation insulating film 2E is formed on the main surface of the epitaxial layer 2B so as to reach the semiconductor region 2D. The element isolation insulating film 2E is formed of a silicon oxide film obtained by oxidizing the main surface of the epitaxial layer 2B.

The bipolar transistor has an n-type collector region C,
np consisting of a p-type base region B and an n-type emitter region E
It is composed of n-type.

The collector region C is composed of an n'' type semiconductor region 2C, an epitaxial layer 2B, and a potential raising n'' type semiconductor region 2F.Semiconductor region 2C is composed of a semiconductor substrate 2A and an epitaxial layer 2B, similar to the semiconductor region 2D. This is a buried semiconductor region provided between the semiconductor region 2F and the semiconductor region 2F of the collector region C. The semiconductor region 2F is provided on the main surface of the epitaxial layer 2B so as to reach the semiconductor region 2C.
A first layer wiring 2N is connected to the first layer through a connection hole 2M formed in the interlayer insulating film 2L. The wiring 2N is formed of an aluminum film or an aluminum film doped with Cu or Si. Cu reduces stress migration. Si reduces the occurrence of alloy spikes.

The base region B is composed of a p-type semiconductor region 2G provided on the main surface of the epitaxial layer 2B that constitutes the collector region C. A wiring 2N is connected to the semiconductor region 2G, which is the base region B.

The emitter region E is composed of an n° type semiconductor region 2H provided on the main surface of the semiconductor region 2G constituting the base region B. Semiconductor region 2H which is emitter region E
An emitter electrode 2K is connected to the insulating film 2 through a connection hole 2J formed in the insulating film 2. The emitter electrode 2 is formed of a polycrystalline silicon film doped with n-type impurities (P or As). The semiconductor region 2H is the emitter electrode 2K.
It is formed by diffusing the n-type impurity introduced into the semiconductor region 2G. Although not shown, the polycrystalline silicon film forming the emitter electrode 2K constitutes wiring, resistance elements, etc. in other regions. Similarly, a wiring 2N is connected to the emitter electrode 2K.

A second layer wiring 2Q is provided above the first layer wiring 2N with an interlayer insulating film 20 interposed therebetween. Further, a third layer wiring 2T is provided above the second layer wiring 2Q with an interlayer insulating film 2R interposed therebetween. As described above, the semiconductor chip 2 has a three-layer wiring structure. The wiring 2N and the wiring a2Q are connected through a connection hole 2P formed in the interlayer insulating film 20. The wiring 2Q and the wiring 2T are connected through a connection hole 2S formed in the interlayer insulating film 2R. Each of wiring 2Q and 2T is wiring 2N.
made of similar materials. Interlayer insulation film 2L, 2o
, 2R are formed mainly from a silicon oxide film.

The passivation film 2U is on the upper layer of the third layer wiring 2T.
is provided. The passivation film 2U is formed of, for example, a silicon nitride film deposited by plasma CVD.

The third layer wiring 2T constitutes an external terminal (ponding pad) BP on each circuit of the peripheral circuit and on the logic circuit section Logic drawn out from each circuit of the peripheral circuit. As shown in Fig. 3, the wiring 2T becomes one external terminal BP.
An opening 2v is formed in the upper passivation film 2U. There is an opening 2v on the wiring 2T which is the external terminal BP.
A barrier metal layer 2W is provided therethrough. The barrier metal layer 2W is composed of a composite film in which Cr, Cu, and Au are sequentially laminated. Cp is 1200-1500r]
Form the film with a thickness of approximately Cu is formed to a thickness of about 5,000 to 7,000 [people]. Au is formed to a thickness of about 700 to 1,100 mm. Wiring 2T which is external terminal BP
is configured to be connected to one end of a protruding electrode 8 formed on the mother chip 2 side with a barrier metal layer 2W interposed therebetween.

The semiconductor chip (memory LSI) 3 is composed of an SRAM. The semiconductor chip 3, as shown in FIG.
A memory cell array MARY is arranged in the central portion. A plurality of memory cells are arranged in rows and columns in the memory cell array MARY.

The memory cell, as shown in FIG. 4 (equivalent circuit diagram of the memory cell), is a Schottky barrier type composed of bipolar transistors. This memory cell is
It is configured within an area defined by a word aWL and a data holding line HL extending in the column direction, and a complementary digit line DL and a line (2).

That is, the memory cell includes two parasitic npn bipolar transistors Tr, two reverse npn bipolar transistors Tr, two Schottky barrier diodes SBD, two memory cell resistors RH, and two low voltage transistors Tr. It consists of a resistor RL.

In the peripheral area of the semiconductor chip 3, as shown in FIG.
Input circuit Din, output circuit Dout, @, source circuit V
C, address buffer circuit AB, X driver circuit XD
A peripheral circuit including a Y driver circuit YD and a Y driver circuit YD are arranged. The semiconductor elements constituting each circuit of this peripheral circuit are bipolar transistors. Although not shown, the bipolar transistors forming the semiconductor chip (memory LSI) 3 and the bipolar transistors forming the semiconductor chip (logic LSI) 2 have substantially the same structure.

The semiconductor chip 3 has a 2M wiring structure (two layers of aluminum wiring). The external terminal BP is composed of second layer wiring. External terminal BP is configured on each peripheral circuit. The external terminal BP is not formed on the memory cell array MARY in order to reduce soft errors caused by α rays generated from trace amounts of radioactive elements (U and Th) contained in the protruding electrodes 8. A memory cell composed of bipolar transistors is more resistant to α-ray soft errors than a memory cell composed of MISFETs, but the external terminal BP is not formed on the memory cell array MARY in order to improve the margin against soft errors.

The mother chip 4 is constructed as shown in FIGS. 2 and 5 (cross-sectional views of main parts of the mother chip). In the mother chip 4, a first layer wiring 4C is provided on the surface of a silicon substrate 4A with an interlayer insulating film 4B interposed therebetween. The silicon substrate 4A is a semiconductor chip (single crystal silicon substrate 2A)2.
There is no difference in the coefficient of thermal expansion between the three types, and the thermal conductivity is good. The interlayer insulating film 4B is formed of a silicon oxide film obtained by oxidizing the main surface of the silicon substrate 4A.

The wiring 4C is formed of an aluminum film or an aluminum film doped with Si.

A second layer wiring 4G is provided on the first layer wiring 4C with interlayer insulating films 4D and 4E interposed therebetween. Wiring 4
G is formed of substantially the same material as the wiring 4C. Wiring 4G and wiring 4C are connected through connection holes 4F formed in interlayer insulating films 4D and 4E. Interlayer insulation film 4
D is mainly used as an etching stopper layer, and is formed of, for example, a silicon nitride film deposited by plasma CVD. The glabellar insulating film 4E is mainly configured to electrically isolate the wiring 4C and the wiring 4G, and is formed of, for example, a silicon oxide film deposited by sputtering. Connection hole 4
F is formed by performing isotropic wet etching on the interlayer insulating film 4E and performing anisotropic dry etching on the interlayer insulating film 4D.

A passivation film 4H and a fourth layer are provided on the second layer wiring 4G. The passivation film 4H is formed of, for example, a silicon nitride film.

The passivation film 4I is formed of, for example, a silicon oxide film.

The second layer wiring 4G constitutes an internal terminal P□ in a predetermined area in the center of the mother chip 4, as shown in FIG. The internal terminal P1 is configured to be connected to each external terminal BP of the semiconductor chip 2.3 with a protruding electrode 8 interposed therebetween. A barrier metal layer 4K is provided on the wiring 4G constituting the internal terminal P1 through the passivation film 4H and the opening 4J formed in the passivation film 4H. The semiconductor chip 2 is in the barrier metal layer 4.
．． It has substantially the same structure (Au/Cu/Cr) as the barrier metal layer 2W provided on the surface of each external terminal BP of No. 3. The opening 4J is formed by isotropic wet etching. A protruding electrode 8 is provided on the barrier metal layer 4.

The second layer wiring 4G constitutes an external terminal P2 in a predetermined area around the mother chip 4. An opening 4L formed in the passivation films 4H and 4I is provided on the wiring 4G constituting the external terminal P2. The opening 4L is configured to connect the bonding wire 12 to the wiring 4G forming the external terminal P2.

The opening 4L is formed by subjecting the passivation film 4I to isotropic wet etching.

As will be described in detail later, the protruding electrode 8 is connected to the wiring 4 constituting the internal terminal P of the mother chip 4 using a lift-off technique.
A barrier metal layer 4K is interposed on G. In other words, the other end of the protruding electrode 8 is connected to the internal terminal P1.

The protruding electrode 8 is formed of solder (solder protruding electrode).

As shown in FIG. 1, the mother chip 4 is mounted on the base substrate 5 with an adhesive metal layer 9 interposed therebetween. The base substrate 5 is made of, for example, a silicon carbide substrate, and is characterized by having a small difference in coefficient of thermal expansion with respect to the mother chip 4 and good heat conduction. The adhesive metal layer 9 is, for example, A
It is made of U-8N alloy.

A beam 10 is provided at the periphery of the base substrate 5 and between the base substrate 5 and the frame 7. Lead 10 is
It is fixed to the base substrate 5 and the frame body 7 with a low melting point glass 11, respectively. The lead 10 is made of, for example, Fe--Ni alloy (4270).

The inner lead part of the lead 10 is the bonding wire 1
2 is connected to the wiring 4G, which is the external terminal P2 of the mother chip 4.

The bonding wire 12 is made of aluminum. The bonding wire 12 is connected to the inner lead portion of the lead 10, the wire 14G constituting the external terminal P2 of the mother chip 4, respectively, by ultrasonic bonding.

Mother chip 4 on which semiconductor chips 2 and 3 are mounted, inner lead portions of leads 10 and bonding wires 12
is hermetically sealed with a sealant 14. For example, silicone gel is used as the sealant 14. Silicone gel is formed by the potting method.

The base substrate 5 and the frame 7 are fixed with a low melting point glass 11, and the frame 7 and the sealing cap 6 are fixed with an adhesive 13. For example, silicone rubber is used as the adhesive 13. The frame body 7 is made of mullite, for example. The sealing cap 6 is made of, for example, a ceramic material.

A radiation fin 16 is provided on the back surface of the base substrate 5 (the back surface facing the mounting surface of the mother chip 4) with an adhesive 15 interposed therebetween. The radiation fin 16 is a semiconductor chip 2.3
are installed to release the heat generated in each to the outside. For example, silicone rubber is used as the adhesive 15.

The outer lead portion of the lead 10 is formed into an L-shape. Although not shown, a solder layer is provided on the surface of the outer lead portion. The outer lead portion is connected to a wiring board (baby board) 17.

Next, a method for forming the mother chip 4 and the protruding electrodes 8 of the semiconductor device 1 will be briefly explained using FIGS. 6 to 15 (cross-sectional views of main parts shown for each manufacturing process).

First, a silicon substrate 4A is prepared. After this, silicon substrate 4A
An interlayer insulating film 4B is formed on the entire surface.

The interlayer insulating film 4B is formed of a silicon oxide film formed by oxidizing the surface of the silicon substrate 4A. The interlayer insulating film 4B is, for example, 1
．． It is formed with a film thickness of about 1 to 1.3 [μml].

Next, as shown in FIG. 6, a first layer wiring 4C is formed on the interlayer insulating film 4B. The wiring 4C is formed of an aluminum (AM-8i) film deposited by sputtering, and has a thickness of 1.8~
It is formed with a film thickness of about 2.2 [μm].

The wiring 4C is patterned by isotropic wet etching. That is, the wiring 4C is formed so that the step shape of the side wall can be relaxed and the step coverage of the upper layer wiring can be improved.

Next, interlayer insulating films 4D and 4 are formed on the entire surface of the substrate including on the wiring 4C.
Each of E is sequentially laminated. Since the glabellar insulating film 4D is used as an etching stopper layer, it is formed to have a different etching rate from that of the interlayer insulating film 4E. The interlayer insulating film 4D is formed of, for example, a silicon nitride film deposited by plasma CVD, and has a thickness of about 0.4 to 0.6 μm. The interlayer insulating film 4E is formed so as to sufficiently electrically isolate the wiring 4C from the wiring layer above it. The interlayer insulating film 4E is formed of, for example, a silicon oxide film deposited by sputtering, and has a thickness of about 3.4 to 3.6 [μm].

Next, as shown in FIG. 7, the interlayer insulating films 4D and 4E on the wiring 4C, which will be the connecting portion with the upper layer wiring, are removed to form a connection hole 4F. The contact hole 4F can be formed by performing isotropic wet etching on the interlayer insulating film 4E and performing anisotropic dry etching on the interlayer insulating film 4D. In forming the connection hole 4F, since the interlayer insulating film 4D is used as an etching stopper layer, the amount of etching of the interlayer insulating film 4E, which has a sufficiently thick film thickness, can be easily controlled. In addition, connection hole 4
Since the interlayer insulating film 4E is etched by isotropic wet etching, the step shape can be relaxed and the step coverage of the upper layer wiring can be improved.

Next, as shown in FIG. 8, the wiring 4 is passed through the connection hole 4F.
A second layer wiring 4G is formed on the interlayer insulating film 4E so as to be connected to C. The wiring 4G is not only a wiring for transmitting signals, but also an internal terminal P1 and an external terminal P2 of the mother chip 4.
The 6 wirings 4G forming each of the wirings 4C are similar to the wirings 4C.

It is formed from an aluminum (AQ-8i) film deposited by sputtering, and has a thickness of about 2.4 to 2.6 [μm]. The wiring 4G is patterned by isotropic wet etching.

Next, a passivation film 4H is formed over the entire surface of the substrate including on the wiring 4G. The passivation film 4H is formed of a silicon nitride film deposited by plasma CVD, for example, and has a thickness of 0.4
It is formed with a film thickness of about 0.6 [μm].

Next, a passivation film 4 is formed over the entire surface of the substrate including over the wiring 4G and over the passivation film 4H. The passivation film 42 is formed of, for example, a silicon oxide film deposited by sputtering, and has a thickness of about 3.4 to 3.6 μm. Thereafter, as shown in FIG. 9, the passivation film 42 on the internal terminal P1 forming region of the wiring 4G is removed to form an opening 4J. The opening 4J is formed by subjecting the passivation film 4I to isotropic wet etching. Next, the passivation film 4H is opened by dry etching.

Next, as shown in FIG. 10, a barrier metal layer 4K is formed inside the opening 4J and on the internal terminal P1 formation region of the wiring 4G. The barrier metal layer 4 includes Cr, Cu.
, Au are sequentially laminated. Cr is formed by vapor deposition or sputtering to a thickness of about 1200 to 1500 [people]. Cu is formed by vapor deposition or sputtering, and
It is formed with a film thickness of about 0 to 7000 [people]. Au is formed by vapor deposition or sputtering to a film thickness of about 700 to 1100 mm. The barrier metal layer 4 is patterned by, for example, a combination of isotropic wet etching and anisotropic dry etching.

Next, as shown in FIG. 11, the external terminal P2 of the wiring 4G
The passivation film 4I on the formation region is removed to form an opening 4L. The opening 4L has substantially the same structure as the opening 4J. That is, the opening 4L is formed by subjecting the passivation film 4H to isotropic wet etching.

Next, although not shown, a back grinding process is performed on the back surface of the silicon substrate 4A, and a barrier metal layer is formed on the surface that has been subjected to this process. This barrier metal layer has substantially the same structure as the barrier metal layer 4. After that, Au is deposited on the surface of the barrier metal layer on the back surface of the silicon substrate 4A. This Au layer connects the mother chip 4 to the base substrate 5.
It becomes part of the adhesive metal layer 9 when it is adhered to.

Next, a lift-off is performed to form the protruding electrode 8.

That is, first, as shown in FIG. 12, a first resist film 18 is formed on the passivation film 4I in a region of the mother chip 4 where the protruding electrodes (conductor film) 8 are not formed. The first resist film 18 is formed in the area shown in FIG. 16 (a plan view of the mother chip showing the formation area of the protruding electrodes and dummy protruding electrodes).

That is, in the area where the semiconductor chip (logic LSI) 2 is mounted, the protruding electrodes 8 are formed in the logic circuit area and the peripheral circuit area, so excluding these areas, the passivation film in the area between them is A first resist film 18 is formed on the fourth layer. In the area where the semiconductor chip (memory LSI) 3 is mounted, the protruding electrode 8 is formed in the peripheral circuit area, so excluding that area, the passivation film 4 in the memory cell array MARY area is
A first resist film 18 is formed on the process. Since the protruding electrode 8 is not formed in the area where the semiconductor chips 2 and 3 are not mounted, the first resist film 18 is formed on the passivation film 4I in the entire area.

The first resist film 18 is formed of a photosensitive resist film, for example, polymethyl methacrylate (monomer type), and has a
．． It is formed with a film thickness of about 0 [μm]. First resist film 1
After coating the entire surface of the substrate, No. 8 is baked at a temperature of about 120 [° C.], and after exposing a predetermined portion to light, development is performed to leave only the region where the protruding electrode 8 is not formed.

Next, as shown in FIG. 13, a second resist film is applied to the entire surface of the substrate, including on the passivation film 4, which is the area where the protruding electrode 8 is to be formed, and on the second resist film 19, which is the area where the protruding electrode 8 is not formed. form 19. Second resist film 1
9 is formed with a two-storey structure in which a film resist film 19B is laminated on the surface of a base resist film 19A.

The base resist film 19A can be used with the film resist film 19B as a base even when there is a step shape due to the wiring a4c and the wiring 4G, a step shape due to the connection hole 4F and the opening 4J, and a step shape at the end of the first resist film 18. It is formed to fit closely together. In other words, the base resist film 19A is
It is configured to prevent the film resist film 19B from peeling off from the base. Base resist fi19A
is a photosensitive resist film made of the same material as the first resist film 18, for example, polymethyl methacrylate, and has a thickness of 3.4 to 3.
．． It is formed with a film thickness of about 6 [μm]. Base resist film 1
9A can be formed by coating the entire surface of the substrate and then baking it at a temperature of about 120['C].

The film resist film 19B is formed to have a large thickness in order to obtain the height necessary for the protruding electrode 8.

The film resist film 19B is formed of a photosensitive resist film made of the same material as the first resist film 18 and the base resist film 19A, for example, polymethyl methacrylate, and has a thickness of 30 to 4
It is formed with a film thickness of about 0 [μm]. Although not shown,
A cover film (about 20 [μm] thick) as a protective film is provided on the surface of the film resist film 19B after the film resist film 19B is exposed to light and before development. The film resist film 19B is formed by thermocompression lamination on the surface of the base resist film 19A.

Next, as shown in FIG. 14, a first opening 20A is formed in the portion of the second resist film 19 where the protruding electrode 8 is to be formed (above the internal terminal P0), and the protruding electrode 8 of the second resist film 19 is A second opening 20B for forming the dummy protruding electrode 8A is formed in a region where the dummy protrusion electrode 8A is not formed (on the first resist film 18). Each of the first opening 20A and the second opening 20B can be formed by exposing the second resist film 19 to light and then developing it. The first openings 20A are formed, for example, at intervals of about 200 to 300 [tt m ]. The first openings 20A forming the protruding electrodes 8 are formed at high density in order to provide multiple terminals. On the other hand, the second openings 20B are formed at intervals equal to or larger than the first openings 20A. The second openings 20B do not need to be formed densely compared to the first openings 20A, and l! In order to improve the fabrication yield, it is preferable to form them at slightly larger intervals.However, in order to ensure that each of the first resist film 18 and the second resist film 19 is peeled off and no peeling defects occur. At least one first opening 20A or second opening 20B is provided within a range of about 1 [mm''].

Next, as shown in FIG. 15, a metal film (conductor film) 8B is formed on the entire surface of the substrate on the second resist film 19.

The metal film 8B uses solder deposited by vapor deposition.

The solder is formed of, for example, 95% by weight of Pb and 5% by weight of Sn. The metal film 8B has a thickness of, for example, 15 to 100[
[mu]m] (this film thickness corresponds to the height of the protruding electrode 8). By forming this metal film 8B on the entire surface of the substrate, the first opening 20 of the second resist film 19
In A, a protruding electrode 8 can be formed on the surface of the barrier metal layer 4 on the wiring 4G, which is the internal terminal P. This protruding electrode 8 is formed as shown by the circle mark (partially omitted and shown by the mark) in FIG. 16. Further, a dummy protruding electrode 8A can be formed on the first resist film 18 within the second opening 20B of the second resist film 19 (in a region where the protruding electrode 8 is not formed).

The dummy protruding electrode 8A is formed as shown in FIG. 16 by the mark (partially omitted and shown by the mark).

Next, each of the second resist film 19 and the first resist film 18 is removed. This removal is carried out using a stripping solution such as methylene chloride. If necessary, ultrasonic treatment may be performed during removal. Each of the base resist film 19A, film resist film 19B, and first resist film 18 of the second resist film 19 is
Since they are formed of the same photosensitive resist film, they can be peeled off in a second peeling process. Since the first openings 20A are densely formed in the region where the protruding electrodes 8 are to be formed, the stripping liquid can sufficiently penetrate into the second resist film 19, as shown by the arrow A in FIG. can. In addition, in the region where the protruding electrode 8 is not formed, the second openings 20B forming the dummy protruding electrodes 8A are formed as densely as or close to the first openings 20A, so that the arrow A shown in FIG. As shown in , the stripping liquid can sufficiently penetrate into the second resist film 19 and the first resist film 18 .

By removing each of the second resist film 19 and the first resist film 18, the protruding electrode 8 formed on the wiring 4G, which is the internal terminal P□, with the barrier metal layer 4K interposed remains. , the dummy protruding electrode 8A on the first resist film 18 and the metal film 8B on the second resist film 19 can be removed.

A completed view of the mother chip 4 in which the protruding electrodes 8 are reflowed after the protruding electrodes 8 are formed is shown in FIG. 5.

Reflow is performed at a temperature of about 340 to 350['C].

In this method of manufacturing the semiconductor device 1, in which the protruding electrodes (conductor film) 8 are formed on the surface of the mother chip 4 by lift-off technology, the protruding electrodes (conductor film) 8 are formed on the surface of the mother chip 4 in areas where the protruding electrodes 8 are not formed. A first resist film 18 is formed, a second resist film 19 is formed on the entire surface of the mother chip 4 including the first resist film 18 and the region where the protruding electrodes 8 are formed, and the protruding electrodes of the second resist film 19 are formed. A first opening 20A for forming the protruding electrode 8 is formed in the region where the protruding electrode 8 is formed, and a dummy protruding electrode (dummy conductor film) 8A is formed in the region of the second resist film 19 where the protruding electrode 8 is not formed.
An opening 20B is formed, and the entire surface of the mother chip 4 including the surface of the mother chip 4 in the first opening 20A, the top of the first resist film 18 and the top of the second resist film 19 in the second opening 20B. A metal film 8B is deposited on the second resist film 19, and each of the second resist film 19 and the first resist film 18 is removed to leave the protruding electrode 8 in the first opening 20A, and the metal film 8B on the second resist film 19 is removed. Film 8B and first resist film 1
By removing the dummy protruding electrode 8A on the second resist film 19, a second opening 20B in which the dummy protruding electrode 8A is formed is formed in a region of the second resist film 19 where the protruding electrode 8 is not formed. Since the stripping solution was actively infiltrated into the second resist film 19 through the
It is possible to improve the releasability of the region where the protruding electrode 8 is not formed.

In addition to the above means, each of the second resist film 18 and the second resist film 19 may be formed of the same material, and each of the first resist film 18 and the second resist film 19 may be formed after the metal film 8B is deposited. By peeling and removing in the same process, in addition to the above effects, the first resist film 18 can be removed in the process of removing the second resist film 19. The manufacturing process of the semiconductor device 1 can be reduced by an amount equivalent to .

Furthermore, by forming the second resist film 19 with a two-layer structure in which a film resist film 19B is formed on a base resist film 19A having excellent fluidity, the first resist film 19
It is possible to reduce the step shape caused by the formation of the metal film 8B and improve the adhesion between the base and the film resist film 19B.
It is possible to prevent peeling defects in which the film resist film 19B peels off before the peeling process of the first resist film 9 and the first resist film 18, and improve manufacturing yield.

Next, the assembly process of the semiconductor device 1 will be briefly explained using FIGS. 17 to 20 (schematic cross-sectional views of the semiconductor device shown for each assembly process).

First, as shown in FIG. 17, each of the semiconductor chips 2 and 3 is mounted (chip mounted) on the mother chip 4 with the protruding electrodes 8 interposed therebetween. As described above, the protruding electrodes 8 are formed on the mother chip 4 side, and by subjecting the protruding electrodes 8 to reflow, each of the semiconductor chips 2.3 and the mother chip 4 can be connected and fixed. As mentioned above, the reflow is performed at a temperature of about 340 to 350['C].

Next, the mother chip 4 is mounted on the base substrate 5.

The baize substrate 5 and the mother chip 4 are fixed to each other by an adhesive metal layer 9. As mentioned above, the adhesive metal layer 9 has A u −
Use Sn alloy.

Next, as shown in FIG. 18, a frame 7 is attached to the peripheral portion of the base substrate 5. When installing this frame 7,
Leads 10 are attached between the base substrate 5 and the frame body 7 at the same time. The frame 7 and leads 10 are attached to the base substrate 5 using low melting point glass 11.

Next, the external terminal P2 of the mother chip 4 is connected to the inner lead portion of the lead 10 using a bonding wire 12. Bonding is performed using an ultrasonic bonding method.

Next, as shown in FIG. 19, the mother chip 4, semiconductor chip 2.degree. 3, and bonding wires 12 within the area defined by the frame 7 are hermetically sealed with a sealant 14. Sealing material 14
uses silicone gel. The silicone gel is applied by the botting method and then cured by Beta.

Next, the sealing cap 6 is attached to the frame body 7 with an adhesive 13 interposed therebetween. When attaching the sealing cap 6, the inside of the cavity formed by the base substrate 5, the frame 7, and the sealing cap 6 is kept in a vacuum state.

Next, a solder layer is formed on the surface of the outer lead portion of the lead 10. This solder layer is formed by dipping it in a solder bath.

Next, as shown in FIG. 20, the outer lead portion of the lead 10 is cut from the frame of the lead frame and molded into a predetermined shape.

Next, the radiation fins 16 are attached to the back surface of the base substrate 5 with an adhesive 15 interposed therebetween. By attaching this radiation fin 16, the semiconductor device 1 is completed.

Next, the semiconductor device 1 is mounted on the wiring board 17 as shown in FIG.

Note that in the above embodiment I, the mother chip 4 of the semiconductor device 1
Although an example has been described in which the protruding electrode 8 is formed on the internal terminal P1 side of the semiconductor chips 2 and 3, in the present invention, the protruding electrode 8 may be formed on the external terminal BP side of each of the semiconductor chips 2 and 3.

(Example ■) This example ■ uses bipolar transistors and complementary MI
Mixed semiconductor chip (B
This is a second embodiment of the present invention in which the present invention is applied to an i-CMO8) semiconductor chip having a memory function.

FIG. 21 (semiconductor chip layout diagram) shows the configuration of a semiconductor chip of a semiconductor device which is Embodiment 2 of the present invention.

As shown in FIG. 21, the mixed semiconductor chip 21 includes a logic circuit section Logic in the center and a memory circuit section RAM in the upper and lower sides, respectively. An input circuit Din and an output circuit Dou are provided at the left and right peripheral portions of the semiconductor chip 21, respectively.
t and a power supply circuit VC are arranged.

The logic circuit section Logic of the semiconductor chip 21 is composed of semiconductor elements mainly composed of complementary MISF'ETs. The memory circuit section RAM is composed of an SRAM, and is composed of semiconductor elements mainly including MISFETs. The peripheral circuit is composed of semiconductor elements mainly consisting of bipolar transistors. In addition, as for the peripheral circuits, the output circuit Dout, which particularly requires driving power, is composed of a bipolar transistor, and the input circuit Din is composed of a complementary MISFE transistor.
It may be composed of T.

The specific structure of each semiconductor element constituting the semiconductor chip 21 is shown in FIG. 22 (a cross-sectional view of main parts). On the left side of Figure 22 is a bipolar transistor, in the center is a p-channel MISFET, and on the right is an n-channel MISFET.
are shown respectively.

As shown in FIG. 22, the semiconductor chip 21 is constructed by growing an epitaxial layer 21B on the main surface of a p-type semiconductor substrate 21A made of single crystal silicon.

The bipolar transistor Tr includes a semiconductor substrate 21A, a buried p° type semiconductor region 21D, and a P' type semiconductor region 21.
It is electrically isolated from other regions by an isolation region made of G and an element isolation insulating film 21H. Semiconductor region 21D
is formed between the semiconductor substrate 21A and the epitaxial layer 21B. The bipolar transistor Tr is of an npn type and includes an n-type collector region, a p-type base region B, and an n-type emitter region E.

The collector region C includes a buried n° type semiconductor region 21C,
N-type well region 21E, potential raising go-type semiconductor region 2
It consists of 11. Semiconductor region 2 of collector region C
11 is connected to the first layer m21U through connection holes 21T formed in interlayer insulating films 21P and 21S. Is the wiring 21U an aluminum film?

It is formed of an aluminum film doped with Cu or Si.

The base region B is composed of a p-type semiconductor region 21J provided on the main surface of the well region 21E.

A wiring 21U is connected to the semiconductor region 21J, which is the base region B.

The emitter region E is an n° type semiconductor region 21 provided on the main surface of the semiconductor region 21J constituting the base region B.
It consists of. An emitter electrode 21M is connected to the semiconductor region 21K, which is the emitter region E. The emitter electrode 21M is formed of a first layer polycrystalline silicon film into which n-type impurities are introduced. The n-type impurity introduced into the emitter electrode 21M is added to the semiconductor region 21.
It is formed by being diffused into 1J. A wiring 21U is connected to the emitter electrode 21M.

The complementary MISFET p-channel MISFETQp is
It is formed on the main surface of the well region 21E in a region surrounded by the element isolation insulating film 21H.

MISFETQP is composed of a well region 21E, a gate insulating film 21L, a gate electrode 21M, and a pair of p° type semiconductor regions 210 that are a source region and a drain region.

The gate insulating film 21L is formed of a silicon oxide film formed by oxidizing the main surface of the well region 21E.

The gate electrode 21M is formed of a polycrystalline silicon film doped with n-type impurities.

The semiconductor region 210 is formed by introducing a p-type impurity (eg, B) by ion implantation.

Since the channel forming region side of the semiconductor region 210 is configured with a low impurity concentration, the MISFETQP has a low impurity concentration.
(Lightly Doped rain) structure. A wiring 21U is connected to the semiconductor region 210.

Complementary MISFET n-channel MISFETQn is
In the region surrounded by the element isolation insulating film 21H, p-
It is formed on the main surface of the mold well region 21F. MISF
ETQn includes a well region 21F, a gate insulating film 21L,
It is composed of a gate electrode 21M and a pair of go-type semiconductor regions 21N, which are a source region and a drain region. MIs
FETQn has an LDD structure similar to MISFETQp.

Wiring 2 is connected to one semiconductor region 21N of MISFETQn.
1U is connected. In the other semiconductor region 21N,
Through the connection hole 21Q formed in the interlayer insulating film 21P,
Wiring 21R, high resistance load element 21R2, wiring 21R3
are connected sequentially. Wiring 21R work, wiring 21
Each of R3 is formed by introducing an n-type impurity into the second layer polycrystalline silicon film. In the memory circuit RAM, the wiring 21R1 is used as a power wiring for supplying a power supply voltage (for example, a circuit operating voltage of 5 [V]) Vcc to the memory cells. The high resistance load element 21R2 is formed by introducing no impurities into the polycrystalline silicon film or by introducing some n-type or p-type impurities into the polycrystalline silicon film.

A second layer wiring 21X is provided on the wiring 21U with an interlayer insulating film 21V interposed therebetween. The wiring 21X is connected to the wiring 21 through the connection hole 21W formed in the interlayer insulating film 21V.
Connected to U. A third layer wiring 21AA is provided on the wiring 1IA21X with an interlayer insulating film 21Y interposed therebetween. The wiring 21AA is connected to the wiring 21X through a connection hole 21Z formed in the interlayer insulating film 21Y. Each of the second layer wiring 21X and the third layer wiring 21AA is formed of the same material as the first layer wiring 21U, for example. In this way, the semiconductor chip 21 has a three-layer wiring structure.

A passivation film 21AB is provided on the third layer wiring 21AA. Passivation film 21A
B is formed of, for example, a silicon nitride film deposited by sputtering.

In the area of the memory circuit RAM of the semiconductor chip 21 or the area of the circuit composed of complementary MISFETs (for example, the logic circuit unit Logic or the input circuit Din), an α-ray shielding film 22 is formed on the passivation films 21A and 21B. is provided. Although not shown in FIG. 22, the α-ray shielding film 22 is configured to shield α-rays mainly generated from radioactive elements (U and Th) contained in trace amounts in the protruding electrodes 8. has been done. The α-ray shielding film 22 is formed of a polyimide resin film, for example, a polyimide iso-indolo-quinazoline-dione film. The α-ray shielding film 22 is formed to have a thickness of, for example, about 10 to 30 [μm].

The memory circuit RAM of the semiconductor chip 21 is composed of an SRAM as described above, and the memory cells of this SRAM are constructed as shown in FIG. 23 (equivalent circuit diagram of memory cells).

As shown in FIG. 23, memory cells of the SRAM are arranged at intersections between complementary data lines DL, DL extending in the row direction and word lines WL extending in the column direction. This memory cell is constructed of a high resistance load type.

The memory cell is composed of a flip-flop circuit used as an information storage section and two transfer MISFETs Qt whose semiconductor regions are connected to a pair of input/output terminals. The other semiconductor region of the transfer MISFET Qt is connected to the complementary data line DL. MIS for transfer
The gate electrode of FETQt is connected to word line WL. This transfer MISFET Qt is composed of the n-channel MISFET Qn shown in FIG. 22 above.

The flip-flop circuit is composed of two high resistance load elements R and two driving MISFETs Qd. The high resistance load element R is the high resistance load element 2 shown in FIG.
1R, (polycrystalline silicon film). Drive MI
SFETQd is an n-channel MISF shown in FIG.
It is formed of ETQn. A power supply voltage VCC is applied to one end of the high resistance load element R (to which the wiring 21R3 is connected). A reference voltage (for example, a circuit reference potential o [vl) V, is applied to the semiconductor region 21N used as a source region of the driving MISFET Qd.

The mixed semiconductor chip 21 configured in this way has a second
As shown in FIG. 4 (a sectional view of a semiconductor chip), a protruding electrode 8 is provided on the external terminal BP.

In other words, the protruding electrode 8 is arranged in a region on the peripheral circuit made up of the bipolar transistor Tr. The protruding electrode 8 is not formed on the mounting substrate side on which the semiconductor chip 21 is mounted, but is formed on the external terminal BP side of the semiconductor chip 21 in this embodiment (2).

When the α rays emitted from the protruding electrode 8 enter the semiconductor substrate 21A, they generate minority carriers, and these minority carriers change the potential of the information charge storage section (node) of the SRAM memory cell, causing soft errors. Therefore, the protruding electrode 8 is not provided at least on the memory circuit RAM. Also,
The minority carrier is MISFETQn, MISFET
Each gate insulating film 21L and gate insulating film 21L of Qp
The complementary MISF
No protruding electrode 8 is provided on the circuit mainly composed of ET. That is, the protruding electrode 8 is not formed on the memory circuit RAM, on the logic circuit section Logic made up of complementary MISFETs, and on the circuit made up of complementary MISFETs among the peripheral circuits. In the region where the protruding electrode 8 is not formed, the α-ray shielding film 22 is provided on the passivation film 21AB. Bipolar transistor Tr is MISFET
Since it is more resistant to α-ray soft errors than Qn and Qp, an α-ray shielding film 2 is provided on the region of the bipolar transistor Tr.
2 is not provided.

Further, the α-ray shielding film 22 is provided in a region other than the region where the protruding electrode 8 is formed. Since the α-ray shielding film 22 has a different coefficient of thermal expansion from the semiconductor substrate 21A of the semiconductor chip 21, α
If the radiation shielding film 22 and the protruding electrodes 8 come into contact, the protruding electrodes 8 will be damaged or destroyed by thermal stress caused by the operation of the semiconductor chip 21, so the α-ray shielding film 22 and the protruding electrodes 8 are not brought into contact.

The protruding electrode 8 is formed by a lift-off method substantially similar to that in Example 2 above. Since the α-ray shielding film 22 is provided on the passivation film 21AB, the first resist film 18 of the lift-off method has α-ray shielding film 22 as shown by the dotted line in FIG.
It is formed on the line shielding film 22.

The first resist film 18 is formed on the area where the protruding electrode 8 is not formed, that is, on the area of the memory circuit RAM, and on the logic circuit area Lo.
They are formed on the gic region and on the peripheral circuit region composed of complementary MISFETs.

A second resist film 19 (not shown) is formed in the region where the protruding electrode 8 is formed and on the first resist film 18 .

A first opening 20A is formed in the region of the second resist film 19 where the protruding electrode 8 is formed, and a second opening 20B is formed on the first resist film 18 of the second resist film 19. A protruding electrode 8 is formed within the first opening 20A, and a dummy protruding electrode 8A is formed within the second opening 20B. Then, by leaving the protruding electrode 8 in the first opening 20A and removing the second resist film 19, the second resist film 19, and the dummy protruding electrode 8A in the second opening 20B, the present embodiment The semiconductor device is completed.

In this way, bipolar transistor Tr and complementary type M
A protruding electrode 8 is provided on the surface of the bipolar transistor Tr forming region of the mixed semiconductor chip 21 having an ISFET.
A manufacturing method of a semiconductor device in which an α-ray shielding film 22 is formed on the surface of a complementary MISFET formation region of the semiconductor chip 21 by a lift-off technique, and a first resist is formed on the α-ray shielding film 22. A film 18 is formed, and this first film 18 is formed.
On the resist film 18 and the bipolar transistor Tr
A second resist film 19 is formed on the entire surface of the semiconductor chip 21 including the formation region, and a first opening 20A for forming the protruding electrode 8 is formed in the bipolar transistor Tr formation region of the second resist film 19. 2 resist film 19
A second opening 20B for forming the dummy protruding electrode 8A is formed in the complementary MISFET formation region, and the first opening 2
On the surface of the semiconductor chip 21 within 0A, the second opening 2
On the first resist film 18 and the second resist film 19 in 0B
A metal film 8B for forming protruding electrodes 8 is deposited on the entire surface of the semiconductor chip 21 including the top, and the second resist film 19 and the first
Each of the resist films 18 is removed, the metal film 8B in the first opening 20A is left to form a protruding electrode 8', and the metal film 8B on the second resist film 19 and the metal film 8B on the first resist film 18 are removed. By removing the metal film 8B (dummy protruding electrode 8A), a second opening 20B for forming the dummy protruding electrode 8A is formed in the complementary MISFET formation region, and a second resist film is formed through the second opening 20B. 19
Since the stripping solution is actively infiltrated, the stripping property of the second resist film 19 in the complementary MISFET formation region where the protruding electrode 8 is not formed can be improved.

Further, by forming the α-ray shielding film 22 on the complementary MISFET formation region of the semiconductor chip 21.

Since the α-ray shielding film 22 can shield α-rays from the protruding electrode 8 and reduce fluctuations in the threshold voltage of the complementary MISFET, it is possible to reduce the deterioration of the characteristics of the complementary MISFET over time. can.

Further, by separating the α-ray shielding film 22 and the protruding electrode 8, damage or destruction of the protruding electrode 8 due to the difference in thermal expansion coefficient between the α-ray shielding film 22 and the semiconductor chip 21 is prevented. Therefore, the electrical reliability of the semiconductor device can be improved.

Furthermore, by not forming the α-ray shielding film 22 made of polyimide resin in the region where the protruding electrode 8 is formed, the protruding electrode 8 can be processed independently without being affected by the poor workability of the α-ray shielding film 22. Therefore, the density of the protruding electrodes 8 can be increased.

Further, the present invention is a method for manufacturing a semiconductor device, in which a protruding electrode 8 is formed by a lift-off technique on the surface of the peripheral circuit formation region of a semiconductor chip 21 having a memory function, which is constituted by a memory circuit portion RAM and a peripheral circuit.

An α-ray shielding film 22 is formed on the surface of the formation region of the memory circuit RAM of the semiconductor chip 21, and this d-ray shielding film 22
A first resist film 18 is formed on the top of the semiconductor chip 21 , a second resist film 19 is formed on the entire surface of the semiconductor chip 21 including on the first resist film 18 and on the peripheral circuit forming area, and A first opening 20A for forming the protruding electrode 8 is formed in the peripheral circuit forming region, and a second opening 20B for forming the dummy protruding electrode 8 is formed in the forming region of the memory circuit RAM of the second resist film 20B. , said first
On the surface of the semiconductor chip 21 in the opening 20A, the second
Protruding electrodes 8 are provided on the entire surface of the semiconductor chip 21 including on the first resist film 18 and on the second resist film 19 in the opening 20B.
A metal film 8B is deposited to form the second resist layer 1.
9. Remove each of the first resist films 18 and open the first openings 2.
The protruding electrode 8 is formed by leaving the metal film 8B in A, and the metal film 8B on the second resist film 19 and the metal film 8B on the first resist film 18 (dummy protruding electrode 8A) is formed.
), a second opening 20B is formed in which a dummy protruding electrode 8A is formed in the formation region of the memory circuit RAM.
was formed and the stripping liquid was actively infiltrated into the second resist film 19 through the second opening 20B, so that the protruding electrode 8
It is possible to improve the removability of the second resist film 19 in the region where the memory circuit portion RAM is not formed.

In addition, by forming the α-ray shielding film 22 in the formation region of the memory circuit RAM of the semiconductor chip 21, the α-ray shielding film 22
2 can block α rays from the protruding electrode 8, so soft errors caused by α rays can be reduced.

Note that in the present invention, the memory circuit section RAM may be configured with a DRAM. A DRAM memory cell is composed of an n-channel MISFET for memory cell selection and an information storage capacitive element connected in series to one of the semiconductor regions.

Further, in the present invention, the protruding electrodes 8 may be provided on the internal terminals of the mounting board on which the semiconductor chip 21 is mounted.

(Example ■) This example (■) is an example of the present invention in which the present invention is applied to a semiconductor device having wiring mainly made of Cu formed on the surface of a wiring board, such as a mother chip, a wiring board, or a printed wiring board. This is the third embodiment.

25 (a plan view of the main parts of the semiconductor device during the lift-off process) and FIG. 26 (the plan view shown in FIG. 25 is taken along the BB cutting line). (cross-sectional view taken at ).

As shown in FIGS. 25 and 26, a wiring board 23A constituting a semiconductor device has a wiring 23G extending therebetween with an interlayer insulating film 23B interposed therebetween. The wiring board 23A is formed of a silicon carbide substrate, a single crystal silicon substrate, a ceramic substrate, an epoxy resin substrate, or a polyimide resin substrate. The wiring 23C is mainly composed of Cu or an alloy containing Cu formed by lift-off, or a composite film in which another metal film is formed on Cu, that is, Cu.

Isotropic wet etching (chemical etching) is possible for Cu, but anisotropic dry etching is difficult, so it is not possible to form wiring in a fine shape. can be formed by law.

The wiring 23C can be formed by a lift-off method that is substantially the same as the lift-off method in Example I.

First, in a region where the wiring 23C is not formed, the first resist film 18 is formed on the wiring substrate 23A with the interlayer insulating film 23B interposed therebetween.

Next, a second resist film 19 is formed on the first resist film 18 in the area where the wiring 23G is to be formed and in the area where the wiring 23C is not to be formed.

Next, the second resist film 1 in the area where the wiring 23C is to be formed.
At the same time, a first opening (groove) 20A is formed in 9.

A second opening 20B is formed in the second resist film 19 in a region where the wiring 23G is not formed.

Next, a metal film 23E mainly composed of Cu is deposited on the entire surface of the wiring board 23A, and the interlayer insulating film 23E is deposited on the entire surface of the wiring board 23A.
A dummy wiring 23D is formed on the first resist film 18 in the second opening 20B, and a metal film 23E is formed on the second resist film 19.

Next, the second resist film 19 and the first resist film 18 are each removed to leave the wiring 23C in the first opening 20A, and the dummy wiring 23D on the first resist film 18 and the second resist film 19 are removed. The upper metal film 23E is removed.

Although the dummy wiring 23D has a circular shape in plan view in this embodiment (2), the dummy wiring 23D may have a rectangular shape in a plan view according to the present invention.

In this method of manufacturing a semiconductor device, the wiring 23C mainly made of Cu is formed on the surface of the wiring board 23A, and the wiring 23G is not formed in a region where the wiring 23C is formed on the surface of the wiring board 23A. A first resist film 18 is formed in the area, and a second resist film 18 is formed on the entire surface of the wiring board 23A including the first resist film 18 and the area where the wiring 23C is formed.
A resist film 19 is formed, and a first opening 20A for forming the wiring 23C is formed in the region of the second resist film 19 where the wiring 23C is formed.
A second opening 20B in which a dummy wiring 23D is formed is formed in a region where dummy wiring 23D is not formed.
Metal film 23E forming wiring 23G on the entire surface of wiring board 23A including on resist film 18 and second resist film 19
are deposited, and the second resist film 19 and the second resist film 1 are deposited.
9 are removed, and the metal film 23E in the first opening 20A is removed.
The metal film 23E on the second resist film 19 and the first resist film 18 are formed by leaving the metal film 23C on the second resist film 19.
By removing the upper dummy wiring 23D, the first opening 20 of the second resist film 19 is opened based on the lift-off technique.
Wiring 2 mainly made of Cu with accuracy equivalent to the processing dimensions of A
3C, it is possible to form the wiring 23C with fine dimensions without using a dry process, and also form the second opening 20B in which the dummy wiring 23D is formed in the region where the wiring 23C is not formed. And this second
Since the stripping liquid is actively infiltrated into the second resist film 19 through the opening 20B, it is possible to improve the stripping properties of the second resist film 19 in areas where the wiring 23G is not formed.

Although the invention made by the present inventor has been specifically explained above based on the above-mentioned embodiments, the present invention is not limited to the above-mentioned embodiments, and can be modified in various ways without departing from the gist thereof. Of course you can get it.

For example, the present invention is not limited to wiring mainly made of Cu, but can also be applied to the case where aluminum wiring is formed in areas where the wiring densities are significantly different.

Furthermore, the present invention can be applied to a semiconductor device equipped with a semiconductor chip mainly composed of MISFETs.

〔Effect of the invention〕

A brief overview of representative inventions among the inventions disclosed in this application is as follows.

In a semiconductor device in which a protruding electrode is formed by a lift-off technique on a semiconductor chip having a bipolar transistor and a complementary MISFET, the removability of a resist film in a complementary MISFET formation region where the protruding electrode is not formed can be improved.

Furthermore, fluctuations in the threshold voltage of the complementary MISFET can be reduced, and the electrical reliability of the semiconductor device can be improved.

[Brief explanation of the drawing]

FIG. 1 is a schematic partial cross-sectional view showing the structure of a semiconductor device according to Embodiment 2 of the present invention. FIG. 2 is a plan view of the mother chip of the semiconductor device, FIG. 3 is a cross-sectional view of a main part of the semiconductor chip of the semiconductor device, and FIG. 4 is a diagram of a memory cell with a storage function built into the semiconductor chip. Equivalent circuit diagram, FIG. 5 is a sectional view of the main part of the mother chip, FIGS. 6 to 15 are sectional views of the main part shown for each manufacturing process of the mother chip and the protruding electrodes, and FIG. 16 is a sectional view of the main part of the mother chip. FIG. 3 is a plan view of the mother chip showing regions where the protruding electrodes and dummy protruding electrodes are formed. 17 to 20 are schematic cross-sectional views showing each assembly process of the semiconductor device; FIG. 21 is a layout diagram showing the configuration of a semiconductor chip of a semiconductor device that is an uninvented embodiment U; FIG. 23 is an equivalent circuit diagram showing an SRAM memory cell built into the semiconductor chip, and FIG. 24 is a sectional view showing the structure of each semiconductor element constituting the semiconductor chip. FIG. 25 is a schematic cross-sectional view of the chip, and FIG. 26 is a plan view of the main part during the lift-off process of the substrate constituting the semiconductor device according to the embodiment (2) of the present invention. FIG. - It is a sectional view cut along the B cutting line. In the figure, 1... semiconductor device, 2, 3. 21... semiconductor chip, 4... mother chip, 5... base substrate,
6'... Sealing cap, 7... Frame body, 8... Protruding electrode (conductor [), 8A... Dummy protruding electrode, 18...
...Second resist film, 19...Second resist film, 19
A... Base resist film, 19B... Film resist film, 20A... First opening, 20B... Second opening, 22... α-ray shielding film, 23C... Wiring, 23D
. . . dummy wiring, Tr . . . bipolar transistor, Q . . . MI S FET.

Claims (1)

[Scope of Claims] 1. A method for manufacturing a semiconductor device in which a protruding electrode is formed on the surface of the bipolar transistor formation region of a mixed semiconductor chip having a bipolar transistor and a complementary MISFET by a lift-off technique, the method comprising: a step of forming an α-ray shielding film on the surface of the complementary MISFET formation region; a step of forming a first resist film on the α-ray shielding film; and a step of forming a first resist film on the first resist film and the bipolar transistor formation region. forming a second resist film over the entire surface of the semiconductor chip including the top, forming a first opening for forming a protruding electrode in the bipolar transistor formation region of the second resist film, and forming a complementary MISFET of the second resist film; A second process for forming dummy protruding electrodes in the formation region.
a step of forming an opening, and a metal film for forming a protruding electrode on the entire surface of the semiconductor chip, including on the surface of the semiconductor chip in the first opening, on the first resist film and on the second resist film in the second opening. Depositing the second resist film and the first resist film, respectively, leaving the metal film in the first opening to form a protruding electrode, and removing the metal film on the second resist film and the first resist film. 1. A method for manufacturing a semiconductor device, comprising the step of removing a dummy protruding electrode on a resist film. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the protruding electrode is formed of solder. 3. The semiconductor device according to claim 1 or 2, wherein each of the first resist film and the second resist film is formed of photosensitive polymethyl methacrylate. Production method. 4. The method of manufacturing a semiconductor device according to claim 1, wherein each of the first resist film and the second resist film is removed in the same step. 5. The method of manufacturing a semiconductor device according to any one of claims 1 to 4, wherein the α-ray shielding film is a polyimide resin film.