JPH01194043A - Electronic computer - Google Patents

Abstract

PURPOSE:To rapidly execute the mishit processing of TLB by using respectively different instruction queues for normal processing and interruption processing by a control means. CONSTITUTION:When a mishit is generated in the TLB 8 during the period of normal processing, an interruption signal (c) is sent to an instruction reading mechanism 3 and an instruction queue control mechanism 7. A mishit processing instruction in the TLB 8 is read out by the mechanism 3, an enqueue signal a2 is sent from the mechanism 7 to a 1st instruction queue 2 and an instruction on an instruction bus 4 is stored in the instruction queue 2. On the other hand, '1' to be a selecting signal (b) is sent from the mechanism 7 to a multiplexer 5 and the instruction of the instruction queue 2 is sent to a decoder 6. At that time, the state of the 2nd instruction queue 1 is held as it is. Consequently, the mishit processing of the TLB can be rapidly executed without flashing the instruction queue or rereading an once read instruction.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a control method for an electronic computer, and particularly to control of interrupts caused by TLB mishits.

[Conventional technology]

Conventionally, in electronic computers with a paging mechanism, when a TLB mishit occurs, an interrupt is generated, the position of the instruction that caused the TLB mishit is memorized, reading of the instruction to execute the TLB mishit processing is started, and the instruction queue is The remaining instructions were flushed, and the TLB miss processing instructions were stored in the instruction queue. After the TLB miss processing is completed, the instructions for the original processing are stored in the read instruction queue again.

[Problem to be solved by the invention]

In the conventional computer control method described above, when an interrupt occurs due to a TLB miss, the instruction queue must be flushed, and when returning to normal processing, the flushed instructions must be read again. There were drawbacks.

[Means to solve the problem]

In order to eliminate such drawbacks, the present invention provides a method for storing mishit processing instructions read out for processing TLB misses for decoding and execution in an electronic computer that manages memory using a paging method. a first instruction queue that stores instructions for normal processing other than miss-processing instructions; The control means controls the transfer of instructions, and the control means uses different instruction queues for normal processing and interrupt processing.

[Effect]

In the electronic computer according to the present invention, in TLB miss processing, there is no need to flush the instruction queue or read out an instruction that has been read out again.

〔Example〕

The figure is a system diagram showing an embodiment of an electronic computer according to the present invention. In the figure, 1 is a second instruction queue, 2 is a first instruction queue, 3 is an instruction reading mechanism, 4 is an instruction bus,
5 is a multiplexer, 6 is a decoder, 7 is an instruction queue control mechanism as a control means, and 8 is a TLB.

During normal processing, when an instruction is sent from the instruction reading mechanism 3 via the instruction bus 4, an enqueue signal al is sent from the instruction queue control mechanism 7 to the second instruction queue 1, and the instruction is sent to the instruction queue 1. is stored in. A selection signal of "0" is sent from the instruction queue control mechanism 7 to the multiplexer 5, and the instructions in the instruction queue 1 are sent to the decoder 6.

When a miss occurs in the TLB 8 during normal processing, an interrupt signal C is sent to the instruction reading mechanism 3 and the instruction queue control mechanism 7. The instruction reading mechanism 3 reads out the instruction for miss processing from the TLB 8, the instruction queue control mechanism 7 sends an enqueue signal a2 to the first instruction queue 2, and the instructions on the instruction bus 4 are stored in the instruction queue 2. . A selection signal of "1" is sent from the instruction queue control mechanism 7 to the multiplexer 5, and the instructions in the instruction queue 2 are sent to the decoder 6. At this time, the state of the second instruction queue 1 is maintained as it is.

When the last instruction of the TLB 8 miss processing is sent to the decoder 6, an interrupt end signal d is sent from the decoder 6 to the instruction reading mechanism 3 and the instruction queue control mechanism 7. The selection signal becomes "0" and the instructions in the instruction queue 1 are sent to the decoder 6 again. In the instruction succession mechanism 3, instructions for normal processing, which are the continuation of the instructions read and sent to the instruction queue 1 before the interrupt, are read and sent to the instruction queue 1.
is stored in.

〔Effect of the invention〕

As explained above, the electronic computer according to the present invention has two instruction queues, one for normal processing and the other for TL.
By using it for mishit processing of B, T
This has the advantage that LB miss-hit processing can be performed at high speed without franchising the instruction queue or re-reading instructions that have been read out twice.

[Brief explanation of the drawing]

The figure is a system diagram showing one embodiment of the electronic computer according to the present invention. DESCRIPTION OF SYMBOLS 1... Second instruction queue, 2... First instruction queue, 3... Instruction reading mechanism, 4... Instruction bus, 5...
- Multiplexer, 6... Decoder, 7... Instruction queue control mechanism, 8... TLB. Patent applicant: NEC Corporation

Claims (1)

[Claims] In an electronic computer that manages memory using a paging method, there is provided a first instruction queue in which a mishit processing instruction read out for processing a TLB mishit is stored for decoding and execution; a second instruction queue for storing instructions for normal processing other than processing instructions; and a control means for controlling storage of instructions in the first and second instruction queues and transfer of instructions to a decoder. An electronic computer, characterized in that the control means controls so that different instruction queues are used for normal processing and interrupt processing.